1 /**************************************************************************/
2 /* File: esdpci200.c - support for ESD Electronics' CAN/PCI-200 cards */
4 /* LinCAN - (Not only) Linux CAN bus driver */
5 /* Copyright (C) 2002-2009 DCE FEE CTU Prague <http://dce.felk.cvut.cz> */
6 /* Copyright (C) 2002-2009 Pavel Pisa <pisa@cmp.felk.cvut.cz> */
7 /* Copyright (C) 2007 Manuel Bessler <m.bessler@gmx.net> */
8 /* Funded by OCERA and FRESCOR IST projects */
9 /* Based on CAN driver code by Arnaud Westenberg <arnaud@wanadoo.nl> */
11 /* LinCAN is free software; you can redistribute it and/or modify it */
12 /* under terms of the GNU General Public License as published by the */
13 /* Free Software Foundation; either version 2, or (at your option) any */
14 /* later version. LinCAN is distributed in the hope that it will be */
15 /* useful, but WITHOUT ANY WARRANTY; without even the implied warranty */
16 /* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */
17 /* General Public License for more details. You should have received a */
18 /* copy of the GNU General Public License along with LinCAN; see file */
19 /* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, */
20 /* Cambridge, MA 02139, USA. */
22 /* To allow use of LinCAN in the compact embedded systems firmware */
23 /* and RT-executives (RTEMS for example), main authors agree with next */
24 /* special exception: */
26 /* Including LinCAN header files in a file, instantiating LinCAN generics */
27 /* or templates, or linking other files with LinCAN objects to produce */
28 /* an application image/executable, does not by itself cause the */
29 /* resulting application image/executable to be covered by */
30 /* the GNU General Public License. */
31 /* This exception does not however invalidate any other reasons */
32 /* why the executable file might be covered by the GNU Public License. */
33 /* Publication of enhanced or derived LinCAN files is required although. */
34 /**************************************************************************/
36 #include "../include/can.h"
37 #include "../include/can_sysdep.h"
38 #include "../include/main.h"
39 #include "../include/sja1000p.h"
41 #ifdef CAN_ENABLE_PCI_SUPPORT
43 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10))
44 #define ioread32 can_readl
45 #define iowrite32 can_writel
46 #define ioread8 can_readb
47 #define iowrite8 can_writeb
53 #define ESDPCI200_PCI_VENDOR_ID 0x10B5
54 #define ESDPCI200_PCI_PRODUCT_ID 0x9050
56 /* PCI to local bus bridge PLX9052 */
58 #define PLX9052_INTCSR 0x4c /* interrupt control register */
59 #define PLX9052_CNTRL 0x50 /* control register, for software reset */
61 /* The ESD PCI/200 uses (per default) just LINTi1 (Local Interrupt 1)
62 * on the PLX. This means that both CAN channels' (SJA1000's) /INT pins
63 * are OR'ed to the LINTi1 pin (actually ANDed in the 74HC08 since both
64 * the SJA1000's /INT pins and the LINTi1 pin are active low).
66 * The board does have an option to route the 2nd channel to LINTi2,
67 * apparently just one or two resistors need to be added.
69 * LINTi2 is floating per default, so don't set its interrupt enable flag
70 * 'PLX9052_INTCSR_LI2EN', it'll just interrupt all the time.
72 #define PLX9052_INTCSR_LI1EN 0x00000001 /* Local Interrupt 1 enable */
73 #define PLX9052_INTCSR_LI1S 0x00000004 /* Local Interrupt 1 status */
74 #define PLX9052_INTCSR_LI2EN 0x00000008 /* Local Interrupt 2 enable */
75 #define PLX9052_INTCSR_LI2S 0x00000020 /* Local Interrupt 2 status */
76 #define PLX9052_INTCSR_PIEN 0x00000040 /* PCI Interrupt enable */
78 #define PLX9052_CNTRL_SWRESET 0x40000000 /* PCI Adapter Software Reset to Local Bus */
80 #define IO_RANGE 0x100
82 // Standard value: Pushpull (OCTP1|OCTN1|OCPOL1|OCTP0|OCTN0|OCM1)
83 #define ESDPCI200_OCR_DEFAULT_STD 0xFA
84 /* Setting the OCR register to 0xFA is a good idea.
85 This means normal output mode , push-pull and the correct polarity. */
88 void esdpci200_pci_soft_reset(struct candevice_t *candev)
90 unsigned long reg_reset;
91 reg_reset = inl( candev->res_addr+PLX9052_CNTRL);
92 reg_reset &= ~(PLX9052_CNTRL_SWRESET);
94 /* PCI Adapter Software Reset plus reset local bus */
95 outl( (reg_reset | PLX9052_CNTRL_SWRESET ), candev->res_addr+PLX9052_CNTRL);
98 outl(reg_reset, candev->res_addr+PLX9052_CNTRL);
103 void esdpci200_disconnect_irq(struct candevice_t *candev)
105 /* writing 0x0 into the PLX's INTCSR register disables interrupts */
106 /* 0x0 is also the value in the register after a power-on reset */
107 outl(0x0, candev->res_addr + PLX9052_INTCSR);
108 DEBUGMSG("disabled interrupts on the PLX\n");
111 void esdpci200_connect_irq(struct candevice_t *candev)
113 /* enable interrupts for the SJA1000's, enable PCI interrupts */
114 outl( PLX9052_INTCSR_LI1EN | PLX9052_INTCSR_PIEN,
115 candev->res_addr+PLX9052_INTCSR);
116 DEBUGMSG("enabled interrupts on the PLX\n");
119 int esdpci200_irq_handler(int irq, struct canchip_t *chip)
122 unsigned long it_reg;
123 struct candevice_t *candev;
124 candev = chip->hostdevice;
125 retcode = CANCHIP_IRQ_NONE;
126 //DEBUGMSG("Starting to handle an IRQ\n");
127 it_reg = inl(candev->res_addr+PLX9052_INTCSR);
129 if((it_reg & (PLX9052_INTCSR_LI1S | PLX9052_INTCSR_LI1EN) )
130 == (PLX9052_INTCSR_LI1S | PLX9052_INTCSR_LI1EN) )
131 { /*interrupt enabled and active */
133 for(chipnum=0; chipnum < candev->nr_sja1000_chips; chipnum++)
135 if(sja1000p_irq_handler(irq, candev->chip[chipnum]) == CANCHIP_IRQ_NONE)
136 { /* since both chips use the same IRQ and the same LINTi on the PLX,
137 we need manually do 'interrupt sharing' on the boardlevel
138 by checking all chips one-by-one */
143 retcode=CANCHIP_IRQ_HANDLED;
146 if( retcode != CANCHIP_IRQ_HANDLED )
147 {/* None of the chips felt they were responsible for this IRQ...
148 so it appears we have problems with the IRQ */
149 it_reg &= ~(PLX9052_INTCSR_LI1EN);
150 //Either we have a problem with IRQ malfunctions, or our IRQ is shared with some other device.
152 //not actually disabled, unless outl() below is uncommented
153 //outl(it_reg,(void*)(candev->res_addr+PLX9052_INTCSR));
154 //CANMSG("CAN Interrupt disabled due to malfunction\n");
160 int esdpci200_request_io(struct candevice_t *candev)
162 struct pci_dev *pcidev = candev->sysdevptr.pcidev;
163 can_ioptr_t remap_addr;
164 unsigned long bar2_addr;
166 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))
167 if(pci_request_region(pcidev, 0, "esdpci200_plx9050") != 0){
168 CANMSG("Request of esdpci200_plx9050 range failed\n");
170 }else if(pci_request_region(pcidev, 1, "esdpci200_io") != 0){
171 CANMSG("Request of esdpci200_io range failed\n");
172 pci_release_region(pcidev, 0);
174 }else if(pci_request_region(pcidev, 2, "esdpci200_sja") != 0){
175 CANMSG("Request of esdpci200_sja range failed\n");
176 pci_release_region(pcidev, 1);
177 pci_release_region(pcidev, 0);
180 #else /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
181 if(pci_request_regions(pcidev, "esdpci200") != 0){
182 CANMSG("Request of esdpci200_plx9050 regions failed\n");
185 #endif /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
188 /* ioports, PLX local configuration registers */
189 candev->res_addr=pci_resource_start(pcidev,1);
190 /*MEM window for SJA1000 chips*/
191 bar2_addr = pci_resource_start(pcidev,2);
192 candev->io_addr = bar2_addr;
193 if( ! (remap_addr=ioremap(bar2_addr,
194 pci_resource_len(pcidev,2)))) /*MEM window for SJA1000 chips*/
196 CANMSG("Unable to access I/O memory at: 0x%lx\n", (unsigned long)bar2_addr);
200 can_base_addr_fixup(candev, remap_addr);
201 CANMSG("esdpci200_sja IO-memory: 0x%lx - 0x%lx (VMA 0x%lx)\n",
202 (unsigned long) bar2_addr,
203 (unsigned long) (bar2_addr + pci_resource_len(pcidev,2) - 1),
209 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))
210 pci_release_region(pcidev, 2);
211 pci_release_region(pcidev, 1);
212 pci_release_region(pcidev, 0);
213 #else /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
214 pci_release_regions(pcidev);
215 #endif /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
219 int esdpci200_release_io(struct candevice_t *candev)
221 esdpci200_disconnect_irq(candev);
222 esdpci200_pci_soft_reset(candev);
224 iounmap(candev->dev_base_addr);
225 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))
226 pci_release_region(candev->sysdevptr.pcidev, 2);
227 pci_release_region(candev->sysdevptr.pcidev, 1);
228 pci_release_region(candev->sysdevptr.pcidev, 0);
229 #else /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
230 pci_release_regions(candev->sysdevptr.pcidev);
231 #endif /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
236 void esdpci200_write_register(unsigned data, can_ioptr_t address)
238 iowrite8((u8)data,address);
242 unsigned esdpci200_read_register(can_ioptr_t address)
244 return ioread8(address);
247 int esdpci200_reset(struct candevice_t *candev)
250 struct canchip_t *chip;
252 DEBUGMSG("Resetting esdpci200 hardware ...\n");
254 esdpci200_disconnect_irq(candev);
255 esdpci200_pci_soft_reset(candev);
257 for(chip_nr=0;chip_nr<candev->nr_all_chips;chip_nr++){
258 if(!candev->chip[chip_nr]) continue;
259 chip=candev->chip[chip_nr];
261 esdpci200_write_register(sjaMOD_RM, chip->chip_base_addr+SJAMOD);
264 cdr=esdpci200_read_register(chip->chip_base_addr+SJACDR);
265 esdpci200_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
267 esdpci200_write_register(0, chip->chip_base_addr+SJAIER);
270 esdpci200_write_register(0, chip->chip_base_addr+SJAMOD);
271 while (esdpci200_read_register(chip->chip_base_addr+SJAMOD)&sjaMOD_RM){
272 if(!i--) return -ENODEV;
274 esdpci200_write_register(0, chip->chip_base_addr+SJAMOD);
277 cdr=esdpci200_read_register(chip->chip_base_addr+SJACDR);
278 esdpci200_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
280 esdpci200_write_register(0, chip->chip_base_addr+SJAIER);
282 esdpci200_read_register(chip->chip_base_addr+SJAIR);
286 esdpci200_connect_irq(candev);
291 int esdpci200_init_hw_data(struct candevice_t *candev)
293 struct pci_dev *pcidev = NULL;
296 pcidev = pci_find_device(ESDPCI200_PCI_VENDOR_ID, ESDPCI200_PCI_PRODUCT_ID, pcidev);
297 if(pcidev == NULL) return -ENODEV;
298 } while(can_check_dev_taken(pcidev));
300 if (pci_enable_device (pcidev)){
301 printk(KERN_CRIT "Setup of ESDPCI200 failed\n");
304 candev->sysdevptr.pcidev=pcidev;
306 can_spin_lock_init(&candev->device_lock);
308 if(!(pci_resource_flags(pcidev, 0)&IORESOURCE_MEM))
310 printk(KERN_CRIT "PCI200 region %d is not MEM\n",0);
313 if(!(pci_resource_flags(pcidev, 1)&IORESOURCE_IO))
315 printk(KERN_CRIT "PCI200 region %d is not IO\n",1);
319 if(!(pci_resource_flags(pcidev,2)&IORESOURCE_MEM))
321 printk(KERN_CRIT "PCI200 region %d is not MEM\n",2);
325 /* Reset/control field - used to store port of PLX9052 control region */
326 candev->res_addr = pci_resource_start(pcidev,1);;
328 /* Physical address of SJA1000 window, stored for debugging only */
329 candev->io_addr = pci_resource_start(pcidev,2);
331 candev->aux_base_addr=NULL; /* mapped dynamically in esdpci200_request_io() */
332 candev->dev_base_addr=NULL; /* mapped dynamically in esdpci200_request_io() */
333 /*candev->flags |= CANDEV_PROGRAMMABLE_IRQ;*/
335 candev->nr_82527_chips=0;
336 candev->nr_sja1000_chips=2;
337 candev->nr_all_chips=2;
342 int esdpci200_init_chip_data(struct candevice_t *candev, int chipnr)
345 if(candev->sysdevptr.pcidev==NULL)
348 CANMSG("initializing esdpci200 chip operations\n");
351 sja1000p_fill_chipspecops(candev->chip[chipnr]);
352 candev->chip[chipnr]->chip_base_addr=candev->dev_base_addr + chipnr * IO_RANGE;
354 candev->chip[chipnr]->chipspecops->irq_handler=esdpci200_irq_handler;
356 candev->chip[chipnr]->flags = 0;
357 candev->chip[chipnr]->int_cpu_reg = 0; /* i82527 specific */
358 candev->chip[chipnr]->int_clk_reg = 0; /* i82527 specific */
359 candev->chip[chipnr]->int_bus_reg = 0; /* i82527 specific */
360 candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | sjaCDR_CLK_OFF; /* hardware specific options for the Clock Divider register */
361 candev->chip[chipnr]->sja_ocr_reg = ESDPCI200_OCR_DEFAULT_STD; /* hardware specific options for the Output Control register */
362 candev->chip[chipnr]->clock = 16000000;
363 candev->chip[chipnr]->chip_irq=candev->sysdevptr.pcidev->irq;
364 candev->chip[chipnr]->flags |= CHIP_IRQ_PCI;
365 if( chipnr > 0 ) /* only one IRQ used for both channels.
366 CHIP_IRQ_CUSTOM req'd for RTAI, since
367 registering two handlers for the same IRQ
369 candev->chip[chipnr]->flags |= CHIP_IRQ_CUSTOM;
374 int esdpci200_init_obj_data(struct canchip_t *chip, int objnr)
376 chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr;
380 int esdpci200_program_irq(struct candevice_t *candev)
386 int esdpci200_register(struct hwspecops_t *hwspecops)
388 hwspecops->request_io = esdpci200_request_io;
389 hwspecops->release_io = esdpci200_release_io;
390 hwspecops->reset = esdpci200_reset;
391 hwspecops->init_hw_data = esdpci200_init_hw_data;
392 hwspecops->init_chip_data = esdpci200_init_chip_data;
393 hwspecops->init_obj_data = esdpci200_init_obj_data;
394 hwspecops->write_register = esdpci200_write_register;
395 hwspecops->read_register = esdpci200_read_register;
396 hwspecops->program_irq = esdpci200_program_irq;
401 #endif /*CAN_ENABLE_PCI_SUPPORT*/