2 * Linux CAN-bus device driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
5 * email:pisa@cmp.felk.cvut.cz
6 * This software is released under the GPL-License.
7 * Version lincan-0.2 9 Jul 2003
10 /* This file contains the low level functions for the pcccan-1 card from Gespac.
11 * You can probably find more information at http://www.gespac.com
14 #include <linux/autoconf.h>
16 #include <linux/ioport.h>
17 #include <linux/delay.h>
18 #include <linux/sched.h>
19 #include <asm/errno.h>
23 #include "../include/main.h"
24 #include "../include/pcccan.h"
25 #include "../include/i82527.h"
28 unsigned long pcccan_base=0x0;
31 * IO_RANGE is the io-memory range that gets reserved, please adjust according
32 * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
33 * #define IO_RANGE 0x20 for sja1000 chips in basic CAN mode.
36 /* The pcccan card uses indexed addressing hence the need to only reserve
37 * eight bytes of memory.
39 * base + 1 = Address loading
40 * base + 2 = Read register
41 * base + 3 = Read register + increment loaded address (saves a write operation
42 * when accessing consecutive registers)
44 * base + 5 = Address read
45 * base + 6 = Write register
46 * base + 7 = Write register + increment loaded address
51 * pcccan_request_io: - reserve io memory
52 * @io_addr: The reserved memory starts at @io_addr, wich is the module
55 * The function pcccan_request_io() is used to reserve the io-memory. If your
56 * hardware uses a dedicated memory range as hardware control registers you
57 * will have to add the code to reserve this memory as well.
58 * %IO_RANGE is the io-memory range that gets reserved, please adjust according
59 * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
60 * #define IO_RANGE 0x20 for sja1000 chips in basic CAN mode.
61 * Return Value: The function returns zero on success or %-ENODEV on failure
64 int pcccan_request_io(struct candevice_t *candev)
66 if (!can_request_io_region(candev->io_addr,IO_RANGE,DEVICE_NAME)) {
67 CANMSG("Unable to open port: 0x%lx\n",candev->io_addr);
70 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", candev->io_addr, candev->io_addr + IO_RANGE - 1);
76 * pcccan_release_io - free reserved io-memory
77 * @io_addr: Start of the memory range to be released.
79 * The function pcccan_release_io() is used to free reserved io-memory.
80 * In case you have reserved more io memory, don't forget to free it here.
81 * IO_RANGE is the io-memory range that gets released, please adjust according
82 * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
83 * #define IO_RANGE 0x20 for sja1000 chips in basic CAN mode.
84 * Return Value: The function always returns zero
87 int pcccan_release_io(struct candevice_t *candev)
89 can_release_io_region(candev->io_addr,IO_RANGE);
95 * pcccan_reset - hardware reset routine
96 * @card: Number of the hardware card.
98 * The function pcccan_reset() is used to give a hardware reset. This is
99 * rather hardware specific so I haven't included example code. Don't forget to
100 * check the reset status of the chip before returning.
101 * Return Value: The function returns zero on success or %-ENODEV on failure
104 int pcccan_reset(struct candevice_t *candev)
108 DEBUGMSG("Resetting pcccan-1 hardware ...\n");
109 while (i < 1000000) {
111 outb(0x0,candev->res_addr);
114 /* Check hardware reset status */
116 outb(iCPU,candev->io_addr+0x1);
117 while ( (inb(candev->io_addr+0x2)&0x80) && (i<=15) ) {
122 CANMSG("Reset status timeout!\n");
123 CANMSG("Please check your hardware.\n");
127 DEBUGMSG("Chip reset status ok.\n");
136 * pcccan_init_hw_data - Initialze hardware cards
137 * @card: Number of the hardware card.
139 * The function pcccan_init_hw_data() is used to initialize the hardware
140 * structure containing information about the installed CAN-board.
141 * %RESET_ADDR represents the io-address of the hardware reset register.
142 * %NR_82527 represents the number of intel 82527 chips on the board.
143 * %NR_SJA1000 represents the number of philips sja1000 chips on the board.
144 * The flags entry can currently only be %PROGRAMMABLE_IRQ to indicate that
145 * the hardware uses programmable interrupts.
146 * Return Value: The function always returns zero
149 int pcccan_init_hw_data(struct candevice_t *candev)
151 candev->res_addr=candev->io_addr;
152 candev->nr_82527_chips=NR_82527;
153 candev->nr_sja1000_chips=NR_SJA1000;
154 candev->nr_all_chips=NR_82527+NR_SJA1000;
155 candev->flags &= ~PROGRAMMABLE_IRQ;
160 #define CHIP_TYPE "i82527"
162 * pcccan_init_chip_data - Initialize chips
163 * @card: Number of the hardware card
164 * @chipnr: Number of the CAN chip on the hardware card
166 * The function pcccan_init_chip_data() is used to initialize the hardware
167 * structure containing information about the CAN chips.
168 * %CHIP_TYPE represents the type of CAN chip. %CHIP_TYPE can be "i82527" or
170 * The @chip_base_addr entry represents the start of the 'official' memory map
171 * of the installed chip. It's likely that this is the same as the @io_addr
172 * argument supplied at module loading time.
173 * The @clock entry holds the chip clock value in Hz.
174 * The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
175 * register. Options defined in the %sja1000.h file:
176 * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
177 * The entry @sja_ocr_reg holds hardware specific options for the Output Control
178 * register. Options defined in the %sja1000.h file:
179 * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
180 * %OCR_TX0_LH, %OCR_TX1_ZZ.
181 * The entry @int_clk_reg holds hardware specific options for the Clock Out
182 * register. Options defined in the %i82527.h file:
183 * %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
184 * The entry @int_bus_reg holds hardware specific options for the Bus
185 * Configuration register. Options defined in the %i82527.h file:
186 * %iBUS_DR0, %iBUS_DR1, %iBUS_DT1, %iBUS_POL, %iBUS_CBY.
187 * The entry @int_cpu_reg holds hardware specific options for the cpu interface
188 * register. Options defined in the %i82527.h file:
189 * %iCPU_CEN, %iCPU_MUX, %iCPU_SLP, %iCPU_PWD, %iCPU_DMC, %iCPU_DSC, %iCPU_RST.
190 * Return Value: The function always returns zero
193 int pcccan_init_chip_data(struct candevice_t *candev, int chipnr)
195 candev->chip[chipnr]->chip_type=CHIP_TYPE;
196 candev->chip[chipnr]->chip_base_addr=candev->io_addr;
197 candev->chip[chipnr]->clock = 16000000;
198 candev->chip[chipnr]->int_cpu_reg = iCPU_DSC | iCPU_DMC;
199 candev->chip[chipnr]->int_clk_reg = iCLK_SL1 | iCLK_CD0;
200 candev->chip[chipnr]->int_bus_reg = iBUS_CBY | iBUS_DR1;
201 candev->chip[chipnr]->sja_cdr_reg = 0;
202 candev->chip[chipnr]->sja_ocr_reg = 0;
203 pcccan_irq=candev->chip[chipnr]->chip_irq;
204 pcccan_base=candev->chip[chipnr]->chip_base_addr;
210 * pcccan_init_obj_data - Initialize message buffers
211 * @chipnr: Number of the CAN chip
212 * @objnr: Number of the message buffer
214 * The function pcccan_init_obj_data() is used to initialize the hardware
215 * structure containing information about the different message objects on the
216 * CAN chip. In case of the sja1000 there's only one message object but on the
217 * i82527 chip there are 15.
218 * The code below is for a i82527 chip and initializes the object base addresses
219 * The entry @obj_base_addr represents the first memory address of the message
220 * object. In case of the sja1000 @obj_base_addr is taken the same as the chips
222 * Unless the hardware uses a segmented memory map, flags can be set zero.
223 * Return Value: The function always returns zero
226 int pcccan_init_obj_data(struct chip_t *chip, int objnr)
228 chip->msgobj[objnr]->obj_base_addr=(objnr+1)*0x10;
229 chip->msgobj[objnr]->flags=0;
235 * pcccan_program_irq - program interrupts
236 * @card: Number of the hardware card.
238 * The function pcccan_program_irq() is used for hardware that uses
239 * programmable interrupts. If your hardware doesn't use programmable interrupts
240 * you should not set the @candevices_t->flags entry to %PROGRAMMABLE_IRQ and
241 * leave this function unedited. Again this function is hardware specific so
242 * there's no example code.
243 * Return value: The function returns zero on success or %-ENODEV on failure
246 int pcccan_program_irq(struct candevice_t *candev)
252 * pcccan_write_register - Low level write register routine
253 * @data: data to be written
254 * @address: memory address to write to
256 * The function pcccan_write_register() is used to write to hardware registers
257 * on the CAN chip. You should only have to edit this function if your hardware
258 * uses some specific write process.
259 * Return Value: The function does not return a value
262 void pcccan_write_register(unsigned char data, unsigned long address)
264 disable_irq(pcccan_irq);
265 outb(address - pcccan_base, pcccan_base+1);
266 outb(data, pcccan_base+6);
267 enable_irq(pcccan_irq);
271 * pcccan_read_register - Low level read register routine
272 * @address: memory address to read from
274 * The function pcccan_read_register() is used to read from hardware registers
275 * on the CAN chip. You should only have to edit this function if your hardware
276 * uses some specific read process.
277 * Return Value: The function returns the value stored in @address
280 unsigned pcccan_read_register(unsigned long address)
283 disable_irq(pcccan_irq);
284 outb(address - pcccan_base, pcccan_base+1);
285 ret=inb(pcccan_base+2);
286 enable_irq(pcccan_irq);
291 /* !!! Don't change this function !!! */
292 int pcccan_register(struct hwspecops_t *hwspecops)
294 hwspecops->request_io = pcccan_request_io;
295 hwspecops->release_io = pcccan_release_io;
296 hwspecops->reset = pcccan_reset;
297 hwspecops->init_hw_data = pcccan_init_hw_data;
298 hwspecops->init_chip_data = pcccan_init_chip_data;
299 hwspecops->init_obj_data = pcccan_init_obj_data;
300 hwspecops->write_register = pcccan_write_register;
301 hwspecops->read_register = pcccan_read_register;
302 hwspecops->program_irq = pcccan_program_irq;