2 * Linux CAN-bus device driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
5 * email:pisa@cmp.felk.cvut.cz
6 * This software is released under the GPL-License.
7 * Version lincan-0.3 17 Jun 2004
9 NOTE: Please see the template.c file for the comments relating to this code.
10 Herein is the modified copy of the functions
13 #include "../include/can.h"
14 #include "../include/can_sysdep.h"
15 #include "../include/main.h"
16 #include "../include/oscar.h"
17 #include "../include/sja1000p.h"
19 #define IO_RANGE 0x80 // allow both basic CAN and PeliCAN modes for sja1000
21 int oscar_request_io(struct candevice_t *candev)
23 if (!can_request_io_region(candev->io_addr,IO_RANGE,DEVICE_NAME)) {
24 CANMSG("Unable to open port: 0x%lx\n",candev->io_addr);
27 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", candev->io_addr, candev->io_addr + IO_RANGE - 1);
32 int oscar_release_io(struct candevice_t *candev)
34 can_release_io_region(candev->io_addr,IO_RANGE);
39 int oscar_reset(struct candevice_t *candev)
42 struct canchip_t *chip=candev->chip[0];
45 oscar_write_register(sjaMOD_RM, chip->chip_base_addr+SJAMOD);
48 cdr=oscar_read_register(chip->chip_base_addr+SJACDR);
49 oscar_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
51 oscar_write_register(0, chip->chip_base_addr+SJAIER);
54 oscar_write_register(0, chip->chip_base_addr+SJAMOD);
55 while (oscar_read_register(chip->chip_base_addr+SJAMOD)&sjaMOD_RM){
56 if(!i--) return -ENODEV;
58 oscar_write_register(0, chip->chip_base_addr+SJAMOD);
61 cdr=oscar_read_register(chip->chip_base_addr+SJACDR);
62 oscar_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
64 oscar_write_register(0, chip->chip_base_addr+SJAIER);
69 int oscar_init_hw_data(struct candevice_t *candev)
71 candev->res_addr = 0x0; // RESET address?
72 candev->nr_82527_chips = 0;
73 candev->nr_sja1000_chips = 1; // We've got a SJA1000 variant
74 candev->nr_all_chips= 1;
75 candev->flags |= CANDEV_PROGRAMMABLE_IRQ;
80 int oscar_init_chip_data(struct candevice_t *candev, int chipnr)
82 // i82527_fill_chipspecops(candev->chip[chipnr]);
83 // sja1000_fill_chipspecops(candev->chip[chipnr]);
84 sja1000p_fill_chipspecops(candev->chip[chipnr]);
86 candev->chip[chipnr]->chip_base_addr = candev->io_addr;
87 candev->chip[chipnr]->clock = 12000000;
88 candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP; // we use an external tranceiver
89 candev->chip[chipnr]->sja_ocr_reg = sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH;
90 // these three int_ registers are unused (we don't have this chip)
91 candev->chip[chipnr]->int_cpu_reg = 0;
92 candev->chip[chipnr]->int_clk_reg = 0;
93 candev->chip[chipnr]->int_bus_reg = 0;
98 int oscar_init_obj_data(struct canchip_t *chip, int objnr)
100 chip->msgobj[objnr]->obj_base_addr = chip->chip_base_addr;
105 int oscar_program_irq(struct candevice_t *candev)
107 // CAN_IRQ_L (active low) interrupt: PF2 / INT2 on our LH7A400 SoC
108 // This IRQ is set up already by the kernel.
113 void oscar_write_register(unsigned data, unsigned long address)
118 unsigned oscar_read_register(unsigned long address)
123 /* !!! Don't change this function !!! */
124 int oscar_register(struct hwspecops_t *hwspecops)
126 hwspecops->request_io = oscar_request_io;
127 hwspecops->release_io = oscar_release_io;
128 hwspecops->reset = oscar_reset;
129 hwspecops->init_hw_data = oscar_init_hw_data;
130 hwspecops->init_chip_data = oscar_init_chip_data;
131 hwspecops->init_obj_data = oscar_init_obj_data;
132 hwspecops->write_register = oscar_write_register;
133 hwspecops->read_register = oscar_read_register;
134 hwspecops->program_irq = oscar_program_irq;