2 * Linux CAN-bus device driver.
3 * This software is released under the GPL-License.
6 #include "../include/can.h"
7 #include "../include/can_sysdep.h"
8 #include "../include/main.h"
9 #include "../include/hcan2.h"
14 #define DEBUGMSG(fmt,args...) can_printk(KERN_ERR "lincan (debug): " fmt,##args)
18 #define MAX_TRANSMIT_WAIT_LOOPS 20
19 #define MAX_SETTING_WAIT_LOOPS 25 /* maximal loop count while checking Chip reply to action */
20 #define MAX_IRQ_WAIT_LOOPS 25
22 void hcan2_irq_read_handler(struct canchip_t *chip, struct msgobj_t *obj);
23 void hcan2_irq_write_handler(struct canchip_t *chip, struct msgobj_t *obj);
25 void hcan2_clear_irq_flags(struct canchip_t *chip);
26 void hcan2_clear_mbox(struct canchip_t *chip, int msgobj_idx);
28 void hcan2_setup_mbox4write(struct msgobj_t * obj, struct canmsg_t * msg);
29 void hcan2_setup_mbox4write_data(struct msgobj_t * obj, struct canmsg_t * msg);
30 void hcan2_setup_mbox4read(struct msgobj_t * obj);
32 void hcan2_setup_ctrl_regs(struct canmsg_t * msg, uint16_t * ctrl0, uint16_t * ctrl1, uint16_t * ctrl2);
34 int hcan2_compare_msg(struct msgobj_t * obj, struct canmsg_t * msg);
36 /* Enable folowing IRQs
37 * HCAN2_IRR_DFRI = Data Frame Received Interrupt Flag
38 * HCAN2_IRR_MBEI = Mailbox Empty Interrupt Flag
40 uint16_t IRQs = ~(HCAN2_IRR_DFRI + HCAN2_IRR_MBEI);
41 /* 1 - mask interrupt, 0 - interrupt not masked */
43 int hcan2_chip_config(struct canchip_t *chip)
45 DEBUGMSG("Configuring chip...\n");
47 if (hcan2_enable_configuration(chip))
51 chip->baudrate=1000000;
52 if (hcan2_baud_rate(chip, chip->baudrate,chip->clock,0,75,0))
55 hcan2_config_irqs(chip, IRQs);
57 if (hcan2_disable_configuration(chip))
60 /* DEBUGMSG("Chip configured\n"); */
64 int hcan2_enable_configuration(struct canchip_t *chip)
69 DEBUGMSG("Enabling configuration...\n");
71 /* Disable interrupt */
72 can_disable_irq(chip->chip_irq);
74 /* Halt mode - disable CAN activity after completing current operation */
75 gsr = can_read_reg_w(chip, HCAN2_GSR);
76 if (gsr & (HCAN2_GSR_BOFF | HCAN2_GSR_RESET)) /* chip is already in config mode */
79 can_write_reg_w(chip, HCAN2_MCR_HALT, HCAN2_MCR);
81 /* Waits until chip enters Halt mode - finishes current TX/RX operation */
82 gsr = can_read_reg_w(chip, HCAN2_GSR);
83 while ( !(gsr & HCAN2_GSR_HSS) && ((i++) <= MAX_SETTING_WAIT_LOOPS) ) {
85 gsr = can_read_reg_w(chip, HCAN2_GSR);
88 if (i >= MAX_SETTING_WAIT_LOOPS) {
89 CANMSG("Error entering HALT mode (enable configuration) \n");
90 can_enable_irq(chip->chip_irq);
94 /* DEBUGMSG("Configuration mode is ENABLED\n"); */
98 int hcan2_disable_configuration(struct canchip_t *chip)
103 DEBUGMSG("Disabling configuration mode...\n");
105 /* Halt mode - disable CAN activity after completing current operation */
106 mcr = can_read_reg_w(chip, HCAN2_MCR);
107 gsr = can_read_reg_w(chip, HCAN2_GSR);
109 /* if configuration already disabled */
110 if (!(gsr & HCAN2_GSR_HSS) && !(mcr & HCAN2_MCR_HALT))
113 can_write_reg_w(chip, mcr & ~HCAN2_MCR_HALT, HCAN2_MCR);
115 /* Waits until chip leaves Halt mode */
116 gsr = can_read_reg_w(chip, HCAN2_GSR);
117 while ( (gsr & HCAN2_GSR_BOFF) && ((i++) <= MAX_SETTING_WAIT_LOOPS) ) {
119 gsr = can_read_reg_w(chip, HCAN2_GSR);
122 if (i >= MAX_SETTING_WAIT_LOOPS) {
123 CANMSG("Error leaving HALT mode (enable configuration) \n");
127 /* Enable interrupt */
128 can_enable_irq(chip->chip_irq);
130 /* DEBUGMSG("Configuration mode is DISABLED\n"); */
134 /* ********************************************* */
135 int hcan2_baud_rate(struct canchip_t *chip, int rate, int clock, int sjw, int sampl_pt, int flags)
137 /* Set communication parameters.
138 * param rate baud rate in Hz
139 * param clock frequency of hcan2 clock in Hz (on sh7760 most probably 27.5MHz)
140 * param sjw synchronization jump width (0-3) prescaled clock cycles
141 * param sampl_pt sample point in % (0-100) sets (TSEG1 + 1)/(TSEG1 + TSEG2 + 1) ration
142 * param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP
146 /* rate = clock / ((tseg1 + tseg2 + 1) * brp ) */
148 int best_error = 1000000000, error;
149 int best_tseg = 0, best_brp = 0, best_rate = 0, brp = 0;
150 int tseg, tseg1 = 0, tseg2 = 0; /* tseg = TSEG1 + TSEG2 + 1*/
151 uint16_t bcr0 = 0, bcr1 = 0;
153 DEBUGMSG("Seting Baud rate...\n");
155 for (tseg = TSEG_MIN; tseg <= TSEG_MAX; tseg++)
157 brp = 10 * clock/(tseg * rate);
158 brp = brp % 10 > 4 ? brp / 10 + 1: brp / 10; /* round */
160 if (brp == 0 || brp > 256)
163 error = rate - clock/(brp * tseg);
166 if (error <= best_error) {
170 best_rate = clock/(brp * tseg);
174 tseg2 = best_tseg - (sampl_pt * best_tseg)/100;
175 if (tseg2 < TSEG2_MIN) /* tseg2 <= sjw +1 , TSEG2_MIN = 4 */
177 if (tseg2 > TSEG2_MAX)
179 tseg1 = best_tseg - tseg2 - 1;
180 if (tseg1 > TSEG1_MAX) {
182 tseg2 = best_tseg - tseg1 - 1;
185 if (best_error && (rate/best_error < 10)) {
186 CANMSG("baud rate %d is not possible with %d Hz clock\n",
188 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
189 best_rate, best_brp, best_tseg, tseg1, tseg2);
193 DEBUGMSG("Setting %d bps.\n", best_rate);
194 /* DEBUGMSG("brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
195 best_brp, best_tseg, tseg1, tseg2,
196 (100 * tseg1 / best_tseg));
199 * EG = 0b0 - Resynchronization at falling edge
200 * BSP = 0b00 - bit sampling at one point (end of TSEG1)
203 bcr1 = (((tseg1 - 1) & 0x000f) << 12) + (((tseg2 - 1) & 0x0007) << 8) + ((sjw & 0x0003) << 4);
204 bcr0 = (best_brp - 1) & 0x00ff;
206 hcan2_set_btregs(chip, bcr0, bcr1);
208 hcan2_disable_configuration(chip);
210 /* DEBUGMSG("Baud rate set successfully\n"); */
214 int hcan2_set_btregs(struct canchip_t *chip, unsigned short bcr0, unsigned short bcr1)
216 /* DEBUGMSG("Seting BCR0 and BCR1.\n"); */
218 /* masks words to correct format */
222 can_write_reg_w(chip, bcr1, HCAN2_BCR1);
223 can_write_reg_w(chip, bcr0, HCAN2_BCR0);
225 /* DEBUGMSG("BCR0 and BCR1 successfully set.\n"); */
229 /* ********************************************* */
230 int hcan2_start_chip(struct canchip_t *chip)
232 /* DEBUGMSG("Starting chip %d...\n", chip->chip_idx); */
234 /* Stop chip turns chip to HALT mode - traffic on CAN bus is ignored after completing curent operation.
235 * Start chip only turn chip back from HALT state - using disable_config
237 hcan2_disable_configuration(chip);
239 DEBUGMSG("Chip [%d] started\n", chip->chip_idx);
243 int hcan2_stop_chip(struct canchip_t *chip)
245 /* DEBUGMSG("Stopping chip %d...\n", chip->chip_idx); */
247 /* Stop chip turns chip to HALT mode - traffic on CAN bus is ignored after completing curent operation.
248 * - using enable_config
250 hcan2_enable_configuration(chip);
252 DEBUGMSG("Chip [%d] stopped\n", chip->chip_idx);
256 int hcan2_attach_to_chip(struct canchip_t *chip)
258 /* DEBUGMSG("Attaching to chip %d.\n", chip->chip_idx); */
260 /* initialize chip */
262 if (hcan2_enable_configuration(chip))
265 /* Clear all Mailboxes */
266 if (hcan2_clear_objects(chip))
269 /* set Baudrate and Interrupts */
270 if (hcan2_chip_config(chip))
273 if (hcan2_disable_configuration(chip))
276 /* Enable interrupt */
277 can_enable_irq(chip->chip_irq);
278 can_enable_irq(chip->chip_irq);
280 CANMSG("Successfully attached to chip [%02d].\n", chip->chip_idx);
284 int hcan2_release_chip(struct canchip_t *chip)
286 hcan2_stop_chip(chip);
287 can_disable_irq(chip->chip_irq);
289 hcan2_clear_objects(chip);
291 DEBUGMSG("Chip released [%02d]\n", chip->chip_idx);
295 /* ********************************************* */
296 int hcan2_standard_mask(struct canchip_t *chip, unsigned short code, unsigned short mask)
298 uint16_t ctrl0, lafm0;
299 struct msgobj_t * obj;
300 int obj_idx = (int) (chip->chip_data);
302 if (code & 0x1ffff800)
303 return hcan2_extended_mask(chip, code, mask);
306 if (obj_idx > 0 && obj_idx <= 32)
307 obj = chip->msgobj[obj_idx - 1];
311 chip->chip_data = (void*)0; /* reset mbox number */
314 ctrl0 = ((code & 0x07ff) << 4);
315 lafm0 = ((mask & 0x07ff) << 4);
317 can_write_reg_w(chip, ctrl0, (int) obj->obj_base_addr + HCAN2_MB_CTRL0);
318 can_write_reg_w(chip, 0x0000, (int) obj->obj_base_addr + HCAN2_MB_CTRL1);
319 can_write_reg_w(chip, lafm0, (int) obj->obj_base_addr + HCAN2_MB_MASK);
320 can_write_reg_w(chip, 0xffff, (int) obj->obj_base_addr + HCAN2_MB_MASK + 2);
322 DEBUGMSG("Set standard_mask [id:0x%04x, m:0x%04x]\n", code, mask);
326 int hcan2_extended_mask(struct canchip_t *chip, unsigned long code, unsigned long mask)
328 uint16_t ctrl0, ctrl1, lafm0, lafm1;
330 struct msgobj_t * obj;
332 int obj_idx = (int) (chip->chip_data);
334 if (obj_idx > 0 && obj_idx <= 32)
335 obj = chip->msgobj[obj_idx - 1];
339 chip->chip_data = (void*)0; /* reset mbox number */
341 ctrl0 = ((code & 0x1ffc0000) >> 14);
342 ctrl0 |=((code & 0x00030000) >> 16);
343 ctrl0 |= HCAN2_MBCT0_IDE; /* set IDE flag */
344 ctrl1 = (code & 0x0000ffff);
346 lafm0 = ((mask & 0x1ffc0000) >> 14);
347 lafm0 |=((mask & 0x00030000) >> 16);
348 lafm1 = (mask & 0x0000ffff);
350 can_write_reg_w(chip, ctrl0, (int) obj->obj_base_addr + HCAN2_MB_CTRL0);
351 can_write_reg_w(chip, ctrl1, (int) obj->obj_base_addr + HCAN2_MB_CTRL1);
352 can_write_reg_w(chip, lafm0, (int) obj->obj_base_addr + HCAN2_MB_MASK);
353 can_write_reg_w(chip, lafm1, (int) obj->obj_base_addr + HCAN2_MB_MASK + 2);
355 DEBUGMSG("Set extended_mask [id:0x%08x, m:0x%08x]\n", (uint32_t)code, (uint32_t)mask);
360 /* ********************************************* */
361 int hcan2_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj)
363 DEBUGMSG("Pre read config\n");
365 hcan2_enable_configuration(chip);
367 /* clears mailbox and setup LFA to accept all Exted Messages */
368 hcan2_setup_mbox4read(obj);
370 hcan2_disable_configuration(chip);
375 int hcan2_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj, struct canmsg_t *msg)
377 DEBUGMSG("Pre write config\n");
379 /* change Mailbox header only if neccessary */
380 /* otherwise change only data */
381 if (hcan2_compare_msg(obj, msg))
383 if (hcan2_enable_configuration(chip))
386 hcan2_setup_mbox4write(obj, msg);
388 if (hcan2_disable_configuration(chip))
392 hcan2_setup_mbox4write_data(obj, msg);
397 int hcan2_send_msg(struct canchip_t *chip, struct msgobj_t *obj, struct canmsg_t *msg)
401 int b_addr = ((obj->object - 1) / 16) * (-2);
403 obj_bit = (1 << ((obj->object - 1) % 16));
405 /* CANMSG("Sending message [obj: %d]\n", obj->object - 1); */
407 can_write_reg_w(chip, obj_bit, b_addr + HCAN2_TXPR0);
409 /* Waits until chip sends message */
411 while (hcan2_check_tx_stat(chip) && ((i++) <= MAX_TRANSMIT_WAIT_LOOPS))
414 if (i >= MAX_TRANSMIT_WAIT_LOOPS) {
415 CANMSG("Failed while waiting for Transmitt finished\n");
419 /* CANMSG("Message sent [obj: %d]\n", obj->object - 1); */
423 int hcan2_remote_request(struct canchip_t *chip, struct msgobj_t *obj)
425 CANMSG("hcan2_remote_request not implemented\n");
429 /* ********************************************* */
430 int hcan2_irq_handler(int irq, struct canchip_t *chip)
432 uint16_t irq_reg, idx;
433 short loop_cnt = MAX_IRQ_WAIT_LOOPS;
435 struct msgobj_t * obj;
437 irq_reg = can_read_reg_w(chip, HCAN2_IRR);
438 DEBUGMSG("irq: %d, chip base addr: 0x%08x\n", irq, (uint32_t)chip->chip_base_addr);
439 /* DEBUGMSG("IRQ Handler: HCAN2_IRR: 0x%04x\n", irq_reg); */
444 CANMSG("hcan2_irq_handler IRQ %d stuck\n", irq);
445 return CANCHIP_IRQ_STUCK;
448 if (irq_reg & HCAN2_IRR_DFRI)
449 { /* Received message */
450 rxdf = (can_read_reg_w(chip, HCAN2_RXPR1) << 16) +
451 can_read_reg_w(chip, HCAN2_RXPR0);
453 DEBUGMSG("Received message [0x%08x]\n", rxdf);
456 /* find the message object */
457 for (idx = 0; (idx < chip->max_objects) && !(rxdf & (1<<idx)); idx++) { }
459 /* realy i got one? */
460 if (idx < chip->max_objects)
461 hcan2_irq_read_handler(chip, chip->msgobj[idx]);
465 /* clear RXPR flag for this msgobj */
466 can_write_reg_w(chip, (1 << (idx % 16)), HCAN2_RXPR0 - 2*(idx / 16));
468 rxdf = (can_read_reg_w(chip, HCAN2_RXPR1) << 16) +
469 can_read_reg_w(chip, HCAN2_RXPR0);
472 /* reset HCAN2_IRR_DFRI flag */
473 can_write_reg_w(chip, irq_reg & ~HCAN2_IRR_DFRI, HCAN2_IRR);
476 if (irq_reg & (HCAN2_IRR_MBEI))
478 /* Mailbox empty - after message was sent */
479 txdf = (can_read_reg_w(chip, HCAN2_TXACK1) << 16) +
480 can_read_reg_w(chip, HCAN2_TXACK0);
482 /* find the message object */
483 for (idx = 0; (idx < chip->max_objects) && !(txdf & (1<<idx)); idx++) { }
485 /* realy i got one? */
486 if (idx >= chip->max_objects) {
487 /* IRQ is caused by Aborted transmition */
488 can_write_reg_w(chip, 0xffff, HCAN2_ABACK0);
489 can_write_reg_w(chip, 0xffff, HCAN2_ABACK1);
490 return CANCHIP_IRQ_HANDLED;
493 obj = chip->msgobj[idx];
495 /* Clear TXACK flag */
496 can_write_reg_w(chip, 1 << (idx % 16), HCAN2_TXACK0 - 2 * (idx / 16));
499 hcan2_wakeup_tx(chip, obj);
502 irq_reg=can_read_reg_w(chip, HCAN2_IRR);
503 } while(irq_reg & (HCAN2_IRR_MBEI | HCAN2_IRR_DFRI));
505 /* reset ALL tinterrupt flags */
506 can_write_reg_w(chip, irq_reg, HCAN2_IRR);
508 return CANCHIP_IRQ_HANDLED;
511 int hcan2_irq_accept(int irq, struct canchip_t *chip)
513 CANMSG("hcan2_irq_accept NOT IMPLEMENTED\n");
517 int hcan2_config_irqs(struct canchip_t *chip, short irqs)
519 hcan2_clear_irq_flags(chip);
521 can_write_reg_w(chip, irqs, HCAN2_IMR);
523 /* allow all mailboxes to generate IRQ */
524 can_write_reg_w(chip, 0, HCAN2_MBIMR0);
525 can_write_reg_w(chip, 0, HCAN2_MBIMR1);
527 /* CANMSG("IRQ Mask set [0x%02x]\n", irqs); */
532 /* ********************************************* */
533 int hcan2_clear_objects(struct canchip_t *chip)
536 for (i = 0; i < chip->max_objects; i++)
537 hcan2_clear_mbox(chip, i);
542 int hcan2_check_tx_stat(struct canchip_t *chip)
544 /* DEBUGMSG("Check TX stat\n"); */
545 /* If Transmition is complete return 0 - no error */
546 if (can_read_reg_w(chip, HCAN2_GSR) & HCAN2_GSR_TXC)
552 int hcan2_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj)
554 DEBUGMSG("WakeUP TX\n");
556 if (obj->object == 1) /* msgbox 0 cant transmit only receive ! */
559 can_preempt_disable();
561 can_msgobj_set_fl(obj,TX_REQUEST);
562 while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
563 can_msgobj_clear_fl(obj,TX_REQUEST);
565 hcan2_irq_write_handler(chip, obj);
567 can_msgobj_clear_fl(obj,TX_LOCK);
568 if(!can_msgobj_test_fl(obj,TX_REQUEST)) break;
571 can_preempt_enable();
573 /* DEBUGMSG("WakeUP TX - END\n"); */
577 int hcan2_filtch_rq(struct canchip_t *chip, struct msgobj_t * obj)
579 struct canfilt_t filter;
583 int num = canqueue_ends_filt_conjuction(obj->qends, &filter);
585 canqueue_ends_filt_conjuction(obj->qends, &filter);
588 /* in structure chip->chip_data is Mailbox number */
589 chip->chip_data = (void*)(obj->object);
591 /* HCAN2 uses oposite logic for LAFM: 1-ignore bit, 0-use bit as mask */
593 DEBUGMSG("CNT: %d ID: 0x%08x MASK: 0x%08x\n", num, (uint32_t) (filter.id) & 0x1fffffff, (uint32_t) (~filter.mask) & 0x1fffffff);
595 if (filter.flags & MSG_EXT) /* Extended ID */
596 return hcan2_extended_mask(chip, filter.id, ~filter.mask);
597 else /* Standard ID */
598 return hcan2_standard_mask(chip, filter.id, ~filter.mask);
601 /* ********************************************* */
602 void hcan2_irq_read_handler(struct canchip_t *chip, struct msgobj_t *obj)
605 unsigned ctrl0, ctrl2, data;
606 unsigned long flag_addr;
610 mb_offset = (int ) obj->obj_base_addr;
612 /* DEBUGMSG("------IRQ Read Handler\n"); */
614 ctrl0 = can_read_reg_w(chip, mb_offset + HCAN2_MB_CTRL0);
615 ctrl2 = can_read_reg_w(chip, mb_offset + HCAN2_MB_CTRL2);
617 obj->rx_msg.length = len = ctrl2 & HCAN2_MBCT2_DLC;
618 obj->rx_msg.flags = (ctrl0 & HCAN2_MBCT0_RTR) ? MSG_RTR : 0;
619 obj->rx_msg.cob = obj->object - 1;
621 /* get ID of received message */
622 if (ctrl0 & HCAN2_MBCT0_IDE)
624 DEBUGMSG("EXTENDED ID\n");
625 obj->rx_msg.id = (ctrl0 & HCAN2_MBCT0_STDID) << (18 - 4);
626 obj->rx_msg.id |= can_read_reg_w(chip, mb_offset + HCAN2_MB_CTRL1);
627 obj->rx_msg.id |= ((ctrl0 & HCAN2_MBCT0_EXTID) << 16);
630 obj->rx_msg.id = (ctrl0 & HCAN2_MBCT0_STDID)>>4;
633 if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
634 for (i = 0; i < len; i++)
636 /* rcanqueue_ends_filt_conjuctionead 16bit data - two data bytes*/
637 data = can_read_reg_w(chip, (int) obj->obj_base_addr + HCAN2_MB_DATA1 + i);
638 obj->rx_msg.data[i] = (data & 0xff00) >> 8;
639 if (++i < len) obj->rx_msg.data[i] = data & 0x00ff;
642 /* Computes correct offset address of register from MSGBOX_IDX and RTR flag
643 * result is one of these:
644 * HCAN2_RXPR1, HCAN2_RXPR0, HCAN2_RFPR1, HCAN2_RFPR0
646 flag_addr = ((ctrl0 & HCAN2_MBCT0_RTR) << 3) + HCAN2_RXPR0 - ((obj->object - 1) / 16) * 2;
648 /* Reset flag by writing 1 to its position */
649 can_write_reg_w(chip, (1 << ((obj->object - 1) % 16)), flag_addr);
651 /* fill CAN message timestamp */
652 can_filltimestamp(&obj->rx_msg.timestamp);
654 canque_filter_msg2edges(obj->qends, &obj->rx_msg);
657 void hcan2_irq_write_handler(struct canchip_t *chip, struct msgobj_t *obj)
662 /* Do local transmitted message distribution if enabled */
664 /* fill CAN message timestamp */
665 can_filltimestamp(&obj->tx_slot->msg.timestamp);
667 obj->tx_slot->msg.flags |= MSG_LOCAL;
668 canque_filter_msg2edges(obj->qends, &obj->tx_slot->msg);
670 /* Free transmitted slot */
671 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
675 cmd = canque_test_outslot(obj->qends, &obj->tx_qedge, &obj->tx_slot);
679 if (chip->chipspecops->pre_write_config(chip, obj, &obj->tx_slot->msg)) {
681 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_PREP);
682 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
686 if (chip->chipspecops->send_msg(chip, obj, &obj->tx_slot->msg)) {
688 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_SEND);
689 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
695 /* ********************************************* */
696 int hcan2_register(struct chipspecops_t *chipspecops)
698 chipspecops->chip_config = hcan2_chip_config;
699 chipspecops->enable_configuration = hcan2_enable_configuration;
700 chipspecops->disable_configuration = hcan2_disable_configuration;
702 chipspecops->baud_rate = hcan2_baud_rate;
703 chipspecops->set_btregs = hcan2_set_btregs;
705 chipspecops->start_chip = hcan2_start_chip;
706 chipspecops->stop_chip = hcan2_stop_chip;
707 chipspecops->attach_to_chip = hcan2_attach_to_chip;
708 chipspecops->release_chip = hcan2_release_chip;
710 chipspecops->standard_mask = hcan2_standard_mask;
711 chipspecops->extended_mask = hcan2_extended_mask;
712 chipspecops->message15_mask = NULL; /* hcan2_message15_mask; */
714 chipspecops->pre_read_config = hcan2_pre_read_config;
715 chipspecops->pre_write_config = hcan2_pre_write_config;
716 chipspecops->send_msg = hcan2_send_msg;
717 chipspecops->remote_request = hcan2_remote_request;
719 chipspecops->irq_handler = hcan2_irq_handler;
720 chipspecops->irq_accept = NULL; /* hcan2_irq_accept; */
721 chipspecops->config_irqs = hcan2_config_irqs;
723 chipspecops->clear_objects = hcan2_clear_objects;
724 chipspecops->check_tx_stat = hcan2_check_tx_stat;
725 chipspecops->wakeup_tx = hcan2_wakeup_tx;
726 chipspecops->filtch_rq = hcan2_filtch_rq;
730 int hcan2_fill_chipspecops(struct canchip_t *chip)
732 chip->chip_type = "hcan2";
733 chip->max_objects = 32;
734 chip->write_register = chip->hostdevice->hwspecops->write_register;
735 chip->read_register = chip->hostdevice->hwspecops->read_register;
756 hcan2_register(chip->chipspecops);
761 /* ********************************************* */
762 int hcan2_reset_chip(struct canchip_t *chip)
764 /* After reset and reconfig (start_chip) Chip waits for
765 * 11 recessive bits to join CAN bus activity
771 DEBUGMSG("Resetting HCAN2 chip %d...\n", chip->chip_idx);
773 /* send Reset Request */
774 can_write_reg_w(chip, HCAN2_MCR_RESET, HCAN2_MCR );
776 /* Check hardware reset status */
778 gsr_reset = can_read_reg_w(chip, HCAN2_GSR) & HCAN2_GSR_RESET;
779 while (!(gsr_reset) && ((i++) <= MAX_SETTING_WAIT_LOOPS))
782 gsr_reset = can_read_reg_w(chip, HCAN2_GSR) & HCAN2_GSR_RESET;
785 if (i >= MAX_SETTING_WAIT_LOOPS) {
786 CANMSG("Reset status timeout! (enter Reset Mode)\n");
790 /* Clear Reset request flag */
791 can_write_reg_w(chip, can_read_reg_w(chip, HCAN2_MCR) & (~HCAN2_MCR_RESET), HCAN2_MCR);
794 /* Clear Reset Interrupt Flag IRR 0 */
795 can_write_reg_w(chip, HCAN2_IRR_RHSI, HCAN2_IRR);
797 /* DEBUGMSG("Chips reset status ok.\n"); */
802 /* !!! Functions below doesn't call enable/disable chip config !!! */
803 /* !!! Usable only in block, where enable/diable config is called explicitly !!! */
804 void hcan2_clear_irq_flags(struct canchip_t *chip)
807 DEBUGMSG("Clearing IRQ flags...\n");
808 DEBUGMSG("IRR: %04x\n",can_read_reg_w(chip, HCAN2_IRR));
810 irr = HCAN2_IRR_TCMI | HCAN2_IRR_TOI | HCAN2_IRR_WUBA |
811 HCAN2_IRR_OF | HCAN2_IRR_BOI | HCAN2_IRR_EPI |
812 HCAN2_IRR_ROWI | HCAN2_IRR_TOWI | HCAN2_IRR_RHSI;
813 can_write_reg_w(chip, irr, HCAN2_IRR);
815 /* Other IRQ flags are cleared through other registers - see below */
817 /* Meseage Overrun/Overwrite interrupt */
818 can_write_reg_w(chip, 0, HCAN2_UMSR0);
819 can_write_reg_w(chip, 0, HCAN2_UMSR1);
821 /* Mailbox Empty Interrupt */
822 can_write_reg_w(chip, 0, HCAN2_TXACK0);
823 can_write_reg_w(chip, 0, HCAN2_TXACK1);
824 can_write_reg_w(chip, 0, HCAN2_ABACK0);
825 can_write_reg_w(chip, 0, HCAN2_ABACK1);
827 /* Remote Frame Request Interrupt */
828 can_write_reg_w(chip, 0, HCAN2_RFPR0);
829 can_write_reg_w(chip, 0, HCAN2_RFPR1);
831 /* Data Frame Received Interupt Flag */
832 can_write_reg_w(chip, 0, HCAN2_RXPR0);
833 can_write_reg_w(chip, 0, HCAN2_RXPR1);
835 DEBUGMSG("clear_irq_flags - OK\n");
838 void hcan2_clear_mbox(struct canchip_t *chip, int msgobj_idx)
840 unsigned long mb_start_addr = HCAN2_MB0 + msgobj_idx * HCAN2_MB_OFFSET;
842 /* DEBUGMSG("Clearing message object %d\n", msgobj_idx); */
845 * Standard Identifier format (0)
849 can_write_reg_w(chip, 0, mb_start_addr + HCAN2_MB_CTRL0);
851 /* EXTID {15:0} = 0 */
852 can_write_reg_w(chip, 0, mb_start_addr + HCAN2_MB_CTRL1);
854 /* NMC: overwrite stored message (1)
855 * ATDF: No message is transmited after receiving Remote Frame (0)
856 * DARTX: disable Automatic Retransmition: yes (1)
857 * MBC = 111 - not used: HCAN2_MBCT2_MBC default value correspond to 'Not Used'
861 can_write_reg_w(chip, (uint16_t) (HCAN2_MBCT2_NMC | HCAN2_MBCT2_DART | HCAN2_MBCT2_MBC), mb_start_addr + HCAN2_MB_CTRL2);
864 can_write_reg_w(chip, 0, mb_start_addr + HCAN2_MB_TSTP);
866 /* Data: all bytes 0xff */
867 can_write_reg_w(chip, (uint16_t) 0xffff, mb_start_addr + HCAN2_MB_DATA0);
868 can_write_reg_w(chip, (uint16_t) 0xffff, mb_start_addr + HCAN2_MB_DATA2);
869 can_write_reg_w(chip, (uint16_t) 0xffff, mb_start_addr + HCAN2_MB_DATA4);
870 can_write_reg_w(chip, (uint16_t) 0xffff, mb_start_addr + HCAN2_MB_DATA6);
872 /* Local Acceptance Filter Mask - all bits of STDID and EXTID must match values set in mailbox */
873 can_write_reg_w(chip, 0, mb_start_addr + HCAN2_MB_MASK);
874 can_write_reg_w(chip, 0, mb_start_addr + HCAN2_MB_MASK + 2); /* Mask is 4 bytes */
877 DEBUGMSG("Mailbox [%d] cleared.\n", msgobj_idx);
880 void hcan2_setup_mbox4write(struct msgobj_t * obj, struct canmsg_t * msg)
883 uint16_t ctrl0, ctrl1, ctrl2;
885 struct canchip_t * chip = obj->hostchip;
887 DEBUGMSG("Change Header\n");
889 mb_offset = (int) obj->obj_base_addr;
891 hcan2_setup_ctrl_regs(msg, &ctrl0, &ctrl1, &ctrl2);
893 can_write_reg_w(chip, ctrl0, mb_offset + HCAN2_MB_CTRL0);
894 can_write_reg_w(chip, ctrl1, mb_offset + HCAN2_MB_CTRL1); /* set 0 if not using EXT format */
895 can_write_reg_w(chip, ctrl2, mb_offset + HCAN2_MB_CTRL2);
898 hcan2_setup_mbox4write_data(obj, msg);
901 void hcan2_setup_mbox4write_data(struct msgobj_t * obj, struct canmsg_t * msg)
903 int len,i, mb_offset;
906 struct canchip_t * chip = obj->hostchip;
908 DEBUGMSG("Change Data\n");
910 mb_offset = (int) obj->obj_base_addr;
913 if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
915 for (i = 0; i < len; i+=2)
917 data = (msg->data[i] << 8) + (i+1 < len ? msg->data[i+1] : 0);
918 can_write_reg_w(chip, data, mb_offset + HCAN2_MB_DATA1 + i);
922 void hcan2_setup_mbox4read(struct msgobj_t * obj)
924 struct canchip_t * chip = obj->hostchip;
926 hcan2_clear_mbox(chip, obj->object - 1);
928 // in structure chip->chip_data is Mailbox number
929 chip->chip_data = (void*)(obj->object);
930 hcan2_extended_mask(chip, 2048, 0x1fffffff); /* accept all */
932 can_write_reg_w(chip, HCAN2_MBCT2_DART + (HCAN2_MBMOD_RXDR << 8),
933 (int) obj->obj_base_addr + HCAN2_MB_CTRL2);
936 void hcan2_setup_ctrl_regs(struct canmsg_t * msg, uint16_t * ctrl0, uint16_t * ctrl1, uint16_t * ctrl2)
939 uint32_t id = msg->id;
942 if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
944 *ctrl0 = (msg->flags & MSG_RTR ? HCAN2_MBCT0_RTR : 0);
946 if (msg->flags & MSG_EXT)
949 *ctrl0 |= ((id & 0x1ffc0000) << 14);
950 *ctrl0 |= ((id & 0x00030000) >> 16) | HCAN2_MBCT0_IDE; /* get bits {17:16} from EXTID */
951 *ctrl1 = (id & 0x0000ffff);
956 *ctrl0 |= ((id & 0x01ff) << 4);
960 *ctrl2 = HCAN2_MBCT2_DART + HCAN2_MBMOD_TXDR + (len & HCAN2_MBCT2_DLC);
963 int hcan2_compare_msg(struct msgobj_t * obj, struct canmsg_t * msg)
965 /* Check if mailbox header content change is neccessary */
966 /* Comparing only Control regs */
967 uint16_t ctrl0, ctrl1, ctrl2;
971 struct canchip_t * chip = obj->hostchip;
973 mb_offset = (int) obj->obj_base_addr;
975 c0 = can_read_reg_w(chip, mb_offset + HCAN2_MB_CTRL0);
976 c1 = can_read_reg_w(chip, mb_offset + HCAN2_MB_CTRL1);
977 c2 = can_read_reg_w(chip, mb_offset + HCAN2_MB_CTRL2);
979 hcan2_setup_ctrl_regs(msg, &ctrl0, &ctrl1, &ctrl2);
981 /* if using EXT ID conpare also ctrl1 */
982 if (msg->flags & MSG_EXT && ctrl1 ^ c1)
986 DEBUGMSG("C0 0x%04x HW: 0x%04x\n", ctrl0, c0);
987 DEBUGMSG("C1 0x%04x HW: 0x%04x\n", ctrl1, c1);
988 DEBUGMSG("C2 0x%04x HW: 0x%04x\n", ctrl2, c2);
990 return ((ctrl0 ^ c0) || (ctrl2 ^ c2));