1 /**************************************************************************/
2 /* File: pip.c - support for PIP5,PIP6,PIP7 and PIP8 boards for */
3 /* Packaged Industrial PCs supportof MPL AG, Switzerland */
5 /* LinCAN - (Not only) Linux CAN bus driver */
6 /* Copyright (C) 2002-2009 DCE FEE CTU Prague <http://dce.felk.cvut.cz> */
7 /* Copyright (C) 2002-2009 Pavel Pisa <pisa@cmp.felk.cvut.cz> */
8 /* Copyright (C) 2005-2006 Stefan Peter, MPL AG, Switzerland */
9 /* Funded by OCERA and FRESCOR IST projects */
10 /* Based on CAN driver code by Arnaud Westenberg <arnaud@wanadoo.nl> */
12 /* LinCAN is free software; you can redistribute it and/or modify it */
13 /* under terms of the GNU General Public License as published by the */
14 /* Free Software Foundation; either version 2, or (at your option) any */
15 /* later version. LinCAN is distributed in the hope that it will be */
16 /* useful, but WITHOUT ANY WARRANTY; without even the implied warranty */
17 /* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */
18 /* General Public License for more details. You should have received a */
19 /* copy of the GNU General Public License along with LinCAN; see file */
20 /* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, */
21 /* Cambridge, MA 02139, USA. */
23 /* To allow use of LinCAN in the compact embedded systems firmware */
24 /* and RT-executives (RTEMS for example), main authors agree with next */
25 /* special exception: */
27 /* Including LinCAN header files in a file, instantiating LinCAN generics */
28 /* or templates, or linking other files with LinCAN objects to produce */
29 /* an application image/executable, does not by itself cause the */
30 /* resulting application image/executable to be covered by */
31 /* the GNU General Public License. */
32 /* This exception does not however invalidate any other reasons */
33 /* why the executable file might be covered by the GNU Public License. */
34 /* Publication of enhanced or derived LinCAN files is required although. */
35 /**************************************************************************/
38 #include "../include/can.h"
39 #include "../include/can_sysdep.h"
40 #include "../include/main.h"
41 #include "../include/pip.h"
42 #include "../include/i82527.h"
43 /* PIP Specific Extension registers */
44 #define PIP_CANRES_REG 0x804 /* CAN Resources */
45 #define PIP_CANCTRL_REG (PIP_CANRES_REG+1) /* CAN Control */
46 /* Interrupt maps for the various PIP variants, see user manual */
47 #define PIP5_IRQ_MAP 0x4F6D
48 #define PIP6_IRQ_MAP 0xDEF8
49 #define PIP7_IRQ_MAP 0x3768
50 #define PIP8_IRQ_MAP 0x3768
52 int pip_request_io(struct candevice_t *candev)
54 if ((candev->io_addr != 0x1000) && (candev->io_addr != 0x8000)
55 && (candev->io_addr != 0xe000)) {
56 CANMSG("Invalid base io address\n");
58 ("Valid values for the PIP are: 0x1000, 0x8000 or 0xe000\n");
59 CANMSG("Please consult your user manual.\n");
62 if (!can_request_io_region(candev->io_addr, 0x100, DEVICE_NAME)) {
63 CANMSG("Unable to open port: 0x%lx\n", candev->io_addr);
66 if (!can_request_io_region(PIP_CANRES_REG, 0x02, DEVICE_NAME))
68 can_release_io_region(candev->io_addr, 0x100);
69 CANMSG("Unable to open port: 0x%x\n", PIP_CANRES_REG);
72 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n",
73 candev->io_addr, candev->io_addr + 0x100 - 1);
74 DEBUGMSG("Registered IO-memory : 0x%x - 0x%x\n",
75 PIP_CANRES_REG, PIP_CANCTRL_REG);
80 int pip_release_io(struct candevice_t *candev)
82 can_release_io_region(candev->io_addr, 0x100);
83 can_release_io_region(PIP_CANRES_REG, 0x02);
88 int pip_reset(struct candevice_t *candev)
92 DEBUGMSG("Resetting %s hardware ...\n", candev->hwname);
95 can_outb(0x01, candev->res_addr);
97 can_outb(0x0, candev->res_addr);
99 /* Check hardware reset status */
101 while ((can_inb(candev->io_addr + iCPU) & iCPU_RST) && (i <= 15)) {
106 CANMSG("Reset status timeout!\n");
107 CANMSG("Please check your hardware.\n");
110 DEBUGMSG("Chip0 reset status ok.\n");
116 int pip_init_hw_data(struct candevice_t *candev)
118 candev->res_addr = PIP_CANCTRL_REG;
119 candev->nr_82527_chips = 1;
120 candev->nr_sja1000_chips = 0;
121 candev->nr_all_chips = 1;
122 candev->flags |= CANDEV_PROGRAMMABLE_IRQ;
127 int pip_init_chip_data(struct candevice_t *candev, int chipnr)
129 i82527_fill_chipspecops(candev->chip[chipnr]);
130 candev->chip[chipnr]->chip_base_addr = can_ioport2ioptr(candev->io_addr);
131 candev->chip[chipnr]->clock = 8000000;
132 candev->chip[chipnr]->int_cpu_reg = 0;
133 candev->chip[chipnr]->int_clk_reg = iCLK_SL1;
134 candev->chip[chipnr]->int_bus_reg = iBUS_CBY;
135 candev->chip[chipnr]->sja_cdr_reg = 0;
136 candev->chip[chipnr]->sja_ocr_reg = 0;
141 int pip_init_obj_data(struct canchip_t *chip, int objnr)
143 chip->msgobj[objnr]->obj_base_addr =
144 chip->chip_base_addr + (objnr + 1) * 0x10;
149 int pip_program_irq(struct candevice_t *candev)
151 unsigned int irq_mask;
152 unsigned char can_addr = 0, can_reg = 0;
153 DEBUGMSG("pip_program_irq\n");
154 /* Reset can controller */
155 can_outb(0x01, candev->res_addr);
156 if (strcmp(candev->hwname, "pip5") == 0) {
157 irq_mask = PIP5_IRQ_MAP;
158 } else if (strcmp(candev->hwname, "pip6") == 0) {
159 irq_mask = PIP6_IRQ_MAP;
160 } else if (strcmp(candev->hwname, "pip7") == 0) {
161 irq_mask = PIP7_IRQ_MAP;
162 } else if (strcmp(candev->hwname, "pip8") == 0) {
163 irq_mask = PIP8_IRQ_MAP;
165 CANMSG("Unsupported PIP specified.\n");
168 if ((candev->chip[0]->chip_irq < 1)
169 || (candev->chip[0]->chip_irq > 15)) {
170 CANMSG("Interrupt specified does not exist.\n");
173 if (((0x01 << (candev->chip[0]->chip_irq - 1)) & irq_mask) == 0) {
174 CANMSG("Invalid Interrupt specified %d\n",
175 candev->chip[0]->chip_irq);
179 /* set the IRQ routing of the board accordingly */
180 switch (candev->io_addr) {
195 ("Supplied io address is not valid, please check your manual\n");
199 can_reg = can_inb(PIP_CANRES_REG);
200 DEBUGMSG("PIP_CANRES was 0x%x\n", can_reg);
201 can_reg = (candev->chip[0]->chip_irq << 4) | can_addr;
202 DEBUGMSG("Setting PIP_CANRES_REG to 0x%x\n", can_reg);
203 can_outb((candev->chip[0]->chip_irq << 4) | can_addr, PIP_CANRES_REG);
204 /* re-enable the chip */
205 can_outb(0x00, candev->res_addr);
211 void pip_write_register(unsigned data, can_ioptr_t address)
213 can_outb(data, address);
216 unsigned pip_read_register(can_ioptr_t address)
218 return can_inb(address);
221 /* !!! Don't change these functions !!! */
222 int pip_register(struct hwspecops_t *hwspecops)
224 hwspecops->request_io = pip_request_io;
225 hwspecops->release_io = pip_release_io;
226 hwspecops->reset = pip_reset;
227 hwspecops->init_hw_data = pip_init_hw_data;
228 hwspecops->init_chip_data = pip_init_chip_data;
229 hwspecops->init_obj_data = pip_init_obj_data;
230 hwspecops->write_register = pip_write_register;
231 hwspecops->read_register = pip_read_register;
232 hwspecops->program_irq = pip_program_irq;