1 /**************************************************************************/
2 /* File: pcccan.c - PCCCAN board support */
4 /* LinCAN - (Not only) Linux CAN bus driver */
5 /* Copyright (C) 2002-2009 DCE FEE CTU Prague <http://dce.felk.cvut.cz> */
6 /* Copyright (C) 2002-2009 Pavel Pisa <pisa@cmp.felk.cvut.cz> */
7 /* Funded by OCERA and FRESCOR IST projects */
8 /* Based on CAN driver code by Arnaud Westenberg <arnaud@wanadoo.nl> */
10 /* LinCAN is free software; you can redistribute it and/or modify it */
11 /* under terms of the GNU General Public License as published by the */
12 /* Free Software Foundation; either version 2, or (at your option) any */
13 /* later version. LinCAN is distributed in the hope that it will be */
14 /* useful, but WITHOUT ANY WARRANTY; without even the implied warranty */
15 /* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */
16 /* General Public License for more details. You should have received a */
17 /* copy of the GNU General Public License along with LinCAN; see file */
18 /* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, */
19 /* Cambridge, MA 02139, USA. */
21 /* To allow use of LinCAN in the compact embedded systems firmware */
22 /* and RT-executives (RTEMS for example), main authors agree with next */
23 /* special exception: */
25 /* Including LinCAN header files in a file, instantiating LinCAN generics */
26 /* or templates, or linking other files with LinCAN objects to produce */
27 /* an application image/executable, does not by itself cause the */
28 /* resulting application image/executable to be covered by */
29 /* the GNU General Public License. */
30 /* This exception does not however invalidate any other reasons */
31 /* why the executable file might be covered by the GNU Public License. */
32 /* Publication of enhanced or derived LinCAN files is required although. */
33 /**************************************************************************/
35 /* This file contains the low level functions for the pcccan-1 card from Gespac.
36 * You can probably find more information at http://www.gespac.com
39 #include "../include/can.h"
40 #include "../include/can_sysdep.h"
41 #include "../include/main.h"
42 #include "../include/pcccan.h"
43 #include "../include/i82527.h"
46 unsigned long pcccan_base=0x0;
48 static CAN_DEFINE_SPINLOCK(pcccan_port_lock);
51 * IO_RANGE is the io-memory range that gets reserved, please adjust according
52 * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
53 * #define IO_RANGE 0x20 for sja1000 chips in basic CAN mode.
56 /* The pcccan card uses indexed addressing hence the need to only reserve
57 * eight bytes of memory.
59 * base + 1 = Address loading
60 * base + 2 = Read register
61 * base + 3 = Read register + increment loaded address (saves a write operation
62 * when accessing consecutive registers)
64 * base + 5 = Address read
65 * base + 6 = Write register
66 * base + 7 = Write register + increment loaded address
71 * pcccan_request_io: - reserve io or memory range for can board
72 * @candev: pointer to candevice/board which asks for io. Field @io_addr
73 * of @candev is used in most cases to define start of the range
75 * The function pcccan_request_io() is used to reserve the io-memory. If your
76 * hardware uses a dedicated memory range as hardware control registers you
77 * will have to add the code to reserve this memory as well.
78 * %IO_RANGE is the io-memory range that gets reserved, please adjust according
79 * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
80 * #define IO_RANGE 0x20 for sja1000 chips in basic CAN mode.
81 * Return Value: The function returns zero on success or %-ENODEV on failure
84 int pcccan_request_io(struct candevice_t *candev)
86 if (!can_request_io_region(candev->io_addr,IO_RANGE,DEVICE_NAME)) {
87 CANMSG("Unable to open port: 0x%lx\n",candev->io_addr);
90 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", candev->io_addr, candev->io_addr + IO_RANGE - 1);
96 * pcccan_elease_io - free reserved io memory range
97 * @candev: pointer to candevice/board which releases io
99 * The function pcccan_release_io() is used to free reserved io-memory.
100 * In case you have reserved more io memory, don't forget to free it here.
101 * IO_RANGE is the io-memory range that gets released, please adjust according
102 * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
103 * #define IO_RANGE 0x20 for sja1000 chips in basic CAN mode.
104 * Return Value: The function always returns zero
107 int pcccan_release_io(struct candevice_t *candev)
109 can_release_io_region(candev->io_addr,IO_RANGE);
115 * pcccan_reset - hardware reset routine
116 * @candev: Pointer to candevice/board structure
118 * The function pcccan_reset() is used to give a hardware reset. This is
119 * rather hardware specific so I haven't included example code. Don't forget to
120 * check the reset status of the chip before returning.
121 * Return Value: The function returns zero on success or %-ENODEV on failure
124 int pcccan_reset(struct candevice_t *candev)
128 DEBUGMSG("Resetting pcccan-1 hardware ...\n");
129 while (i < 1000000) {
131 can_outb(0x0,candev->res_addr);
134 /* Check hardware reset status */
136 can_outb(iCPU,candev->io_addr+0x1);
137 while ( (can_inb(candev->io_addr+0x2)&0x80) && (i<=15) ) {
142 CANMSG("Reset status timeout!\n");
143 CANMSG("Please check your hardware.\n");
147 DEBUGMSG("Chip reset status ok.\n");
156 * pcccan_init_hw_data - Initialize hardware cards
157 * @candev: Pointer to candevice/board structure
159 * The function pcccan_init_hw_data() is used to initialize the hardware
160 * structure containing information about the installed CAN-board.
161 * %RESET_ADDR represents the io-address of the hardware reset register.
162 * %NR_82527 represents the number of intel 82527 chips on the board.
163 * %NR_SJA1000 represents the number of philips sja1000 chips on the board.
164 * The flags entry can currently only be %CANDEV_PROGRAMMABLE_IRQ to indicate that
165 * the hardware uses programmable interrupts.
166 * Return Value: The function always returns zero
169 int pcccan_init_hw_data(struct candevice_t *candev)
171 candev->res_addr=candev->io_addr;
172 candev->nr_82527_chips=NR_82527;
173 candev->nr_sja1000_chips=NR_SJA1000;
174 candev->nr_all_chips=NR_82527+NR_SJA1000;
175 candev->flags &= ~CANDEV_PROGRAMMABLE_IRQ;
181 * pcccan_init_chip_data - Initialize chips
182 * @candev: Pointer to candevice/board structure
183 * @chipnr: Number of the CAN chip on the hardware card
185 * The function pcccan_init_chip_data() is used to initialize the hardware
186 * structure containing information about the CAN chips.
187 * %CHIP_TYPE represents the type of CAN chip. %CHIP_TYPE can be "i82527" or
189 * The @chip_base_addr entry represents the start of the 'official' memory map
190 * of the installed chip. It's likely that this is the same as the @io_addr
191 * argument supplied at module loading time.
192 * The @clock entry holds the chip clock value in Hz.
193 * The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
194 * register. Options defined in the %sja1000.h file:
195 * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
196 * The entry @sja_ocr_reg holds hardware specific options for the Output Control
197 * register. Options defined in the %sja1000.h file:
198 * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
199 * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
200 * The entry @int_clk_reg holds hardware specific options for the Clock Out
201 * register. Options defined in the %i82527.h file:
202 * %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
203 * The entry @int_bus_reg holds hardware specific options for the Bus
204 * Configuration register. Options defined in the %i82527.h file:
205 * %iBUS_DR0, %iBUS_DR1, %iBUS_DT1, %iBUS_POL, %iBUS_CBY.
206 * The entry @int_cpu_reg holds hardware specific options for the cpu interface
207 * register. Options defined in the %i82527.h file:
208 * %iCPU_CEN, %iCPU_MUX, %iCPU_SLP, %iCPU_PWD, %iCPU_DMC, %iCPU_DSC, %iCPU_RST.
209 * Return Value: The function always returns zero
212 int pcccan_init_chip_data(struct candevice_t *candev, int chipnr)
214 i82527_fill_chipspecops(candev->chip[chipnr]);
215 candev->chip[chipnr]->chip_base_addr=can_ioport2ioptr(candev->io_addr);
216 candev->chip[chipnr]->clock = 16000000;
217 candev->chip[chipnr]->int_cpu_reg = iCPU_DSC | iCPU_DMC;
218 candev->chip[chipnr]->int_clk_reg = iCLK_SL1 | iCLK_CD0;
219 candev->chip[chipnr]->int_bus_reg = iBUS_CBY | iBUS_DR1;
220 candev->chip[chipnr]->sja_cdr_reg = 0;
221 candev->chip[chipnr]->sja_ocr_reg = 0;
222 pcccan_irq=candev->chip[chipnr]->chip_irq;
223 pcccan_base=candev->chip[chipnr]->chip_base_addr;
229 * pcccan_init_obj_data - Initialize message buffers
230 * @chip: Pointer to chip specific structure
231 * @objnr: Number of the message buffer
233 * The function pcccan_init_obj_data() is used to initialize the hardware
234 * structure containing information about the different message objects on the
235 * CAN chip. In case of the sja1000 there's only one message object but on the
236 * i82527 chip there are 15.
237 * The code below is for a i82527 chip and initializes the object base addresses
238 * The entry @obj_base_addr represents the first memory address of the message
239 * object. In case of the sja1000 @obj_base_addr is taken the same as the chips
241 * Unless the hardware uses a segmented memory map, flags can be set zero.
242 * Return Value: The function always returns zero
245 int pcccan_init_obj_data(struct canchip_t *chip, int objnr)
247 chip->msgobj[objnr]->obj_base_addr=(objnr+1)*0x10;
253 * pcccan_program_irq - program interrupts
254 * @candev: Pointer to candevice/board structure
256 * The function pcccan_program_irq() is used for hardware that uses
257 * programmable interrupts. If your hardware doesn't use programmable interrupts
258 * you should not set the @candevices_t->flags entry to %CANDEV_PROGRAMMABLE_IRQ and
259 * leave this function unedited. Again this function is hardware specific so
260 * there's no example code.
261 * Return value: The function returns zero on success or %-ENODEV on failure
264 int pcccan_program_irq(struct candevice_t *candev)
270 * pcccan_write_register - Low level write register routine
271 * @data: data to be written
272 * @address: memory address to write to
274 * The function pcccan_write_register() is used to write to hardware registers
275 * on the CAN chip. You should only have to edit this function if your hardware
276 * uses some specific write process.
277 * Return Value: The function does not return a value
280 void pcccan_write_register(unsigned data, can_ioptr_t address)
282 can_spin_irqflags_t flags;
283 can_spin_lock_irqsave(&pcccan_port_lock,flags);
284 can_outb(address - pcccan_base, pcccan_base+1);
285 can_outb(data, pcccan_base+6);
286 can_spin_unlock_irqrestore(&pcccan_port_lock,flags);
290 * pcccan_read_register - Low level read register routine
291 * @address: memory address to read from
293 * The function pcccan_read_register() is used to read from hardware registers
294 * on the CAN chip. You should only have to edit this function if your hardware
295 * uses some specific read process.
296 * Return Value: The function returns the value stored in @address
299 unsigned pcccan_read_register(can_ioptr_t address)
302 can_spin_irqflags_t flags;
303 can_spin_lock_irqsave(&pcccan_port_lock,flags);
304 can_outb(address - pcccan_base, pcccan_base+1);
305 ret=can_inb(pcccan_base+2);
306 can_spin_unlock_irqrestore(&pcccan_port_lock,flags);
311 /* !!! Don't change this function !!! */
312 int pcccan_register(struct hwspecops_t *hwspecops)
314 hwspecops->request_io = pcccan_request_io;
315 hwspecops->release_io = pcccan_release_io;
316 hwspecops->reset = pcccan_reset;
317 hwspecops->init_hw_data = pcccan_init_hw_data;
318 hwspecops->init_chip_data = pcccan_init_chip_data;
319 hwspecops->init_obj_data = pcccan_init_obj_data;
320 hwspecops->write_register = pcccan_write_register;
321 hwspecops->read_register = pcccan_read_register;
322 hwspecops->program_irq = pcccan_program_irq;