1 /**************************************************************************/
2 /* File: mscan.c - Freescale MPC5200 MSCAN controller support */
4 /* LinCAN - (Not only) Linux CAN bus driver */
5 /* Copyright (C) 2002-2009 DCE FEE CTU Prague <http://dce.felk.cvut.cz> */
6 /* Copyright (C) 2002-2009 Pavel Pisa <pisa@cmp.felk.cvut.cz> */
7 /* Copyright (C) 2007-2008 Martin Petera <peterm4@fel.cvut.cz> */
8 /* Funded by OCERA and FRESCOR IST projects */
9 /* Based on CAN driver code by Arnaud Westenberg <arnaud@wanadoo.nl> */
11 /* LinCAN is free software; you can redistribute it and/or modify it */
12 /* under terms of the GNU General Public License as published by the */
13 /* Free Software Foundation; either version 2, or (at your option) any */
14 /* later version. LinCAN is distributed in the hope that it will be */
15 /* useful, but WITHOUT ANY WARRANTY; without even the implied warranty */
16 /* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */
17 /* General Public License for more details. You should have received a */
18 /* copy of the GNU General Public License along with LinCAN; see file */
19 /* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, */
20 /* Cambridge, MA 02139, USA. */
22 /* To allow use of LinCAN in the compact embedded systems firmware */
23 /* and RT-executives (RTEMS for example), main authors agree with next */
24 /* special exception: */
26 /* Including LinCAN header files in a file, instantiating LinCAN generics */
27 /* or templates, or linking other files with LinCAN objects to produce */
28 /* an application image/executable, does not by itself cause the */
29 /* resulting application image/executable to be covered by */
30 /* the GNU General Public License. */
31 /* This exception does not however invalidate any other reasons */
32 /* why the executable file might be covered by the GNU Public License. */
33 /* Publication of enhanced or derived LinCAN files is required although. */
34 /**************************************************************************/
36 #include "../include/can.h"
37 #include "../include/can_sysdep.h"
38 #include "../include/main.h"
39 #include "../include/mscan.h"
40 //#include "../include/mpc5200.h"
43 #define MSCAN_MAX_TRANSMIT_WAIT_LOOPS 20
44 #define MSCAN_MAX_SETTING_WAIT_LOOPS 25 /* maximal loop count while checking Chip reply to action ~ 5 ms */
45 #define MSCAN_MAX_IRQ_WAIT_LOOPS 25
47 CAN_DEFINE_SPINLOCK(mscan_prewr_lock);
49 void mscan_irq_read_handler(struct canchip_t *chip, struct msgobj_t *obj);
50 void mscan_irq_write_handler(struct canchip_t *chip, struct msgobj_t *obj);
52 int mscan_clear_irq_flags(struct canchip_t *chip);
53 void mscan_setup_ctrl_regs(struct canmsg_t * msg, uint16_t * ctrl0, uint16_t * ctrl1, uint16_t * ctrl2);
55 void mscan_msg_from_rxbuffer(struct canchip_t * chip, struct canmsg_t * msg);
56 void mscan_setup_txbuffer(struct canchip_t * chip, struct canmsg_t * msg);
58 void mscan_notifyRXends(struct msgobj_t * obj, int what);
59 int mscan_check_txbuff_stat(struct canchip_t *chip, int buffer);
61 static int mscan_update_samplept(int sampl_pt, int tseg, int *tseg1, int *tseg2);
63 static int mscan_init_mode_active(struct canchip_t *chip);
64 static int mscan_sleep_mode_active(struct canchip_t *chip);
66 static int mscan_enter_init_mode(struct canchip_t * chip);
67 static int mscan_enter_sleep_mode(struct canchip_t * chip);
69 static reg_t mscan_get_flags(struct canchip_t * chip, reg_t flags, unsigned reg_addr);
70 static void mscan_set_flags(struct canchip_t * chip, reg_t flags, unsigned reg_addr);
71 static void mscan_clear_flags(struct canchip_t * chip, reg_t flags, unsigned reg_addr);
72 static uint16_t mscan_get_irq_flags(struct canchip_t * chip);
74 static void mscan_clear_buffer(struct canchip_t * chip, unsigned start_addr);
75 static int mscan_abort_msg(struct canchip_t * chip, reg_t buffer_mask);
78 static void dump_regs(struct canchip_t * chip)
80 CANMSG("MSCAN reg dump\n");
81 CANMSG("CTL0 0x%02x\tCTL1 0x%02x\tBTR0 0x%02x\tBTR1 0x%02x\n",
82 mscan_get_flags(chip, 0xff, MSCAN_CTL0),
83 mscan_get_flags(chip, 0xff, MSCAN_CTL1),
84 mscan_get_flags(chip, 0xff, MSCAN_BTR0),
85 mscan_get_flags(chip, 0xff, MSCAN_BTR1));
87 CANMSG("RFLG 0x%02x\tRIER 0x%02x\tTFLG 0x%02x\tTIER 0x%02x\n",
88 mscan_get_flags(chip, 0xff, MSCAN_RFLG),
89 mscan_get_flags(chip, 0xff, MSCAN_RIER),
90 mscan_get_flags(chip, 0xff, MSCAN_TFLG),
91 mscan_get_flags(chip, 0xff, MSCAN_TIER));
93 CANMSG("TARQ 0x%02x\tTAAK 0x%02x\tTBSEL 0x%02x\tIDAC 0x%02x\n",
94 mscan_get_flags(chip, 0xff, MSCAN_TARQ),
95 mscan_get_flags(chip, 0xff, MSCAN_TAAK),
96 mscan_get_flags(chip, 0xff, MSCAN_TBSEL),
97 mscan_get_flags(chip, 0xff, MSCAN_IDAC));
99 CANMSG("RXERR 0x%02x\tTXERR 0x%02x\n",
100 mscan_get_flags(chip, 0xff, MSCAN_RXERR),
101 mscan_get_flags(chip, 0xff, MSCAN_TXERR));
105 static void dump_buff(struct canchip_t * chip, unsigned offset_addr)
107 volatile struct mscan_msg_buffer * buff = (struct mscan_msg_buffer *)(chip->chip_base_addr + offset_addr);
109 CANMSG("MSCAN buffer dump\n");
111 /* structural access */
112 CANMSG("Data0 0x%02x Data1 0x%02x Data2 0x%02x Data3 0x%02x Data4 0x%02x Data5 0x%02x Data6 0x%02x Data7 0x%02x\n",
113 buff->data_0, buff->data_1, buff->data_2, buff->data_3, buff->data_4, buff->data_5, buff->data_6, buff->data_7);
114 CANMSG("Data Len %d\tPriority 0x%02x\n",
115 buff->data_len, buff->local_prio);
116 CANMSG("IDR0 0x%02x\tIDR1 0x%02x\tIDR2 0x%02x\tIDR3 0x%02x\n",
117 buff->id_0, buff->id_1, buff->id_2, buff->id_3);
121 static void dump_filter(struct canchip_t * chip)
123 volatile struct mscan_flt_regs * flt = (struct mscan_flt_regs *)(chip->chip_base_addr + MSCAN_IDAR0);
125 CANMSG("MSCAN Acceptance filter dump\n");
127 CANMSG("IDAC 0x%02x\n", mscan_get_flags(chip, MSCAN_IDAC_IDAM | MSCAN_IDAC_IDHIT, MSCAN_IDAC));
129 CANMSG("IDAR0 0x%02x\tIDAR1 0x%02x\tIDAR2 0x%02x\tIDAR3 0x%02x\n",
130 flt->acp_id_0, flt->acp_id_1, flt->acp_id_2, flt->acp_id_3);
131 CANMSG("IDMR0 0x%02x\tIDMR1 0x%02x\tIDMR2 0x%02x\tIDMR3 0x%02x\n",
132 flt->acp_mask_0, flt->acp_mask_1, flt->acp_mask_2, flt->acp_mask_3);
134 CANMSG("IDAR4 0x%02x\tIDAR5 0x%02x\tIDAR6 0x%02x\tIDAR7 0x%02x\n",
135 flt->acp_id_4, flt->acp_id_5, flt->acp_id_6, flt->acp_id_7);
136 CANMSG("IDMR4 0x%02x\tIDMR5 0x%02x\tIDMR6 0x%02x\tIDMR7 0x%02x\n",
137 flt->acp_mask_4, flt->acp_mask_5, flt->acp_mask_6, flt->acp_mask_7);
139 #endif /* MPC5200_DBG */
142 /* macro for standardized CAN Bus Status change report */
143 #define MSCAN_STAT_CHANGE(msg,idx) CANMSG("MSCAN chip %d %s\n", idx, msg)
145 /* Enable folowing IRQs
146 * MSCAN_TIER_TXE - Transmit Empty Interrupt - Set and Cleared during TX proccess not during init
147 * MSCAN_RIER_RXFIE - Receive Buffer Full
148 * MSCAN_RIER_RSTATE - Receiver Status Change Enable: 0-Never, 1-BusOff, 2-BusOff+RxErr, 3-All
149 * MSCAN_RIER_TSTATE - Transmitter Status Change Enable: 0-Never, 1-BusOff, 2-BusOff+TxErr, 3-All
150 * MSCAN_RIER_OVRIE - Overrun
151 * MSCAN_RIER_CSCIE - CAN Status Change
153 uint16_t mscan_IRQs = MSCAN_RIER_RXFIE |
154 MSCAN_RIER_RSTATE | MSCAN_RIER_TSTATE |
155 MSCAN_RIER_OVRIE | MSCAN_RIER_CSCIE; /* TX interrupt flag is held shifted */
156 /* 1 - enable interrupt, 0 - interrupt is masked */
158 /* used to distinguish which direction (TX/RX) caused Can Bus State change interrupt */
162 /* initial acceptance filter settings */
163 #define INIT_STD_ID 0x0000
164 #define INIT_STD_MASK 0x0fff /* accept all messages - 11 mask bits and LSB is RTR */
168 /* ************************************************************************************************************************************* */
171 int mscan_chip_config(struct canchip_t *chip)
173 /* Do not clear buffers here, they may contain valid data ! */
176 DEBUGMSG("Configuring chip...\n");
178 if ((err = mscan_enable_configuration(chip)))
182 chip->baudrate=1000000; /* default baudrate set to 1Mbit */
183 if ((err = mscan_baud_rate(chip, chip->baudrate, chip->clock, 0, 750, 0)))
186 if ((err = mscan_disable_configuration(chip)))
189 /* IRQ mask could be set only when NOT in INIT mode */
190 if ((err = mscan_config_irqs(chip, mscan_IRQs)))
196 /* enter initialization AND sleep mode */
197 int mscan_enable_configuration(struct canchip_t *chip)
199 /* Do not clear buffers here, they may contain valid data ! */
201 DEBUGMSG("config ENABLE\n");
203 if (mscan_init_mode_active(chip)) /* chip is already in config mode */
205 DEBUGMSG("config ENABLE ... already in INIT mode\n");
209 /* Disable interrupt */
210 can_disable_irq(chip->chip_irq);
213 /* Sleep mode - disable CAN activity after completing current operation */
214 /* if controler not synced to bus, skip sleep mode */
215 if (!mscan_sleep_mode_active(chip) &&
216 mscan_get_flags(chip, MSCAN_CTL0_SYNCH, MSCAN_CTL0))
217 if (mscan_enter_sleep_mode(chip))
219 /* cannot enter sleep mode */
221 DEBUGMSG("Forcig INIT\n");
225 /* now we can enter Init mode */
226 if(mscan_enter_init_mode(chip))
227 goto econf_exit_busy;
230 /* DEBUGMSG("config ENABLE ... OK\n"); */
234 /* DEBUGMSG("config ENABLE ... failed !\n"); */
235 can_enable_irq(chip->chip_irq);
239 int mscan_disable_configuration(struct canchip_t *chip)
241 /* Do not clear buffers here, they may contain valid data ! */
244 DEBUGMSG("config DISABLE\n");
246 if (!mscan_init_mode_active(chip) && !mscan_sleep_mode_active(chip)) /* chip is already in normal mode */
248 DEBUGMSG("config DISABLE ... not in INIT mode\n");
253 /* disable Init mode */
254 mscan_clear_flags(chip, MSCAN_CTL0_INITRQ, MSCAN_CTL0);
256 /* Waits until chip leaves Sleep mode */
257 while (mscan_get_flags(chip, MSCAN_CTL1_INITAK, MSCAN_CTL1) && i++ < MSCAN_MAX_SETTING_WAIT_LOOPS)
260 if (i >= MSCAN_MAX_SETTING_WAIT_LOOPS) {
261 DEBUGMSG("Error leaving Init mode (disable configuration) \n");
266 /* disable Sleep mode */
267 mscan_clear_flags(chip, MSCAN_CTL0_SLPRQ, MSCAN_CTL0);
270 /* Waits until chip leaves Init mode */
271 while (mscan_get_flags(chip, MSCAN_CTL1_SLPAK, MSCAN_CTL1) && i++ < MSCAN_MAX_SETTING_WAIT_LOOPS)
274 if (i >= MSCAN_MAX_SETTING_WAIT_LOOPS) {
275 DEBUGMSG("Error leaving Sleep mode (disable configuration) \n");
280 /* Enable interrupt */
281 can_enable_irq(chip->chip_irq);
283 /* DEBUGMSG("config DISABLE ... OK\n"); */
289 /* ************************************************************************************************************************************* */
292 int mscan_baud_rate(struct canchip_t *chip, int bitrate, int clock, int sjw, int sampl_pt, int flags)
294 /* Set communication parameters.
295 * param rate baud rate in Hz
296 * param clock frequency of mscan clock in Hz
297 * param sjw synchronization jump width (0-3) prescaled clock cycles
298 * param sampl_pt sample point (0-1000) sets (TSEG1 + 1)/(TSEG1 + TSEG2 + 2) ratio
303 /* rate = clock / ((tseg1 + tseg2 + 1) * brp ) */
305 long rate, best_rate = 0;
306 long best_error = 1000000000, error = 0;
307 int best_tseg = 0, best_brp = 0, brp = 0;
308 int tsegall, tseg = 0, tseg1 = 0, tseg2 = 0;
309 int spt = 0, spt_error = best_error;
313 /* Use CIA recommended sample points */
316 if (bitrate > 800000)
318 else if (bitrate > 500000)
324 /* tseg even = round down, odd = round up */
325 for (tseg = MSCAN_TSEG_MAX * 2 + 1; tseg >= MSCAN_TSEG_MIN * 2; tseg--)
327 tsegall = 1 + tseg / 2;
328 /* Compute all possible tseg choices (tseg=tseg1+tseg2) */
329 brp = clock / (tsegall * bitrate) + tseg % 2;
331 if ((brp < MSCAN_BRP_MIN) || (brp > MSCAN_BRP_MAX))
334 /* tseg brp biterror */
335 rate = clock / (brp * tsegall);
336 error = bitrate - rate;
340 if (error > best_error)
345 spt = mscan_update_samplept(sampl_pt, tseg / 2, &tseg1, &tseg2);
346 error = sampl_pt - spt;
350 if (error > spt_error)
355 best_tseg = tseg / 2;
363 /* Error in one-tenth of a percent */
364 error = (best_error * 1000) / bitrate;
365 DEBUGMSG("Baudrate error %lu\n", error);
369 /* recompute with best values */
370 spt = mscan_update_samplept(sampl_pt, best_tseg, &tseg1, &tseg2);
372 DEBUGMSG("Setting %lu bps.\n", best_rate);
374 /* all values has offset -1 in MSCAN memory */
375 best_brp--; tseg1--; tseg2--;
377 btr0 = (best_brp & MSCAN_BTR0_BRP) | ((sjw << 6) & MSCAN_BTR0_SJW);
378 btr1 = (tseg1 & MSCAN_BTR1_TSEG1) | ((tseg2 << 4) & MSCAN_BTR1_TSEG2);
380 mscan_set_btregs(chip, btr0, btr1);
382 mscan_disable_configuration(chip);
384 /* DEBUGMSG("Baud rate set successfully\n"); */
388 int mscan_set_btregs(struct canchip_t *chip, unsigned short bcr0, unsigned short bcr1)
390 /* DEBUGMSG("Seting BCR0 and BCR1.\n"); */
396 btr1 &= ~MSCAN_BTR1_SAMP; /* use one-point sample, not three smaples per bit */
398 DEBUGMSG("BTR0 0x%02x BTR1 0x%02x\n", btr0, btr1);
400 can_write_reg(chip, btr0, MSCAN_BTR0);
401 can_write_reg(chip, btr1, MSCAN_BTR1);
403 /* DEBUGMSG("BCR0 and BCR1 successfully set.\n"); */
408 /* ************************************************************************************************************************************* */
411 int mscan_start_chip(struct canchip_t *chip)
413 /* DEBUGMSG("Starting chip %d...\n", chip->chip_idx); */
415 /* Stop chip turns chip to Sleep&Init mode - traffic on CAN bus is ignored after completing curent operation.
416 * Start chip only turn chip back from Sleep&Init state - using disable_config
418 mscan_disable_configuration(chip);
420 DEBUGMSG("Chip [%d] started\n", chip->chip_idx);
424 int mscan_stop_chip(struct canchip_t *chip)
426 /* DEBUGMSG("Stopping chip %d...\n", chip->chip_idx); */
428 /* Stop chip turns chip to Sleep&Init mode - traffic on CAN bus is ignored after completing curent operation.
429 * - using enable_config
431 mscan_enable_configuration(chip);
433 DEBUGMSG("Chip [%d] stopped\n", chip->chip_idx);
437 int mscan_attach_to_chip(struct canchip_t *chip)
439 /* DEBUGMSG("Attaching to chip %d.\n", chip->chip_idx); */
443 /* Clear all TX and RX buffers */
444 if (mscan_clear_objects(chip))
448 /* Transmitt Abort Request Register (TARQ) is clean after INIT mode - no need to clear it explicitly */
449 /* Control Register 0 (CTL0) is clean after INIT too (excepts fro WUPE, SLRQ and INITRQ) */
451 /* initialize chip by entering Sleep & Init mode */
452 if (mscan_enable_configuration(chip))
455 /* reset Control Register 1 (CTL1) */
456 ctl1 = MSCAN_CTL1_CANE |
457 (MPC5200_CLKSRC ? MSCAN_CTL1_CLKSRC : 0x00) ;
458 /* MSCAN_CTL1_LOOPB | LoopBack mode not used */
459 /* MSCAN_CTL1_LISTEN | Listen-Only mode not used */
460 /* MSCAN_CTL1_WUPM | WakeUp mode not used */
461 /* MSCAN_CTL1_SLPAK | ReadOnly */
462 /* MSCAN_CTL1_INITAK | ReadOnly */
464 can_write_reg(chip, ctl1, MSCAN_CTL1);
467 /* set filter to accept all STD messages */
468 if (mscan_standard_mask(chip, INIT_STD_ID, INIT_STD_MASK))
470 DEBUGMSG("Failed to set initial filter ID: %d Mask: 0x%04x\n", INIT_STD_ID, INIT_STD_MASK);
473 /* set Baudrate and Interrupts */
474 if (mscan_chip_config(chip))
477 /* not neccessary, but just to be sure */
478 if (mscan_disable_configuration(chip))
481 /* Enable interrupt - called in mpc5200_request_io */
482 /* can_enable_irq(chip->chip_irq); */
484 DEBUGMSG("Successfully attached to chip [%02d].\n", chip->chip_idx);
489 int mscan_release_chip(struct canchip_t *chip)
491 /* IRQ unmapped in lincan driver core */
492 can_disable_irq(chip->chip_irq);
494 mscan_clear_objects(chip); /* Cannot be called in INIT mode */
497 mscan_stop_chip(chip); /* we are in INIT mode */
500 mscan_clear_flags(chip, MSCAN_CTL1_CANE, MSCAN_CTL1);
502 DEBUGMSG("Chip released [%02d]\n", chip->chip_idx);
507 /* ************************************************************************************************************************************* */
509 /* has to be called in Init & Sleep mode */
510 int mscan_standard_mask(struct canchip_t *chip, unsigned short code, unsigned short mask)
512 /* code - contains 11bit ID and as LSB the RTR flag */
513 /* code - contains 11bit mask and RTR mask as LSB */
515 reg_t idr0, idr1, mr0, mr1; /* ID register 0,1, Mask register 0, 1 */
517 if (code & 0x1ffff800)
518 return mscan_extended_mask(chip, code, mask);
521 /* we use two 32-bit acceptance filters */
522 mscan_clear_flags(chip, MSCAN_IDAC_IDAM, MSCAN_IDAC);
525 idr0 = (reg_t)((code & 0x0ff0) >> 4); /* 8 most significant bits */
526 idr1 = (reg_t)((code & 0x000f) << 4); /* 3 last bits, RTR as LSB, IDE=0 doesnt have to be set explicitly */
527 mr0 = (reg_t)((mask & 0x0ff0) >> 4);
528 mr1 = (reg_t)(((mask & 0x000f) << 4) & 0xf0); /* to be sure IDE=0 */
531 can_write_reg(chip, idr0, MSCAN_IDAR0);
532 can_write_reg(chip, idr1, MSCAN_IDAR1);
534 can_write_reg(chip, mr0, MSCAN_IDMR0);
535 can_write_reg(chip, mr1, MSCAN_IDMR1);
537 /* use same filtering settings for second filter */
538 can_write_reg(chip, idr0, MSCAN_IDAR4);
539 can_write_reg(chip, idr1, MSCAN_IDAR5);
541 can_write_reg(chip, mr0, MSCAN_IDMR4);
542 can_write_reg(chip, mr1, MSCAN_IDMR5);
545 DEBUGMSG("Set standard_mask [id:0x%04x RTR=%d, m:0x%04x RTR=%d]\n", code >> 1, code & 0x0001, mask >> 1, mask & 0x0001);
551 /* has to be called in Init & Sleep mode */
552 int mscan_extended_mask(struct canchip_t *chip, unsigned long code, unsigned long mask)
554 /* code - contains 11bit ID and as LSB the RTR flag */
555 /* code - contains 11bit mask and RTR mask as LSB */
557 reg_t idr0, idr1, idr2, idr3; /* ID registers 0,1,2,3 */
558 reg_t mr0, mr1, mr2, mr3; /* Mask registers 0,1,2,3 */
561 /* we use two 32-bit acceptance filters */
562 mscan_clear_flags(chip, MSCAN_IDAC_IDAM, MSCAN_IDAC);
565 idr0 = (reg_t)((code & 0x7fa00000) >> 22); /* EXT_ID {29:21} */
567 idr1 = (reg_t)((code & 0x00380000) >> 14); /* EXT_ID {20:18} */
568 idr1|= 0x18; /* SRR and IDE */
569 idr1|= (reg_t)((code & 0x00070000) >> 16); /* EXT_ID {17:15} */
571 idr2 = (reg_t)((code & 0x0000ff00) >> 8); /* EXT_ID {14:7} */
572 idr3 = (reg_t) (code & 0x000000ff); /* EXT_ID {6:0} and RTR */
575 mr0 = (reg_t)((mask & 0x7fa00000) >> 22); /* EXT_ID {29:21} */
577 mr1 = (reg_t)((mask & 0x00380000) >> 14); /* EXT_ID {20:18} */
578 /* SRR=0 and IDE=0 - do not ignore */
579 mr1|= (reg_t)((mask & 0x00070000) >> 16); /* EXT_ID {17:15} */
581 mr2 = (reg_t)((mask & 0x0000ff00) >> 8); /* EXT_ID {14:7} */
582 mr3 = (reg_t) (mask & 0x000000ff); /* EXT_ID {6:0} and RTR */
585 can_write_reg(chip, idr0, MSCAN_IDAR0);
586 can_write_reg(chip, idr1, MSCAN_IDAR1);
587 can_write_reg(chip, idr2, MSCAN_IDAR2);
588 can_write_reg(chip, idr3, MSCAN_IDAR3);
590 can_write_reg(chip, mr0, MSCAN_IDMR0);
591 can_write_reg(chip, mr1, MSCAN_IDMR1);
592 can_write_reg(chip, mr2, MSCAN_IDMR2);
593 can_write_reg(chip, mr3, MSCAN_IDMR3);
595 /* use same filtering settings for second filter */
596 can_write_reg(chip, idr0, MSCAN_IDAR4);
597 can_write_reg(chip, idr1, MSCAN_IDAR5);
598 can_write_reg(chip, idr2, MSCAN_IDAR6);
599 can_write_reg(chip, idr3, MSCAN_IDAR7);
601 can_write_reg(chip, mr0, MSCAN_IDMR4);
602 can_write_reg(chip, mr1, MSCAN_IDMR5);
603 can_write_reg(chip, mr2, MSCAN_IDMR6);
604 can_write_reg(chip, mr3, MSCAN_IDMR7);
607 DEBUGMSG("Set extended_mask [id:0x%08x RTR=%lu, m:0x%08x RTR=%lu]\n", (uint32_t)(code >> 1), code & 0x00000001, (uint32_t)(mask >> 1), mask & 0x00000001);
614 /* ************************************************************************************************************************************* */
617 int mscan_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj)
619 DEBUGRX("Pre read config\n");
621 /* MSCAN has only one buffer, which is already initialized */
626 int mscan_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj, struct canmsg_t *msg)
632 can_spin_lock(&mscan_prewr_lock);
633 can_preempt_disable();
634 DEBUGTX("Pre write config\n");
636 /* find free buffer */
637 txf = mscan_get_flags(chip, MSCAN_TFLG_TXE, MSCAN_TFLG);
638 for (buff_no = 0; buff_no < 3 && !(txf & (0x01 << buff_no)); buff_no++) { }
642 DEBUGTX("no free buffer found [0x%02x]\n", txf);
643 goto pwrite_exit_fail; /* no free buffer found */
648 bf = (reg_t)(0x01 << buff_no);
649 can_write_reg(chip, bf & MSCAN_TBSEL_TX, MSCAN_TBSEL);
651 DEBUGTX("Buffer %d\n", buff_no);
653 mscan_setup_txbuffer(chip, msg);
655 /* store buffer flag into canmsg_t->cob for future
657 * canmsg_t->cob is not used according to Lincan documentation */
661 can_preempt_enable();
662 can_spin_unlock(&mscan_prewr_lock);
666 can_preempt_enable();
667 can_spin_unlock(&mscan_prewr_lock);
668 return -ENODEV; /* no free buffer found */
671 int mscan_send_msg(struct canchip_t *chip, struct msgobj_t *obj, struct canmsg_t *msg)
673 DEBUGTX("Send Message\n");
675 /* turn on IRQ for this buffer */
676 can_write_reg(chip, msg->cob, MSCAN_TIER);
678 /* clear TX Buffer Empty flag (by writing '1') to initiate trasmition */
679 can_write_reg(chip, msg->cob, MSCAN_TFLG);
684 int mscan_remote_request(struct canchip_t *chip, struct msgobj_t *obj)
686 DEBUGMSG("mscan_remote_request not implemented\n");
691 /* ************************************************************************************************************************************* */
694 int mscan_irq_handler(int irq, struct canchip_t *chip)
697 MSCAN_RFLG_CSCIF - CAN Status Change Interrupt Flag
698 MSCAN_RFLG_RSTAT - Receiver Status Bits: 0-RxOK, 1-RxWRN, 2-RxERR, 3-BusOff
699 MSCAN_RFLG_TSTAT - Transmitter Status Bits: 0-TxOK, 1-TxWRN, 2-TxErr, 3-BusOff
700 MSCAN_RFLG_OVRIF - Overrun Interrupt Flag
701 MSCAN_RFLG_RXF - Receive Buffer Full
703 MSCAN_TFLG_TXE - Transmitter Buffer Empty */
706 uint16_t irq_reg, tx_irq;
707 reg_t irq_rstat, irq_tstat;
708 short loop_cnt = MSCAN_MAX_IRQ_WAIT_LOOPS;
710 tx_irq = (MSCAN_TFLG_TXE << 8); /* to spare few tacts in IRQ loop */
712 irq_reg = mscan_get_irq_flags(chip);
713 DEBUGMSG("IRQ Handler chip %d (%d)\n", chip->chip_idx, irq);
718 goto irqhnd_exit_stuck;
720 DEBUGMSG("IRR: 0x%04x\n", irq_reg);
722 /* Received message */
723 if (irq_reg & MSCAN_RFLG_RXF)
725 DEBUGRX("Received message\n");
727 mscan_irq_read_handler(chip, chip->msgobj[0]);
728 /* RXPR flag for this msgobj is cleared during irq_read_handler*/
731 mscan_set_flags(chip, MSCAN_RFLG_RXF, MSCAN_RFLG);
735 /* Can Status change - due to RX/TX error counters */
736 if(irq_reg & MSCAN_RFLG_CSCIF)
738 irq_rstat = (irq_reg >> 4) & 0x03;
739 irq_tstat = (irq_reg >> 2) & 0x03;
742 /* Receive bus off/error/warning */
743 if (irq_rstat ^ rxstat) /* check whether RSTAT changed */
747 case 3: /* Bus off */
748 MSCAN_STAT_CHANGE("RX: BUS OFF", chip->chip_idx);
750 chip->msgobj[0]->ret=-1;
753 mscan_notifyRXends(chip->msgobj[0], CANQUEUE_NOTIFY_ERROR);
756 case 2: /* bus - error passive */
757 MSCAN_STAT_CHANGE("RX: ERROR PASSIVE", chip->chip_idx);
758 /* Show warning only */
761 case 1: /* bus - warning */
762 MSCAN_STAT_CHANGE("RX: Bus Warning", chip->chip_idx);
763 /* Show warning only */
766 case 0: /* bus - OK */
767 MSCAN_STAT_CHANGE("RX: Bus OK", chip->chip_idx);
768 /* Show warning only */
771 rxstat = irq_rstat; /* update static RX status field */
774 /* Transmit bus off/error/warning */
775 if (irq_tstat ^ txstat)
779 case 3: /* Bus off */
780 MSCAN_STAT_CHANGE("TX: BUS OFF", chip->chip_idx);
783 if(chip->msgobj[0]->tx_slot)
784 canque_notify_inends(chip->msgobj[0]->tx_qedge, CANQUEUE_NOTIFY_ERROR);
787 case 2: /* bus - error passive */
788 MSCAN_STAT_CHANGE("TX: ERROR PASSIVE", chip->chip_idx);
789 /* Show warning only */
792 case 1: /* bus - warning */
793 MSCAN_STAT_CHANGE("TX: Bus Warning", chip->chip_idx);
794 /* Show warning only */
797 case 0: /* bus - OK */
798 MSCAN_STAT_CHANGE("TX: Bus OK", chip->chip_idx);
799 /* Show warning only */
802 txstat = irq_tstat; /* update static TX status field */
806 mscan_set_flags(chip, MSCAN_RFLG_CSCIF, MSCAN_RFLG);
809 /* Message Overrun/Overwritten */
810 if (irq_reg & MSCAN_RFLG_OVRIF)
812 CANMSG("Error: MESSAGE OVERRUN/OVERWRITTEN");
814 /* notify only injured RXqueue-end */
815 mscan_notifyRXends(chip->msgobj[0], CANQUEUE_NOTIFY_ERROR);
818 mscan_set_flags(chip, MSCAN_RFLG_OVRIF, MSCAN_RFLG);
821 /* Mailbox empty - after message was sent */
822 if (irq_reg & tx_irq)
824 DEBUGTX("Buffer empty interrupt\n");
826 /* clear propriate TXE IRE Enabled flag */
827 can_spin_lock(&mscan_prewr_lock);
828 mscan_clear_flags(chip, (irq_reg >> 8) & MSCAN_TIER_TXE, MSCAN_TIER);
829 can_spin_unlock(&mscan_prewr_lock);
833 mscan_wakeup_tx(chip, chip->msgobj[0]);
836 irq_reg = mscan_get_irq_flags(chip);
838 /* omit RSTAT and TSTAT - they're used only in CSCIF handler */
841 ~(MSCAN_RFLG_RSTAT | MSCAN_RFLG_TSTAT));
844 return CANCHIP_IRQ_HANDLED;
847 DEBUGMSG("mscan_irq_handler IRQ %d stuck\n", irq);
848 return CANCHIP_IRQ_STUCK;
851 int mscan_irq_accept(int irq, struct canchip_t *chip)
853 DEBUGMSG("mscan_irq_accept NOT IMPLEMENTED\n");
857 int mscan_config_irqs(struct canchip_t *chip, short irqs)
862 DEBUGMSG("config IRQs\n");
864 if (mscan_init_mode_active(chip))
866 DEBUGMSG("MSCAN: Setting Up IRQs while INIT active \n");
870 rier = (reg_t)(irqs & 0x00ff);
871 tier = (reg_t)((irqs >> 8) & 0x00ff);
873 if((err = mscan_clear_irq_flags(chip)))
876 can_write_reg(chip, rier, MSCAN_RIER);
877 can_write_reg(chip, tier, MSCAN_TIER);
879 DEBUGMSG("IRQ Mask set [rier: 0x%02x]\n", rier);
884 /* ************************************************************************************************************************************* */
887 int mscan_clear_objects(struct canchip_t *chip)
889 /* clear RX buffer */
890 mscan_clear_buffer(chip, MSCAN_RXFG);
892 /* clear TX buffers, need to set CANTBSEL register */
893 can_write_reg(chip, 0x01, MSCAN_TBSEL);
894 mscan_clear_buffer(chip, MSCAN_TXFG);
896 can_write_reg(chip, 0x02, MSCAN_TBSEL);
897 mscan_clear_buffer(chip, MSCAN_TXFG);
899 can_write_reg(chip, 0x04, MSCAN_TBSEL);
900 mscan_clear_buffer(chip, MSCAN_TXFG);
905 int mscan_check_tx_stat(struct canchip_t *chip)
907 /* DEBUGMSG("Check TX stat\n"); */
908 /* If Transmition is complete return 0 - no error */
909 if (mscan_get_flags(chip, MSCAN_TFLG_TXE, MSCAN_TFLG) == MSCAN_TFLG_TXE) /* all buffers empty */
915 /* Note: this checks TX status of particular buffer */
916 int mscan_check_txbuff_stat(struct canchip_t *chip, int buffer)
918 /* Transmition is complete return 0 - no error */
919 reg_t txf = mscan_get_flags(chip, MSCAN_TFLG_TXE & (0x01 << buffer), MSCAN_TFLG);
920 return (txf ^ (0x01 << buffer));
923 int mscan_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj)
925 can_preempt_disable();
926 DEBUGMSG("WakeUP TX\n");
928 can_msgobj_set_fl(obj, TX_REQUEST);
929 while(!can_msgobj_test_and_set_fl(obj, TX_LOCK)) {
930 can_msgobj_clear_fl(obj, TX_REQUEST);
932 /* enable transmition only if any TX buffer is empty */
933 if (mscan_get_flags(chip, MSCAN_TFLG_TXE, MSCAN_TFLG))
934 mscan_irq_write_handler(chip, obj);
937 can_msgobj_clear_fl(obj, TX_LOCK);
942 can_msgobj_clear_fl(obj, TX_LOCK);
944 if(!can_msgobj_test_fl(obj, TX_REQUEST))
949 can_preempt_enable();
951 DEBUGMSG("WakeUP TX - END\n");
955 int mscan_filtch_rq(struct canchip_t *chip, struct msgobj_t * obj)
957 struct canfilt_t filter;
962 int num = canqueue_ends_filt_conjuction(obj->qends, &filter);
964 canqueue_ends_filt_conjuction(obj->qends, &filter);
967 DEBUGMSG("CNT: %d ID: 0x%08x MASK: 0x%08x\n", num, (uint32_t) (filter.id) & 0x1fffffff, (uint32_t) (~filter.mask) & 0x1fffffff);
969 /* MSCAN uses oposite logic (compared to IP) for LAFM: 1-ignore bit, 0-use bit as mask */
970 mask = (~filter.mask) << 1;
972 /* RTR is LSB of mask */
973 if (filter.flags & MSG_RTR)
976 if (filter.flags & MSG_EXT) /* Extended ID */
977 return mscan_extended_mask(chip, filter.id, mask);
978 else /* Standard ID */
979 return mscan_standard_mask(chip, filter.id, mask);
983 /* ************************************************************************************************************************************* */
986 void mscan_irq_read_handler(struct canchip_t *chip, struct msgobj_t *obj)
989 if (!mscan_get_flags(chip, MSCAN_RFLG_RXF, MSCAN_RFLG))
992 DEBUGRX("Receive buffer empty\n");
996 mscan_msg_from_rxbuffer(chip, &(obj->rx_msg));
998 /* fill CAN message timestamp */
999 can_filltimestamp(&obj->rx_msg.timestamp);
1001 canque_filter_msg2edges(obj->qends, &obj->rx_msg);
1004 void mscan_irq_write_handler(struct canchip_t *chip, struct msgobj_t *obj)
1008 DEBUGTX("Irq write handler\n");
1011 /* Do local transmitted message distribution if enabled */
1013 /* fill CAN message timestamp */
1014 can_filltimestamp(&obj->tx_slot->msg.timestamp);
1016 obj->tx_slot->msg.flags |= MSG_LOCAL;
1017 canque_filter_msg2edges(obj->qends, &obj->tx_slot->msg);
1019 /* Free transmitted slot */
1020 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
1024 cmd = canque_test_outslot(obj->qends, &obj->tx_qedge, &obj->tx_slot);
1028 if (chip->chipspecops->pre_write_config(chip, obj, &obj->tx_slot->msg)) {
1030 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_PREP);
1031 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
1032 obj->tx_slot = NULL;
1035 if (chip->chipspecops->send_msg(chip, obj, &obj->tx_slot->msg)) {
1037 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_SEND);
1038 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
1039 obj->tx_slot = NULL;
1045 /* ************************************************************************************************************************************* */
1048 int mscan_register(struct chipspecops_t *chipspecops)
1050 chipspecops->chip_config = mscan_chip_config;
1051 chipspecops->enable_configuration = mscan_enable_configuration;
1052 chipspecops->disable_configuration = mscan_disable_configuration;
1054 chipspecops->baud_rate = mscan_baud_rate;
1055 chipspecops->set_btregs = mscan_set_btregs;
1057 chipspecops->start_chip = mscan_start_chip;
1058 chipspecops->stop_chip = mscan_stop_chip;
1059 chipspecops->attach_to_chip = mscan_attach_to_chip;
1060 chipspecops->release_chip = mscan_release_chip;
1062 chipspecops->standard_mask = mscan_standard_mask;
1063 chipspecops->extended_mask = mscan_extended_mask;
1064 chipspecops->message15_mask = NULL; /* mscan_message15_mask; */
1066 chipspecops->pre_read_config = mscan_pre_read_config;
1067 chipspecops->pre_write_config = mscan_pre_write_config;
1068 chipspecops->send_msg = mscan_send_msg;
1069 chipspecops->remote_request = mscan_remote_request;
1071 chipspecops->irq_handler = mscan_irq_handler;
1072 chipspecops->irq_accept = NULL; /* mscan_irq_accept; */
1073 chipspecops->config_irqs = mscan_config_irqs;
1075 chipspecops->clear_objects = mscan_clear_objects;
1076 chipspecops->check_tx_stat = mscan_check_tx_stat;
1077 chipspecops->wakeup_tx = mscan_wakeup_tx;
1078 chipspecops->filtch_rq = mscan_filtch_rq;
1082 int mscan_fill_chipspecops(struct canchip_t *chip)
1084 chip->chip_type = "mscan";
1085 chip->max_objects = 1;
1086 chip->write_register = chip->hostdevice->hwspecops->write_register;
1087 chip->read_register = chip->hostdevice->hwspecops->read_register;
1103 chip->worker_thread;
1108 mscan_register(chip->chipspecops);
1113 /* ************************************************************************************************************************************* */
1116 int mscan_reset_chip(struct canchip_t * chip)
1118 DEBUGMSG("chip reset \n");
1120 /* reset chip by turning MSCAN off and on in INIT mode */
1121 if (mscan_enable_configuration(chip))
1124 mscan_clear_flags(chip, MSCAN_CTL1_CANE, MSCAN_CTL1);
1125 mscan_set_flags(chip, MSCAN_CTL1_CANE, MSCAN_CTL1);
1127 if (mscan_disable_configuration(chip))
1130 /* Abort all pending messages */
1131 mscan_abort_msg(chip, MSCAN_TARQ_ABTRQ);
1133 DEBUGMSG("chip reset DONE\n");
1138 /* mscan_clear_irq_flags should be called only when not in INIT mode */
1139 int mscan_clear_irq_flags(struct canchip_t *chip)
1141 /* do not clear TXE flags -> it forces chip to send messages in buffers */
1144 if (mscan_init_mode_active(chip))
1146 DEBUGMSG("MSCAN: Clearing IRQs while INIT active \n");
1150 DEBUGMSG("Clearing IRQ flags...\n");
1152 rflg = MSCAN_RFLG_WUPIF | MSCAN_RFLG_CSCIF | MSCAN_RFLG_RSTAT |
1153 MSCAN_RFLG_TSTAT | MSCAN_RFLG_OVRIF | MSCAN_RFLG_RXF;
1155 /* reset flags by writing '1' */
1156 can_write_reg(chip, rflg, MSCAN_RFLG);
1162 /* ************************************************************************************************************************************* */
1165 void mscan_notifyRXends(struct msgobj_t * obj, int what)
1167 struct canque_edge_t * edge;
1168 canque_for_each_inedge(obj->qends, edge){
1169 canque_notify_outends(edge, what);
1173 /* Fill message content to one transmit buffers */
1174 /* Note: Check whether buffer is empy has to be done before calling this function */
1175 void mscan_setup_txbuffer(struct canchip_t * chip, struct canmsg_t * msg)
1177 volatile struct mscan_msg_buffer * txb = (struct mscan_msg_buffer *)(chip->chip_base_addr + MSCAN_TXFG);
1181 if (msg->flags & MSG_RTR)
1186 /* set Can mesage ID and local priority */
1187 if (msg->flags & MSG_EXT)
1190 txb->id_0 = (reg_t)((msg->id >> 21) & 0x000000ff);
1191 txb->id_1 = (reg_t)(
1192 ((msg->id >> 18) & 0x000000e0) |
1193 0x00000018 | /* SRR & IDE */
1194 ((msg->id >> 15) & 0x00000003));
1195 txb->id_2 = (reg_t)((msg->id >> 7) & 0x000000ff);
1196 txb->id_3 = (reg_t)(((msg->id << 1) & 0x000000fe) | rtr);
1198 /* local priority is 7 MSB bits followed by IDE flag */
1199 txb->local_prio = (reg_t)((txb->id_0 & 0xfe) | 0x01); /* IDE=1 */
1204 txb->id_0 = (reg_t)((msg->id >> 3) & 0x000000ff);
1205 txb->id_1 = (reg_t)(((msg->id << 5) & 0x000000e0) | (rtr << 4)); /* IDE=0 */
1209 /* local priority are 7 MSB bits folowed by IDE flag */
1210 txb->local_prio = (reg_t)(txb->id_0 & 0xfe); /* IDE=0 */
1214 switch (msg->length)
1216 case 8: txb->data_7 = msg->data[7];
1217 case 7: txb->data_6 = msg->data[6];
1218 case 6: txb->data_5 = msg->data[5];
1219 case 5: txb->data_4 = msg->data[4];
1220 case 4: txb->data_3 = msg->data[3];
1221 case 3: txb->data_2 = msg->data[2];
1222 case 2: txb->data_1 = msg->data[1];
1223 case 1: txb->data_0 = msg->data[0];
1227 txb->data_len = (reg_t)(msg->length & 0x1f);
1229 DUMPBUFF(chip, MSCAN_TXFG);
1232 /* Fill message content from receive buffer */
1233 void mscan_msg_from_rxbuffer(struct canchip_t * chip, struct canmsg_t * msg)
1235 struct mscan_msg_buffer * rxb = (struct mscan_msg_buffer *)(chip->chip_base_addr + MSCAN_RXFG);
1237 /* retrieve Can mesage ID */
1238 msg->flags = 0; /* clear all */
1240 /* check buffer IDE flag */
1241 if (mscan_get_flags(chip, (reg_t)0x08, MSCAN_RXFG + MSCAN_MSGBUFF_ID1)) /* 0x08 - IDE flag in ID1 */
1243 DEBUGMSG("Ext ID\n");
1245 msg->id = (((uint32_t)rxb->id_0 << 21) & 0x3fa00000) |
1246 (((uint32_t)rxb->id_1 << 18) & 0x00380000) |
1247 (((uint32_t)rxb->id_1 << 15) & 0x00070000) |
1248 (((uint32_t)rxb->id_2 << 7 ) & 0x0000ff00) |
1249 (((uint32_t)rxb->id_3 >> 1 ) & 0x000000ff);
1252 if (rxb->id_3 & 0x01)
1253 msg->flags |= MSG_RTR;
1256 msg->flags |= MSG_EXT;
1260 DEBUGMSG("std ID\n");
1262 msg->id = (((uint32_t)rxb->id_0 << 3) & 0x000007f8) |
1263 (((uint32_t)rxb->id_1 >> 5) & 0x00000007);
1266 if (rxb->id_1 & 0x08)
1267 msg->flags |= MSG_RTR;
1269 /* no EXT flag is set here */
1273 switch (rxb->data_len)
1275 case 8: msg->data[7] = rxb->data_7;
1276 case 7: msg->data[6] = rxb->data_6;
1277 case 6: msg->data[5] = rxb->data_5;
1278 case 5: msg->data[4] = rxb->data_4;
1279 case 4: msg->data[3] = rxb->data_3;
1280 case 3: msg->data[2] = rxb->data_2;
1281 case 2: msg->data[1] = rxb->data_1;
1282 case 1: msg->data[0] = rxb->data_0;
1286 msg->length = (reg_t)(rxb->data_len & 0x1f);
1288 /* updates the TSEG1 and TSEG2 according to overall TSEG and Sample Point (0-1000) */
1289 static int mscan_update_samplept(int sampl_pt, int tseg, int *tseg1, int *tseg2)
1291 /* tseg = tseg1 + tseg2, its NOT tsegall !
1292 * difference between tseg and tsegall is:
1293 * tsegall = tseg + 1
1296 *tseg2 = tseg + 1 - (sampl_pt * (tseg + 1)) / 1000;
1297 if (*tseg2 < MSCAN_TSEG2_MIN)
1298 *tseg2 = MSCAN_TSEG2_MIN;
1299 if (*tseg2 > MSCAN_TSEG2_MAX)
1300 *tseg2 = MSCAN_TSEG2_MAX;
1301 *tseg1 = tseg - *tseg2;
1302 if (*tseg1 > MSCAN_TSEG1_MAX) {
1303 *tseg1 = MSCAN_TSEG1_MAX;
1304 *tseg2 = tseg - *tseg1;
1306 return 1000 * (*tseg1 + 1) / (tseg + 1);
1310 static int mscan_init_mode_active(struct canchip_t *chip)
1312 /* Init request AND Init ACK */
1313 /* DEBUGMSG(" is Init active?\n"); */
1314 return mscan_get_flags(chip, MSCAN_CTL0_INITRQ, MSCAN_CTL0) &&
1315 mscan_get_flags(chip, MSCAN_CTL1_INITAK, MSCAN_CTL1);
1317 static int mscan_sleep_mode_active(struct canchip_t *chip)
1319 /* Sleep Request AND Sleep Ack */
1320 return mscan_get_flags(chip, MSCAN_CTL0_SLPRQ, MSCAN_CTL0) &&
1321 mscan_get_flags(chip, MSCAN_CTL1_SLPAK, MSCAN_CTL1);
1324 static int mscan_enter_init_mode(struct canchip_t * chip)
1326 int i = MSCAN_MAX_SETTING_WAIT_LOOPS + 1;
1328 mscan_set_flags(chip, MSCAN_CTL0_INITRQ, MSCAN_CTL0);
1330 /* Waits until chip enters Init mode */
1331 while (!mscan_get_flags(chip, MSCAN_CTL1_INITAK, MSCAN_CTL1) && --i)
1336 DEBUGMSG("Error entering Init mode (enable configuration) \n");
1342 static int mscan_enter_sleep_mode(struct canchip_t * chip)
1344 int i = MSCAN_MAX_SETTING_WAIT_LOOPS + 1;
1346 if (mscan_sleep_mode_active(chip))
1348 DEBUGMSG("Already in sleep mode or not synced to Bus\n");
1352 /* DEBUGMSG("isSynced: 0x%02x\n",mscan_get_flags(chip, MSCAN_CTL0_SYNCH, MSCAN_CTL0)); */
1354 mscan_set_flags(chip, MSCAN_CTL0_SLPRQ, MSCAN_CTL0);
1356 /* Waits until chip enters Sleep mode - finishes current TX/RX operation */
1357 while (!mscan_get_flags(chip, MSCAN_CTL1_SLPAK, MSCAN_CTL1) && --i)
1362 DEBUGMSG("Error entering Sleep mode (enable configuration) \n");
1371 static reg_t mscan_get_flags(struct canchip_t * chip, reg_t flags, unsigned reg_addr)
1373 /* DEBUGMSG(" get flags [%u]\n", reg_addr); */
1374 return (reg_t)can_read_reg(chip, reg_addr) & flags;
1376 static void mscan_set_flags(struct canchip_t * chip, reg_t flags, unsigned reg_addr)
1378 reg_t r = can_read_reg(chip, reg_addr);
1379 can_write_reg(chip, r | flags, reg_addr);
1381 static void mscan_clear_flags(struct canchip_t * chip, reg_t flags, unsigned reg_addr)
1383 reg_t r = can_read_reg(chip, reg_addr);
1384 can_write_reg(chip, r & ~flags, reg_addr);
1386 static uint16_t mscan_get_irq_flags(struct canchip_t * chip)
1388 /* Transmit Buffer Empty only if enabled */
1389 return ((mscan_get_flags(chip, MSCAN_TIER_TXE, MSCAN_TIER) &
1390 mscan_get_flags(chip, MSCAN_TFLG_TXE, MSCAN_TFLG)) << 8) |
1391 (mscan_get_flags(chip, (reg_t)(mscan_IRQs & 0xff), MSCAN_RFLG));
1395 static void mscan_clear_buffer(struct canchip_t * chip, unsigned start_addr)
1397 /* clear 25 registers of buffer, others are reset to 0-no need to clean them */
1399 for (addr = start_addr; addr < 26; addr++)
1400 can_write_reg(chip, 0x00, addr);
1403 static int mscan_abort_msg(struct canchip_t * chip, reg_t buffer_mask)
1406 int i = MSCAN_MAX_SETTING_WAIT_LOOPS + 1;
1409 m = buffer_mask & MSCAN_TARQ_ABTRQ;
1411 /* It's not neccessary to abort empy message */
1412 m &= (~mscan_get_flags(chip, MSCAN_TFLG_TXE, MSCAN_TFLG));
1416 DEBUGMSG("nothing to abort\n");
1417 goto abortmsg_exit_ok;
1421 /* set TARQ - Transmitt Abort Request */
1422 mscan_set_flags(chip, m, MSCAN_TARQ);
1425 /* Waits until chip acknowleges abortition */
1426 while (mscan_get_flags(chip, MSCAN_TAAK_ABTAK, MSCAN_TAAK) != m && --i)
1431 DEBUGMSG("Error waiting for Message Abort [requested: 0x%02x]\n", m);
1432 goto abortmsg_exit_fail;