1 /**************************************************************************/
2 /* File: hcan2.h - Renesas SH7760 HCAN2 controller support */
4 /* LinCAN - (Not only) Linux CAN bus driver */
5 /* Copyright (C) 2002-2009 DCE FEE CTU Prague <http://dce.felk.cvut.cz> */
6 /* Copyright (C) 2002-2009 Pavel Pisa <pisa@cmp.felk.cvut.cz> */
7 /* Copyright (C) 2007-2008 Martin Petera <peterm4@fel.cvut.cz> */
8 /* Funded by OCERA and FRESCOR IST projects */
9 /* Based on CAN driver code by Arnaud Westenberg <arnaud@wanadoo.nl> */
11 /* LinCAN is free software; you can redistribute it and/or modify it */
12 /* under terms of the GNU General Public License as published by the */
13 /* Free Software Foundation; either version 2, or (at your option) any */
14 /* later version. LinCAN is distributed in the hope that it will be */
15 /* useful, but WITHOUT ANY WARRANTY; without even the implied warranty */
16 /* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */
17 /* General Public License for more details. You should have received a */
18 /* copy of the GNU General Public License along with LinCAN; see file */
19 /* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, */
20 /* Cambridge, MA 02139, USA. */
22 /* To allow use of LinCAN in the compact embedded systems firmware */
23 /* and RT-executives (RTEMS for example), main authors agree with next */
24 /* special exception: */
26 /* Including LinCAN header files in a file, instantiating LinCAN generics */
27 /* or templates, or linking other files with LinCAN objects to produce */
28 /* an application image/executable, does not by itself cause the */
29 /* resulting application image/executable to be covered by */
30 /* the GNU General Public License. */
31 /* This exception does not however invalidate any other reasons */
32 /* why the executable file might be covered by the GNU Public License. */
33 /* Publication of enhanced or derived LinCAN files is required although. */
34 /**************************************************************************/
36 int hcan2_chip_config(struct canchip_t *chip);
37 int hcan2_enable_configuration(struct canchip_t *chip);
38 int hcan2_disable_configuration(struct canchip_t *chip);
40 int hcan2_baud_rate(struct canchip_t *chip, int rate, int clock, int sjw, int sampl_pt, int flags);
41 int hcan2_set_btregs(struct canchip_t *chip, unsigned short btr0, unsigned short btr1);
43 int hcan2_start_chip(struct canchip_t *chip);
44 int hcan2_stop_chip(struct canchip_t *chip);
45 int hcan2_attach_to_chip(struct canchip_t *chip);
46 int hcan2_release_chip(struct canchip_t *chip);
48 int hcan2_standard_mask(struct canchip_t *chip, unsigned short code, unsigned short mask);
49 int hcan2_extended_mask(struct canchip_t *chip, unsigned long code, unsigned long mask);
50 int hcan2_message15_mask(int irq, struct canchip_t *chip);
52 int hcan2_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj);
53 int hcan2_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj, struct canmsg_t *msg);
54 int hcan2_send_msg(struct canchip_t *chip, struct msgobj_t *obj, struct canmsg_t *msg);
55 int hcan2_remote_request(struct canchip_t *chip, struct msgobj_t *obj);
57 int hcan2_irq_handler(int irq, struct canchip_t *chip);
58 int hcan2_irq_accept(int irq, struct canchip_t *chip);
59 int hcan2_config_irqs(struct canchip_t *chip, short irqs);
61 int hcan2_clear_objects(struct canchip_t *chip);
62 int hcan2_check_tx_stat(struct canchip_t *chip);
63 int hcan2_check_MB_tx_stat(struct canchip_t *chip, struct msgobj_t *obj);
64 int hcan2_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj);
65 int hcan2_filtch_rq(struct canchip_t *chip, struct msgobj_t * obj);
67 int hcan2_register(struct chipspecops_t *chipspecops);
68 int hcan2_fill_chipspecops(struct canchip_t *chip);
70 int hcan2_reset_chip(struct canchip_t *chip);
73 extern inline void can_write_reg_w(const struct canchip_t *pchip, uint16_t data, unsigned reg)
75 can_ioptr_t address = pchip->chip_base_addr + reg;
76 #ifndef CONFIG_OC_LINCAN_DYNAMICIO
78 #else /*CONFIG_OC_LINCAN_DYNAMICIO*/
79 pchip->write_register(data, address);
80 #endif /*CONFIG_OC_LINCAN_DYNAMICIO*/
83 extern inline uint16_t can_read_reg_w(const struct canchip_t *pchip, unsigned reg)
85 can_ioptr_t address = pchip->chip_base_addr + reg;
86 #ifndef CONFIG_OC_LINCAN_DYNAMICIO
87 return readw(address);
88 #else /*CONFIG_OC_LINCAN_DYNAMICIO*/
89 return pchip->read_register(address);
90 #endif /*CONFIG_OC_LINCAN_DYNAMICIO*/
94 /* BasicCAN mode address map */
95 #define HCAN2_MCR 0x00000000 /* Master control register */
96 #define HCAN2_GSR 0x00000002 /* General status register */
97 #define HCAN2_BCR1 0x00000004 /* Bit configuration register 1 */
98 #define HCAN2_BCR0 0x00000006 /* Bit configuration register 0 */
99 #define HCAN2_IRR 0x00000008 /* Interrupt request register */
100 #define HCAN2_IMR 0x0000000a /* Interrupt mask register */
101 #define HCAN2_TECREC 0x0000000c /* 15:8 Transmit error counter 7:0 Receive error counter */
102 #define HCAN2_TXPR1 0x00000020 /* Transmit pending request register 1 */
103 #define HCAN2_TXPR0 0x00000022 /* Transmit pending request register 0 */
104 #define HCAN2_TXCR1 0x00000028 /* Transmit cancel register 1 */
105 #define HCAN2_TXCR0 0x0000002a /* Transmit cancel register 0 */
106 #define HCAN2_TXACK1 0x00000030 /* Transmit acknowledge register 1 */
107 #define HCAN2_TXACK0 0x00000032 /* Transmit acknowledge register 0 */
108 #define HCAN2_ABACK1 0x00000038 /* Abort acknowledge register 1 */
109 #define HCAN2_ABACK0 0x0000003a /* Abort acknowledge register 0 */
110 #define HCAN2_RXPR1 0x00000040 /* Receive data frame pending register 1 */
111 #define HCAN2_RXPR0 0x00000042 /* Receive data frame pending register 0 */
112 #define HCAN2_RFPR1 0x00000048 /* Remote frame request pending register 1 */
113 #define HCAN2_RFPR0 0x0000004a /* Remote frame request pending register 0 */
114 #define HCAN2_MBIMR1 0x00000050 /* Mailbox interrupt mask register 1 */
115 #define HCAN2_MBIMR0 0x00000052 /* Mailbox interrupt mask register 0 */
116 #define HCAN2_UMSR1 0x00000058 /* Unread message status register 1 */
117 #define HCAN2_UMSR0 0x0000005a /* Unread message status register 0 */
118 #define HCAN2_TCNTR 0x00000080 /* Timer counter register */
119 #define HCAN2_TCR 0x00000082 /* Timer control register */
120 #define HCAN2_TCMR 0x00000084 /* Timer Compare Match register */
121 #define HCAN2_TDCR 0x00000086
122 #define HCAN2_LOSR 0x00000088
123 #define HCAN2_ICR1 0x0000008e
124 #define HCAN2_TCMR0 0x00000090 /* Timer compare match register */
125 #define HCAN2_TCMR1 0x00000092
126 #define HCAN2_TCMR2 0x00000094
127 #define HCAN2_CCR 0x00000096
128 #define HCAN2_CMAX 0x00000098
129 #define HCAN2_TMR 0x0000009a
131 /* BaudRate minimal and maximal TSEG values */
140 /* bits 15 to 8 are used for test mode */
141 HCAN2_MCR_AWAKE = 1 << 7, /* Auto Wake Mode */
142 HCAN2_MCR_SLEEP = 1 << 5, /* Sleep Mode */
143 HCAN2_MCR_TXP = 1 << 2, /* Transmition Priority 0-message ID number priority, 1-mailbox number piority*/
144 HCAN2_MCR_HALT = 1 << 1, /* Halt Request */
145 HCAN2_MCR_RESET = 1 << 0, /* Reset Request */
149 HCAN2_GSR_EPS = 1 << 5, /* Error Passive Status */
150 HCAN2_GSR_HSS = 1 << 4, /* Halt/Sleep Status */
151 HCAN2_GSR_RESET = 1 << 3, /* Reset Status */
152 HCAN2_GSR_TXC = 1 << 2, /* Message Transmission Complete Flag */
153 HCAN2_GSR_TXRXW = 1 << 1, /* Transmit/Receive Warning Flag */
154 HCAN2_GSR_BOFF = 1 << 0, /* Buss Off Flag */
157 /* IRR and IMR register */
159 HCAN2_IRR_TCMI = 1 << 14, /* Time Compare Match Register */
160 HCAN2_IRR_TOI = 1 << 13, /* Time Overrun Interrupt */
161 HCAN2_IRR_WUBA = 1 << 12, /* Wake-up on Bus Activity */
162 HCAN2_IRR_MOOI = 1 << 9, /* Message Overrun/Overwrite Interrupt Flag */
163 HCAN2_IRR_MBEI = 1 << 8, /* Messagebox Empty Interrupt Flag */
164 HCAN2_IRR_OF = 1 << 7, /* Overload Frame */
165 HCAN2_IRR_BOI = 1 << 6, /* Bus Off Interrupt Flag */
166 HCAN2_IRR_EPI = 1 << 5, /* Error Passive Interrupt Flag */
167 HCAN2_IRR_ROWI = 1 << 4, /* Receive Overload Warning Interrupt Flag */
168 HCAN2_IRR_TOWI = 1 << 3, /* Transmit Overload Warining Interrupt Flag */
169 HCAN2_IRR_RFRI = 1 << 2, /* Remote Frame Request Interrupt Flag */
170 HCAN2_IRR_DFRI = 1 << 1, /* Data Frame Received Interrupt Flag */
171 HCAN2_IRR_RHSI = 1 << 0, /* Reset/Halt/Sleep Interrupt Flag */
174 /* Message box 0-31 */
175 #define HCAN2_MB0 0x00000100 /* RECEIVE ONLY */
176 #define HCAN2_MB_OFFSET 0x00000020
178 /* Message box structure offsets */
179 #define HCAN2_MB_CTRL0 0x00000000 /* Control 0 */
180 #define HCAN2_MB_CTRL1 0x00000002 /* Control 1 */
181 #define HCAN2_MB_CTRL2 0x00000004 /* Control 2 */
182 #define HCAN2_MB_TSTP 0x00000006 /* Time stamp */
183 #define HCAN2_MB_DATA0 0x00000009 /* Data 0 */
184 #define HCAN2_MB_DATA1 0x00000008 /* Data 1 */
185 #define HCAN2_MB_DATA2 0x0000000b /* Data 2 */
186 #define HCAN2_MB_DATA3 0x0000000a /* Data 3 */
187 #define HCAN2_MB_DATA4 0x0000000d /* Data 4 */
188 #define HCAN2_MB_DATA5 0x0000000c /* Data 5 */
189 #define HCAN2_MB_DATA6 0x0000000f /* Data 6 */
190 #define HCAN2_MB_DATA7 0x0000000e /* Data 7 */
191 #define HCAN2_MB_MASK 0x00000010 /* Acceptance filter mask 4 bytes */
193 /* Control register 0 */
195 HCAN2_MBCT0_STDID = 0x7ff0, /* STD ID */
196 HCAN2_MBCT0_RTR = 0x0008, /* Remote transmition request 0-DataFrame 1-RemoteFrame */
197 HCAN2_MBCT0_IDE = 0x0004, /* Identifier extension 0-Standard 1-Extended */
198 HCAN2_MBCT0_EXTID = 0x0003 /* EXTID 17:16 */
201 /* Control register 1 */
202 /* whole register is EXTD ID 15:0 */
204 /* Control register 2 */
206 HCAN2_MBCT2_NMC = 1<<13, /* New message control */
207 HCAN2_MBCT2_ATX = 1<<12, /* Automatic transmition of data frame */
208 HCAN2_MBCT2_DART = 1<<11, /* Disable automatic re-transmition */
209 HCAN2_MBCT2_MBC = 7<<8, /* Mailbox configuration */
210 HCAN2_MBCT2_CBE = 1<<5, /* CAN bus error */
211 HCAN2_MBCT2_DLC = 0xf /* Data length code */
214 /* MessageBox modes */
216 HCAN2_MBMOD_TXDR = 0, /* Transmit Data and Remote Frame */
217 HCAN2_MBMOD_TXDR_RXR = 1, /* Transmit Data and Remote Frame, Receive Remote Frame */
218 HCAN2_MBMOD_RXDR = 2, /* Receive Data and Remote Frame */
219 HCAN2_MBMOD_RXD = 3, /* Receive Data Frame */
220 HCAN2_MBMOD_TXR_RXDR = 4, /* Transmit Remote Frame, Receive Data and Remove Frame */
221 HCAN2_MBMOD_TXR_RXD = 5, /* Transmit Remote Frame, Receive Data Frame */
222 /* 6 is not used and prohibited */
223 HCAN2_MBMOD_INNACTIVE = 7, /* Mailboc Innactive */