1 /**************************************************************************/
2 /* File: c_can.h - generic C_CAN Bosch IP core handling */
3 /* The C_CAN core is found in Hynix HMS30c7202 and OKI OKI ML9620 devices */
5 /* LinCAN - (Not only) Linux CAN bus driver */
6 /* Copyright (C) 2002-2009 DCE FEE CTU Prague <http://dce.felk.cvut.cz> */
7 /* Copyright (C) 2002-2009 Pavel Pisa <pisa@cmp.felk.cvut.cz> */
8 /* Copyright (C) 2004 Sebastian Stolzenberg <stolzi@sebastian-stolzenberg.de> */
9 /* Funded by OCERA and FRESCOR IST projects */
10 /* Based on CAN driver code by Arnaud Westenberg <arnaud@wanadoo.nl> */
11 /* and Ake Hedman, eurosource <akhe@eurosource.se> */
13 /* LinCAN is free software; you can redistribute it and/or modify it */
14 /* under terms of the GNU General Public License as published by the */
15 /* Free Software Foundation; either version 2, or (at your option) any */
16 /* later version. LinCAN is distributed in the hope that it will be */
17 /* useful, but WITHOUT ANY WARRANTY; without even the implied warranty */
18 /* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */
19 /* General Public License for more details. You should have received a */
20 /* copy of the GNU General Public License along with LinCAN; see file */
21 /* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, */
22 /* Cambridge, MA 02139, USA. */
24 /* To allow use of LinCAN in the compact embedded systems firmware */
25 /* and RT-executives (RTEMS for example), main authors agree with next */
26 /* special exception: */
28 /* Including LinCAN header files in a file, instantiating LinCAN generics */
29 /* or templates, or linking other files with LinCAN objects to produce */
30 /* an application image/executable, does not by itself cause the */
31 /* resulting application image/executable to be covered by */
32 /* the GNU General Public License. */
33 /* This exception does not however invalidate any other reasons */
34 /* why the executable file might be covered by the GNU Public License. */
35 /* Publication of enhanced or derived LinCAN files is required although. */
36 /**************************************************************************/
39 * optimized inline version, may it be, that it can be too fast for the chip
41 extern inline void c_can_write_reg_w(const struct canchip_t *pchip, u16 data, unsigned reg)
43 can_ioptr_t address = pchip->chip_base_addr + reg;
44 #ifndef CONFIG_OC_LINCAN_DYNAMICIO
46 #else /*CONFIG_OC_LINCAN_DYNAMICIO*/
47 pchip->write_register(data, address);
48 #endif /*CONFIG_OC_LINCAN_DYNAMICIO*/
51 extern inline u16 c_can_read_reg_w(const struct canchip_t *pchip, unsigned reg)
53 can_ioptr_t address = pchip->chip_base_addr + reg;
54 #ifndef CONFIG_OC_LINCAN_DYNAMICIO
55 return readw(address);
56 #else /*CONFIG_OC_LINCAN_DYNAMICIO*/
57 return pchip->read_register(address);
58 #endif /*CONFIG_OC_LINCAN_DYNAMICIO*/
61 extern can_spinlock_t c_can_spwlock; // Spin lock for write operations
62 extern can_spinlock_t c_can_sprlock; // Spin lock for read operations
63 extern can_spinlock_t c_can_if1lock; // spin lock for the if1 register
64 extern can_spinlock_t c_can_if2lock; // spin lcok for the if2 register
66 int c_can_if1_busycheck(struct canchip_t *pchip);
67 int c_can_if2_busycheck(struct canchip_t *pchip);
69 int c_can_enable_configuration(struct canchip_t *pchip);
70 int c_can_disable_configuration(struct canchip_t *pchip);
71 int c_can_chip_config(struct canchip_t *pchip);
72 int c_can_baud_rate(struct canchip_t *chip, int rate, int clock,
73 int sjw, int sampl_pt, int flags);
74 int c_can_mask(struct msgobj_t *pmsgobj,
77 int c_can_use_mask(struct msgobj_t *pmsgobj,
79 int c_can_clear_objects(struct canchip_t *pchip);
80 int c_can_config_irqs(struct canchip_t *pchip,
82 int c_can_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj);
83 int c_can_send_msg(struct canchip_t *pchip, struct msgobj_t *pmsgobj,
84 struct canmsg_t *pmsg);
85 int c_can_remote_request(struct canchip_t *pchip, struct msgobj_t *pmsgobj );
86 int c_can_set_btregs(struct canchip_t *chip,
89 int c_can_start_chip(struct canchip_t *pchip);
90 int c_can_stop_chip(struct canchip_t *pchip);
91 int c_can_check_tx_stat(struct canchip_t *pchip);
93 int c_can_register(struct chipspecops_t *chipspecops);
95 void c_can_registerdump(struct canchip_t *pchip);
97 void c_can_if1_registerdump(struct canchip_t *pchip);
99 void c_can_irq_sync_activities(struct canchip_t *chip, struct msgobj_t *obj);
101 int c_can_irq_handler(int irq, struct canchip_t *pchip);
103 int c_can_fill_chipspecops(struct canchip_t *pchip);
105 /* The CCCE register is not implemented in version 1.2 of C_CAN */
106 #undef C_CAN_WITH_CCCE
108 /* The mask of C_CAN registers offsets */
109 #define C_CAN_REGOFFS_MASK 0xFF
111 /* SSEE C_CAN Memory map */
112 /* BasicCAN offsets are multiplied by two */
113 #define CCCR 0x00 /* Control Register */
114 #define CCSR 0x02 /* Status Register */
115 #define CCEC 0x04 /* Error Counting Register */
116 #define CCBT 0x06 /* Bit Timing Register */
117 #define CCINTR 0x08 /* Interrupt Register */
118 #define CCTR 0x0A /* Test Register */
119 #define CCBRPE 0x0C /* Baud Rate Prescaler Extension Register */
121 #ifdef C_CAN_WITH_CCCE
122 #define CCCE 0x0E /* CAN Enable Register */
123 #endif /*C_CAN_WITH_CCCE*/
125 #define CCIF1CR 0x10 /* Interface 1 Command Request Register */
126 #define CCIF1CM 0x12 /* IF1 Command Mask Register */
127 #define CCIF1M1 0x14 /* IF1 Mask 1 Register */
128 #define CCIF1M2 0x16 /* IF1 Mask 2 Register */
129 #define CCIF1A1 0x18 /* IF1 Arbitration 1 Register */
130 #define CCIF1A2 0x1A /* IF1 Arbitration 2 Register */
131 #define CCIF1DMC 0x1C /* IF1 Message Control Register */
132 #define CCIF1DA1 0x1E /* IF1 Data A 1 Register */
133 #define CCIF1DA2 0x20 /* IF1 Data A 2 Register */
134 #define CCIF1DB1 0x22 /* IF1 Data B 1 Register */
135 #define CCIF1DB2 0x24 /* IF1 Data B 2 Register */
137 #define CCIF2CR 0x40 /* Interface 2 Command Request Register */
138 #define CCIF2CM 0x42 /* IF2 Command Mask Register */
139 #define CCIF2M1 0x44 /* IF2 Mask 1 Register */
140 #define CCIF2M2 0x46 /* IF2 Mask 2 Register */
141 #define CCIF2A1 0x48 /* IF2 Arbitration 1 Register */
142 #define CCIF2A2 0x4A /* IF2 Arbitration 2 Register */
143 #define CCIF2DMC 0x4C /* IF2 Message Control Register */
144 #define CCIF2DA1 0x4E /* IF2 Data A 1 Register */
145 #define CCIF2DA2 0x50 /* IF2 Data A 2 Register */
146 #define CCIF2DB1 0x52 /* IF2 Data B 1 Register */
147 #define CCIF2DB2 0x54 /* IF2 Data B 2 Register */
149 #define CCTREQ1 0x80 /* Transmission Request 1 Register */
150 #define CCTREQ2 0x82 /* Transmission Request 2 Register */
152 #define CCND1 0x90 /* New Data 1 Register */
153 #define CCND2 0x92 /* New Data 2 Register */
155 #define CCINTP1 0xA0 /* Interrupt Pending 1 Register */
156 #define CCINTP2 0xA2 /* Interrupt Pending 2 Register */
158 #define CCIMV1 0xB0 /* Message Valid 1 Register */
159 #define CCIMV2 0xB2 /* Message Valid 2 Register */
161 /* Control register */
164 CR_INIT = 1, // Internal Initialization Pending
165 CR_MIE = 1<<1, // Module Interrupt Enable
166 CR_SIE = 1<<2, // Status-change Interrupt Enable
167 CR_EIE = 1<<3, // Error Interrupt Enable
168 CR_DAR = 1<<5, // Disable Automatic Retransmission
169 CR_CCE = 1<<6, // Configuration Change Enable
170 CR_TEST = 1<<7 // Test Mode Enable
173 /* Status Register */
176 SR_TXOK = 1<<3, // Transmitted a Message Successfully
177 SR_RXOK = 1<<4, // Received a Message Successfully
178 SR_EPASS = 1<<5, // Error Passive
179 SR_EWARN = 1<<6, // Error Warning Status
180 SR_BOFF = 1<<7, // Bus Off Status
183 /* Status Register Last Error Codes */
184 enum c_can_BASIC_SRLEC
186 SRLEC_NE = 0, // Last Error Code: No Error
187 SRLEC_SE = 1, // LEC: Stuff Error
188 SRLEC_FE = 2, // LEC: Form Error
189 SRLEC_AE = 3, // LEC: Acknowledgement Error
190 SRLEC_B1 = 4, // LEC: Bit1 Error
191 SRLEC_B0 = 5, // LEC: Bit0 Error
192 SRLEC_CR = 6 // LEC: CRC Error
195 /* Error Counting Register */
198 EC_REP = 1<<15 // Receive Error Passive
201 /* Interrupt Register */
204 INT_NOINT = 0, // No Interrupt is pending
205 INT_STAT = 0x8000 // Status Interrupt
208 /* CAN Test Register */
211 TR_BASIC = 1<<2, // Basic Mode
212 TR_SLNT = 1<<3, // Silent Mode
213 TR_LOOPB = 1<<4, // Loop Back Mode
214 TR_RX = 1<<7 // Receive (CAN_RX Pin)
217 /* CAN Test Register TX Control*/
218 enum c_can_BASIC_TRTX
220 TRTX_RST = 0, // Reset value, CAN_TX is controlled by the CAN Core
221 TRTX_MON = 1, // Sample Point can be monitored at CAN_TX pin
222 TRTX_DOM = 2, // CAN_TX pin drives a dominant('0') value
223 TRTX_REC = 3 // CAN_TX pin drives a recessive('1') value
226 /* CAN Enable Register */
229 CE_EN = 1 // CAN Enable Bit
232 /* Interface X Command Request Register */
233 enum c_can_BASIC_IFXCR
235 IFXCR_BUSY = 1<<15 // Busy Flag (Write Access only when Busy='0')
238 /* Interface X Command Mask Register */
239 enum c_can_BASIC_IFXCM
241 IFXCM_DB = 1, // R/W Data Byte 4-7
242 IFXCM_DA = 1<<1, // R/W Data Byte 0-3
243 IFXCM_TRND = 1<<2, // Transmit Request (WRRD=1) or Reset New Date Bit (WRRD=0)
244 IFXCM_CLRINTPND = 1<<3, // Clear Interrupt Pending Bit when reading the Message Object
245 IFXCM_CNTRL = 1<<4, // Access Interface X Message Control Bits
246 IFXCM_ARB = 1<<5, // Access Interface X Arbitration
247 IFXCM_MASK = 1<<6, // Access Interface X Mask Bits
248 IFXCM_WRRD = 1<<7 // Read/Write (write data from Interface Registers to Message Object if ='1')
249 // (read data from Message Object to Interface Registers if ='0')
252 /* Interface X Mask 2 Register */
253 enum c_can_BASIC_IFXMSK2
255 IFXMSK2_MDIR = 1<<14, // Mask Message Direction (message direction bit(RTR) used for acceptance filt. or not)
256 IFXMSK2_MXTD = 1<<15 // Mask Extended Identifier (extended id bit(IDE) used for acceptance filt. or not)
259 /* Interface X Arbitration 2 Register */
260 enum c_can_BASIC_IFXARB2
262 IFXARB2_DIR = 1<<13, // Message Direction (transmit='1')
263 IFXARB2_XTD = 1<<14, // Use Extended Identifier
264 IFXARB2_MVAL = 1<<15 // Message Validation
267 /* Interface X Message Control Register */
268 enum c_can_BASIC_IFXMC
270 IFXMC_EOB = 1<<7, // End of Buffer (marks last Message Object of FIFO Buffer)
271 IFXMC_TXRQST = 1<<8, // Transmit Request
272 IFXMC_RMTEN = 1<<9, // Remote Enable
273 IFXMC_RXIE = 1<<10, // Receive Interrupt Enable
274 IFXMC_TXIE = 1<<11, // Transmit Interrupt Enable
275 IFXMC_UMASK = 1<<12, // Use Identifier Mask
276 IFXMC_INTPND = 1<<13, // Interrupt Pending
277 IFXMC_MSGLST = 1<<14, // Message Lost (Only valid for direction = receive)
278 IFXMC_NEWDAT = 1<<15 // New Data