2 * Linux CAN-bus device driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
5 * email:pisa@cmp.felk.cvut.cz
6 * This software is released under the GPL-License.
7 * Version lincan-0.3 17 Jun 2004
10 #include "../include/can.h"
11 #include "../include/can_sysdep.h"
12 #include "../include/main.h"
13 #include "../include/i82527.h"
15 void i82527_irq_rtr_handler(struct canchip_t *chip, struct msgobj_t *obj,
16 struct rtr_id *rtr_search, unsigned long message_id);
23 /* helper functions for segmented cards read and write configuration and status registers
26 void i82527_seg_write_reg(const struct canchip_t *chip, unsigned char data, unsigned address)
28 if((address > 0xf) && (chip->flags & CHIP_SEGMENTED))
29 canobj_write_reg(chip, chip->msgobj[(address>>4)-1],data, address & 0xf);
31 can_write_reg(chip, data, address);
34 unsigned i82527_seg_read_reg(const struct canchip_t *chip, unsigned address)
36 if((address > 0xf) && (chip->flags & CHIP_SEGMENTED))
37 return canobj_read_reg(chip, chip->msgobj[(address>>4)-1], address & 0xf);
39 return can_read_reg(chip, address);
42 int i82527_enable_configuration(struct canchip_t *chip)
44 unsigned short flags=0;
46 flags = can_read_reg(chip, iCTL) & (iCTL_IE|iCTL_SIE|iCTL_EIE);
47 can_write_reg(chip, flags|iCTL_CCE, iCTL);
52 int i82527_disable_configuration(struct canchip_t *chip)
54 unsigned short flags=0;
56 flags = can_read_reg(chip, iCTL) & (iCTL_IE|iCTL_SIE|iCTL_EIE);
57 can_write_reg(chip, flags, iCTL);
62 int i82527_chip_config(struct canchip_t *chip)
64 can_write_reg(chip,chip->int_cpu_reg,iCPU); // Configure cpu interface
65 can_write_reg(chip,(iCTL_CCE|iCTL_INI),iCTL); // Enable configuration
66 i82527_seg_write_reg(chip,chip->int_clk_reg,iCLK); // Set clock out slew rates
67 i82527_seg_write_reg(chip,chip->int_bus_reg,iBUS); /* Bus configuration */
68 can_write_reg(chip,0x00,iSTAT); /* Clear error status register */
70 /* Check if we can at least read back some arbitrary data from the
71 * card. If we can not, the card is not properly configured!
73 canobj_write_reg(chip,chip->msgobj[1],0x25,iMSGDAT1);
74 canobj_write_reg(chip,chip->msgobj[2],0x52,iMSGDAT3);
75 canobj_write_reg(chip,chip->msgobj[10],0xc3,iMSGDAT6);
76 if ( (canobj_read_reg(chip,chip->msgobj[1],iMSGDAT1) != 0x25) ||
77 (canobj_read_reg(chip,chip->msgobj[2],iMSGDAT3) != 0x52) ||
78 (canobj_read_reg(chip,chip->msgobj[10],iMSGDAT6) != 0xc3) ) {
79 CANMSG("Could not read back from the hardware.\n");
80 CANMSG("This probably means that your hardware is not correctly configured!\n");
84 DEBUGMSG("Could read back, hardware is probably configured correctly\n");
86 if (chip->baudrate == 0)
87 chip->baudrate=1000000;
89 if (i82527_baud_rate(chip,chip->baudrate,chip->clock,0,75,0)) {
90 CANMSG("Error configuring baud rate\n");
93 if (i82527_standard_mask(chip,0x0000,stdmask)) {
94 CANMSG("Error configuring standard mask\n");
97 if (i82527_extended_mask(chip,0x00000000,extmask)) {
98 CANMSG("Error configuring extended mask\n");
101 if (i82527_message15_mask(chip,0x00000000,mo15mask)) {
102 CANMSG("Error configuring message 15 mask\n");
105 if (i82527_clear_objects(chip)) {
106 CANMSG("Error clearing message objects\n");
109 if (i82527_config_irqs(chip,iCTL_IE|iCTL_EIE)) { /* has been 0x0a */
110 CANMSG("Error configuring interrupts\n");
117 /* Set communication parameters.
118 * param rate baud rate in Hz
119 * param clock frequency of i82527 clock in Hz (ISA osc is 14318000)
120 * param sjw synchronization jump width (0-3) prescaled clock cycles
121 * param sampl_pt sample point in % (0-100) sets (TSEG1+2)/(TSEG1+TSEG2+3) ratio
122 * param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP
124 int i82527_baud_rate(struct canchip_t *chip, int rate, int clock, int sjw,
125 int sampl_pt, int flags)
127 int best_error = 1000000000, error;
128 int best_tseg=0, best_brp=0, best_rate=0, brp=0;
129 int tseg=0, tseg1=0, tseg2=0;
131 if (i82527_enable_configuration(chip))
134 if(chip->int_cpu_reg & iCPU_DSC)
137 /* tseg even = round down, odd = round up */
138 for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++) {
139 brp = clock/((1+tseg/2)*rate)+tseg%2;
140 if (brp == 0 || brp > 64)
142 error = rate - clock/(brp*(1+tseg/2));
145 if (error <= best_error) {
149 best_rate = clock/(brp*(1+tseg/2));
152 if (best_error && (rate/best_error < 10)) {
153 CANMSG("baud rate %d is not possible with %d Hz clock\n",
155 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
156 best_rate, best_brp, best_tseg, tseg1, tseg2);
159 tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
162 if (tseg2 > MAX_TSEG2)
165 tseg1 = best_tseg-tseg2-2;
166 if (tseg1>MAX_TSEG1) {
168 tseg2 = best_tseg-tseg1-2;
171 DEBUGMSG("Setting %d bps.\n", best_rate);
172 DEBUGMSG("brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
173 best_brp, best_tseg, tseg1, tseg2,
174 (100*(best_tseg-tseg2)/(best_tseg+1)));
177 i82527_seg_write_reg(chip, sjw<<6 | best_brp, iBT0);
178 can_write_reg(chip, ((flags & BTR1_SAM) != 0)<<7 | tseg2<<4 | tseg1,
180 DEBUGMSG("Writing 0x%x to iBT0\n",(sjw<<6 | best_brp));
181 DEBUGMSG("Writing 0x%x to iBT1\n",((flags & BTR1_SAM) != 0)<<7 |
184 i82527_disable_configuration(chip);
189 int i82527_standard_mask(struct canchip_t *chip, unsigned short code, unsigned short mask)
191 unsigned char mask0, mask1;
193 mask0 = (unsigned char) (mask >> 3);
194 mask1 = (unsigned char) (mask << 5);
196 can_write_reg(chip,mask0,iSGM0);
197 can_write_reg(chip,mask1,iSGM1);
199 DEBUGMSG("Setting standard mask to 0x%lx\n",(unsigned long)mask);
204 int i82527_extended_mask(struct canchip_t *chip, unsigned long code, unsigned long mask)
206 unsigned char mask0, mask1, mask2, mask3;
208 mask0 = (unsigned char) (mask >> 21);
209 mask1 = (unsigned char) (mask >> 13);
210 mask2 = (unsigned char) (mask >> 5);
211 mask3 = (unsigned char) (mask << 3);
213 can_write_reg(chip,mask0,iEGM0);
214 can_write_reg(chip,mask1,iEGM1);
215 can_write_reg(chip,mask2,iEGM2);
216 can_write_reg(chip,mask3,iEGM3);
218 DEBUGMSG("Setting extended mask to 0x%lx\n",(unsigned long)mask);
223 int i82527_message15_mask(struct canchip_t *chip, unsigned long code, unsigned long mask)
225 unsigned char mask0, mask1, mask2, mask3;
227 mask0 = (unsigned char) (mask >> 21);
228 mask1 = (unsigned char) (mask >> 13);
229 mask2 = (unsigned char) (mask >> 5);
230 mask3 = (unsigned char) (mask << 3);
232 can_write_reg(chip,mask0,i15M0);
233 can_write_reg(chip,mask1,i15M1);
234 can_write_reg(chip,mask2,i15M2);
235 can_write_reg(chip,mask3,i15M3);
237 DEBUGMSG("Setting message 15 mask to 0x%lx\n",mask);
244 int i82527_clear_objects(struct canchip_t *chip)
247 struct msgobj_t *obj;
249 DEBUGMSG("Cleared all message objects on chip\n");
251 for (i=0; i<chip->max_objects; i++) {
253 canobj_write_reg(chip,obj,(INTPD_RES|RXIE_RES|TXIE_RES|MVAL_RES),iMSGCTL0);
254 canobj_write_reg(chip,obj,(NEWD_RES|MLST_RES|TXRQ_RES|RMPD_RES), iMSGCTL1);
255 for (data=0x07; data<0x0f; data++)
256 canobj_write_reg(chip,obj,0x00,data);
257 for (id=2; id<6; id++) {
258 canobj_write_reg(chip,obj,0x00,id);
261 canobj_write_reg(chip,obj,0x00,iMSGCFG);
264 canobj_write_reg(chip,obj,MCFG_XTD,iMSGCFG);
268 DEBUGMSG("All message ID's set to standard\n");
270 DEBUGMSG("All message ID's set to extended\n");
275 int i82527_config_irqs(struct canchip_t *chip, short irqs)
277 can_write_reg(chip,irqs,iCTL);
278 DEBUGMSG("Configured hardware interrupt delivery\n");
282 int i82527_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj)
284 unsigned long id=obj->rx_preconfig_id;
286 can_msgobj_set_fl(obj,RX_MODE);
288 if (extended || can_msgobj_test_fl(obj,RX_MODE_EXT)) {
290 canobj_write_reg(chip,obj,id,iMSGID3);
291 canobj_write_reg(chip,obj,id>>8,iMSGID2);
292 canobj_write_reg(chip,obj,id>>16,iMSGID1);
293 canobj_write_reg(chip,obj,id>>24,iMSGID0);
294 canobj_write_reg(chip,obj,MCFG_XTD,iMSGCFG);
297 canobj_write_reg(chip,obj,id,iMSGID1);
298 canobj_write_reg(chip,obj,id>>8,iMSGID0);
299 canobj_write_reg(chip,obj,0x00,iMSGCFG);
302 canobj_write_reg(chip,obj,(NEWD_RES|MLST_RES|TXRQ_RES|RMPD_RES), iMSGCTL1);
303 canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
305 DEBUGMSG("i82527_pre_read_config: configured obj at 0x%08lx\n",obj->obj_base_addr);
310 int i82527_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
311 struct canmsg_t *msg)
313 int i=0,id0=0,id1=0,id2=0,id3=0;
317 if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
319 can_msgobj_clear_fl(obj,RX_MODE);
321 canobj_write_reg(chip,obj,(MVAL_SET|TXIE_SET|RXIE_RES|INTPD_RES),iMSGCTL0);
322 canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|CPUU_SET|NEWD_RES),iMSGCTL1);
324 if (extended || (msg->flags&MSG_EXT)) {
325 canobj_write_reg(chip,obj,(len<<4)|(MCFG_DIR|MCFG_XTD),iMSGCFG);
326 id0 = (unsigned char) (msg->id<<3);
327 id1 = (unsigned char) (msg->id>>5);
328 id2 = (unsigned char) (msg->id>>13);
329 id3 = (unsigned char) (msg->id>>21);
330 canobj_write_reg(chip,obj,id0,iMSGID3);
331 canobj_write_reg(chip,obj,id1,iMSGID2);
332 canobj_write_reg(chip,obj,id2,iMSGID1);
333 canobj_write_reg(chip,obj,id3,iMSGID0);
336 canobj_write_reg(chip,obj,(len<<4)|MCFG_DIR,iMSGCFG);
337 id1 = (unsigned char) (msg->id<<5);
338 id0 = (unsigned char) (msg->id>>3);
339 canobj_write_reg(chip,obj,id1,iMSGID1);
340 canobj_write_reg(chip,obj,id0,iMSGID0);
342 canobj_write_reg(chip,obj,RMPD_UNC|TXRQ_UNC|CPUU_SET|NEWD_SET,iMSGCTL1);
343 for (i=0; i<len; i++) {
344 canobj_write_reg(chip,obj,msg->data[i],iMSGDAT0+i);
350 int i82527_send_msg(struct canchip_t *chip, struct msgobj_t *obj,
351 struct canmsg_t *msg)
353 canobj_write_reg(chip,obj,(MVAL_SET|TXIE_SET|RXIE_RES|INTPD_RES),iMSGCTL0);
355 if (msg->flags & MSG_RTR) {
356 canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|CPUU_RES|NEWD_SET),iMSGCTL1);
359 canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_SET|CPUU_RES|NEWD_SET),iMSGCTL1);
365 int i82527_check_tx_stat(struct canchip_t *chip)
367 if (can_read_reg(chip,iSTAT) & iSTAT_TXOK) {
368 can_write_reg(chip,0x0,iSTAT);
372 can_write_reg(chip,0x0,iSTAT);
377 int i82527_remote_request(struct canchip_t *chip, struct msgobj_t *obj)
379 canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
380 canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_SET|MLST_RES|NEWD_RES),iMSGCTL1);
385 int i82527_set_btregs(struct canchip_t *chip, unsigned short btr0,
388 if (i82527_enable_configuration(chip))
391 i82527_seg_write_reg(chip, btr0, iBT0);
392 i82527_seg_write_reg(chip, btr1, iBT1);
394 i82527_disable_configuration(chip);
399 int i82527_start_chip(struct canchip_t *chip)
401 unsigned short flags = 0;
403 flags = can_read_reg(chip, iCTL) & (iCTL_IE|iCTL_SIE|iCTL_EIE);
404 can_write_reg(chip, flags, iCTL);
409 int i82527_stop_chip(struct canchip_t *chip)
411 unsigned short flags = 0;
413 flags = can_read_reg(chip, iCTL) & (iCTL_IE|iCTL_SIE|iCTL_EIE);
414 can_write_reg(chip, flags|(iCTL_CCE|iCTL_INI), iCTL);
419 int i82527_attach_to_chip(struct canchip_t *chip)
424 int i82527_release_chip(struct canchip_t *chip)
426 i82527_stop_chip(chip);
427 can_write_reg(chip, (iCTL_CCE|iCTL_INI), iCTL);
433 void i82527_irq_write_handler(struct canchip_t *chip, struct msgobj_t *obj)
437 canobj_write_reg(chip,obj,(MVAL_RES|TXIE_RES|RXIE_RES|INTPD_RES),iMSGCTL0);
440 /* Do local transmitted message distribution if enabled */
442 /* fill CAN message timestamp */
443 can_filltimestamp(&obj->tx_slot->msg.timestamp);
445 obj->tx_slot->msg.flags |= MSG_LOCAL;
446 canque_filter_msg2edges(obj->qends, &obj->tx_slot->msg);
448 /* Free transmitted slot */
449 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
453 cmd=canque_test_outslot(obj->qends, &obj->tx_qedge, &obj->tx_slot);
457 if (chip->chipspecops->pre_write_config(chip, obj, &obj->tx_slot->msg)) {
459 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_PREP);
460 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
464 if (chip->chipspecops->send_msg(chip, obj, &obj->tx_slot->msg)) {
466 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_SEND);
467 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
475 void i82527_irq_read_handler(struct canchip_t *chip, struct msgobj_t *obj, int objnum)
478 unsigned long message_id;
481 msgctl1=canobj_read_reg(chip,obj,iMSGCTL1);
482 if(msgctl1 & NEWD_RES)
487 canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|MLST_UNC|NEWD_RES),iMSGCTL1);
488 canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
491 msgcfg = canobj_read_reg(chip,obj,iMSGCFG);
493 if (msgcfg&MCFG_XTD) {
494 message_id =canobj_read_reg(chip,obj,iMSGID3);
495 message_id|=canobj_read_reg(chip,obj,iMSGID2)<<8;
496 message_id|=canobj_read_reg(chip,obj,iMSGID1)<<16;
497 message_id|=canobj_read_reg(chip,obj,iMSGID0)<<24;
499 obj->rx_msg.flags = MSG_EXT;
503 message_id =canobj_read_reg(chip,obj,iMSGID1);
504 message_id|=canobj_read_reg(chip,obj,iMSGID0)<<8;
506 obj->rx_msg.flags = 0;
509 obj->rx_msg.length = (msgcfg >> 4) & 0xf;
510 if(obj->rx_msg.length > CAN_MSG_LENGTH) obj->rx_msg.length = CAN_MSG_LENGTH;
512 obj->rx_msg.id = message_id;
514 for (i=0; i < obj->rx_msg.length; i++)
515 obj->rx_msg.data[i] = canobj_read_reg(chip,obj,iMSGDAT0+i);
519 /* if NEWD is set after data read, then read data are likely inconsistent */
520 msgctl1=canobj_read_reg(chip,obj,iMSGCTL1);
521 if(msgctl1 & NEWD_SET) {
522 CANMSG("i82527_irq_read_handler: object %d data overwritten\n",objnum);
527 /* this object is special and data are queued in the shadow register */
528 canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
529 canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|MLST_UNC|NEWD_RES),iMSGCTL1);
530 msgctl1=canobj_read_reg(chip,obj,iMSGCTL1);
534 /* fill CAN message timestamp */
535 can_filltimestamp(&obj->rx_msg.timestamp);
537 canque_filter_msg2edges(obj->qends, &obj->rx_msg);
539 if (msgctl1 & NEWD_SET)
542 if (msgctl1 & MLST_SET) {
543 canobj_write_reg(chip,obj,(RMPD_UNC|TXRQ_UNC|MLST_RES|NEWD_UNC),iMSGCTL1);
544 CANMSG("i82527_irq_read_handler: object %d message lost\n",objnum);
553 if (msgcfg&MCFG_XTD) {
554 message_id =canobj_read_reg(chip,obj,iMSGID3);
555 message_id|=canobj_read_reg(chip,obj,iMSGID2)<<8;
556 message_id|=canobj_read_reg(chip,obj,iMSGID1)<<16;
557 message_id|=canobj_read_reg(chip,obj,iMSGID0)<<24;
561 message_id =canobj_read_reg(chip,obj,iMSGID1);
562 message_id|=canobj_read_reg(chip,obj,iMSGID0)<<8;
566 can_spin_lock(&hardware_p->rtr_lock);
567 rtr_search=hardware_p->rtr_queue;
568 while (rtr_search != NULL) {
569 if (rtr_search->id == message_id)
571 rtr_search=rtr_search->next;
573 can_spin_unlock(&hardware_p->rtr_lock);
574 if ((rtr_search!=NULL) && (rtr_search->id==message_id))
575 i82527_irq_rtr_handler(chip, obj, rtr_search, message_id);
577 i82527_irq_read_handler(chip, obj, message_id);
582 void i82527_irq_update_filter(struct canchip_t *chip, struct msgobj_t *obj)
584 struct canfilt_t filt;
586 if(canqueue_ends_filt_conjuction(obj->qends, &filt)) {
587 obj->rx_preconfig_id=filt.id;
588 canobj_write_reg(chip,obj,(MVAL_RES|TXIE_RES|RXIE_RES|INTPD_RES),iMSGCTL0);
589 if(obj->object == 15) {
590 i82527_message15_mask(chip,filt.id,filt.mask);
592 if (filt.flags&MSG_EXT)
593 can_msgobj_set_fl(obj,RX_MODE_EXT);
595 can_msgobj_clear_fl(obj,RX_MODE_EXT);
597 i82527_pre_read_config(chip, obj);
599 CANMSG("i82527_irq_update_filter: obj at 0x%08lx\n",obj->obj_base_addr);
604 int i82527_irq_sync_activities(struct canchip_t *chip, struct msgobj_t *obj)
608 while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)) {
610 if(can_msgobj_test_and_clear_fl(obj,TX_REQUEST)) {
611 if(canobj_read_reg(chip,obj,iMSGCTL1)&TXRQ_RES)
612 i82527_irq_write_handler(chip, obj);
616 if(can_msgobj_test_and_clear_fl(obj,FILTCH_REQUEST)) {
617 i82527_irq_update_filter(chip, obj);
625 can_msgobj_clear_fl(obj,TX_LOCK);
626 if(can_msgobj_test_fl(obj,TX_REQUEST))
628 if(can_msgobj_test_fl(obj,FILTCH_REQUEST) && !obj->tx_slot)
636 int i82527_irq_handler(int irq, struct canchip_t *chip)
638 unsigned char msgcfg;
640 unsigned irq_register;
641 unsigned status_register;
643 struct msgobj_t *obj;
644 int loop_cnt=CHIP_MAX_IRQLOOP;
646 /*put_reg=device->hwspecops->write_register;*/
647 /*get_reg=device->hwspecops->read_register;*/
649 irq_register = i82527_seg_read_reg(chip, iIRQ);
652 DEBUGMSG("i82527: spurious IRQ\n");
653 return CANCHIP_IRQ_NONE;
660 CANMSG("i82527_irq_handler IRQ %d stuck\n",irq);
661 CANMSG("i82527_irq_register 0x%x\n",irq_register);
662 return CANCHIP_IRQ_STUCK;
665 DEBUGMSG("i82527: iIRQ 0x%02x\n",irq_register);
667 if (irq_register == 0x01) {
668 status_register=can_read_reg(chip, iSTAT);
669 CANMSG("Status register: 0x%x\n",status_register);
671 /*return CANCHIP_IRQ_NONE;*/
674 if (irq_register == 0x02)
676 else if(irq_register <= 13+3)
677 object = irq_register-3;
679 return CANCHIP_IRQ_NONE;
681 obj=chip->msgobj[object];
683 msgcfg = canobj_read_reg(chip,obj,iMSGCFG);
684 if (msgcfg & MCFG_DIR) {
685 can_msgobj_set_fl(obj,TX_REQUEST);
687 /* calls i82527_irq_write_handler synchronized with other invocations */
688 if(i82527_irq_sync_activities(chip, obj)<=0){
689 /* The interrupt has to be cleared anyway */
690 canobj_write_reg(chip,obj,(MVAL_UNC|TXIE_UNC|RXIE_UNC|INTPD_RES),iMSGCTL0);
693 * Rerun for case, that parallel activity on SMP or fully-preemptive
694 * kernel result in preparation and finished sending of message
695 * between above if and canobj_write_reg.
697 i82527_irq_sync_activities(chip, obj);
702 i82527_irq_read_handler(chip, obj, object);
705 } while((irq_register=i82527_seg_read_reg(chip, iIRQ)) != 0);
707 return CANCHIP_IRQ_HANDLED;
710 void i82527_irq_rtr_handler(struct canchip_t *chip, struct msgobj_t *obj,
711 struct rtr_id *rtr_search, unsigned long message_id)
715 canobj_write_reg(chip,obj,(MVAL_RES|TXIE_RES|RXIE_RES|INTPD_RES),iMSGCTL0);
716 canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|MLST_RES|NEWD_RES),iMSGCTL1);
718 can_spin_lock(&hardware_p->rtr_lock);
720 rtr_search->rtr_message->id=message_id;
721 rtr_search->rtr_message->length=(canobj_read_reg(chip,obj,iMSGCFG) & 0xf0)>>4;
722 for (i=0; i<rtr_search->rtr_message->length; i++)
723 rtr_search->rtr_message->data[i]=canobj_read_reg(chip,obj,iMSGDAT0+i);
725 can_spin_unlock(&hardware_p->rtr_lock);
727 if (waitqueue_active(&rtr_search->rtr_wq))
728 wake_up(&rtr_search->rtr_wq);
732 * i82527_wakeup_tx: - wakeups TX processing
733 * @chip: pointer to chip state structure
734 * @obj: pointer to message object structure
736 * Function is responsible for initiating message transmition.
737 * It is responsible for clearing of object TX_REQUEST flag
739 * Return Value: negative value reports error.
742 int i82527_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj)
744 can_preempt_disable();
746 can_msgobj_set_fl(obj,TX_REQUEST);
748 /* calls i82527_irq_write_handler synchronized with other invocations
749 from kernel and IRQ context */
750 i82527_irq_sync_activities(chip, obj);
752 can_preempt_enable();
756 int i82527_filtch_rq(struct canchip_t *chip, struct msgobj_t *obj)
758 can_preempt_disable();
760 can_msgobj_set_fl(obj,FILTCH_REQUEST);
762 /* setups filter synchronized with other invocations from kernel and IRQ context */
763 i82527_irq_sync_activities(chip, obj);
765 can_preempt_enable();
769 int i82527_register(struct chipspecops_t *chipspecops)
771 chipspecops->chip_config = i82527_chip_config;
772 chipspecops->baud_rate = i82527_baud_rate;
773 chipspecops->standard_mask = i82527_standard_mask;
774 chipspecops->extended_mask = i82527_extended_mask;
775 chipspecops->message15_mask = i82527_message15_mask;
776 chipspecops->clear_objects = i82527_clear_objects;
777 chipspecops->config_irqs = i82527_config_irqs;
778 chipspecops->pre_read_config = i82527_pre_read_config;
779 chipspecops->pre_write_config = i82527_pre_write_config;
780 chipspecops->send_msg = i82527_send_msg;
781 chipspecops->check_tx_stat = i82527_check_tx_stat;
782 chipspecops->wakeup_tx = i82527_wakeup_tx;
783 chipspecops->filtch_rq = i82527_filtch_rq;
784 chipspecops->remote_request = i82527_remote_request;
785 chipspecops->enable_configuration = i82527_enable_configuration;
786 chipspecops->disable_configuration = i82527_disable_configuration;
787 chipspecops->set_btregs = i82527_set_btregs;
788 chipspecops->attach_to_chip = i82527_attach_to_chip;
789 chipspecops->release_chip = i82527_release_chip;
790 chipspecops->start_chip = i82527_start_chip;
791 chipspecops->stop_chip = i82527_stop_chip;
792 chipspecops->irq_handler = i82527_irq_handler;
793 chipspecops->irq_accept = NULL;
797 int i82527_fill_chipspecops(struct canchip_t *chip)
799 chip->chip_type="i82527";
800 chip->max_objects=15;
801 i82527_register(chip->chipspecops);