1 /**************************************************************************/
2 /* File: i82527.h - Intel i82527 CAN controller support */
4 /* LinCAN - (Not only) Linux CAN bus driver */
5 /* Copyright (C) 2002-2009 DCE FEE CTU Prague <http://dce.felk.cvut.cz> */
6 /* Copyright (C) 2002-2009 Pavel Pisa <pisa@cmp.felk.cvut.cz> */
7 /* Funded by OCERA and FRESCOR IST projects */
8 /* Based on CAN driver code by Arnaud Westenberg <arnaud@wanadoo.nl> */
10 /* LinCAN is free software; you can redistribute it and/or modify it */
11 /* under terms of the GNU General Public License as published by the */
12 /* Free Software Foundation; either version 2, or (at your option) any */
13 /* later version. LinCAN is distributed in the hope that it will be */
14 /* useful, but WITHOUT ANY WARRANTY; without even the implied warranty */
15 /* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */
16 /* General Public License for more details. You should have received a */
17 /* copy of the GNU General Public License along with LinCAN; see file */
18 /* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, */
19 /* Cambridge, MA 02139, USA. */
21 /* To allow use of LinCAN in the compact embedded systems firmware */
22 /* and RT-executives (RTEMS for example), main authors agree with next */
23 /* special exception: */
25 /* Including LinCAN header files in a file, instantiating LinCAN generics */
26 /* or templates, or linking other files with LinCAN objects to produce */
27 /* an application image/executable, does not by itself cause the */
28 /* resulting application image/executable to be covered by */
29 /* the GNU General Public License. */
30 /* This exception does not however invalidate any other reasons */
31 /* why the executable file might be covered by the GNU Public License. */
32 /* Publication of enhanced or derived LinCAN files is required although. */
33 /**************************************************************************/
35 int i82527_enable_configuration(struct canchip_t *chip);
36 int i82527_disable_configuration(struct canchip_t *chip);
37 int i82527_chip_config(struct canchip_t *chip);
38 int i82527_baud_rate(struct canchip_t *chip, int rate, int clock, int sjw,
39 int sampl_pt, int flags);
40 int i82527_standard_mask(struct canchip_t *chip, unsigned short code,
42 int i82527_extended_mask(struct canchip_t *chip, unsigned long code,
44 int i82527_message15_mask(struct canchip_t *chip, unsigned long code,
46 int i82527_clear_objects(struct canchip_t *chip);
47 int i82527_config_irqs(struct canchip_t *chip, short irqs);
48 int i82527_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj);
49 int i82527_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
50 struct canmsg_t *msg);
51 int i82527_send_msg(struct canchip_t *chip, struct msgobj_t *obj,
52 struct canmsg_t *msg);
53 int i82527_remote_request(struct canchip_t *chip, struct msgobj_t *obj);
54 int i82527_set_btregs(struct canchip_t *chip, unsigned short btr0,
56 int i82527_start_chip(struct canchip_t *chip);
57 int i82527_stop_chip(struct canchip_t *chip);
58 int i82527_check_tx_stat(struct canchip_t *chip);
59 int i82527_irq_handler(int irq, struct canchip_t *chip);
60 int i82527_fill_chipspecops(struct canchip_t *chip);
63 #define MSG_OFFSET(object) ((object)*0x10)
65 #define iCTL 0x00 // Control Register
66 #define iSTAT 0x01 // Status Register
67 #define iCPU 0x02 // CPU Interface Register
68 #define iHSR 0x04 // High Speed Read
69 #define iSGM0 0x06 // Standard Global Mask byte 0
71 #define iEGM0 0x08 // Extended Global Mask byte 0
75 #define i15M0 0x0c // Message 15 Mask byte 0
79 #define iCLK 0x1f // Clock Out Register
80 #define iBUS 0x2f // Bus Configuration Register
81 #define iBT0 0x3f // Bit Timing Register byte 0
83 #define iIRQ 0x5f // Interrupt Register
84 #define iP1C 0x9f // Port 1 Register
85 #define iP2C 0xaf // Port 2 Register
86 #define iP1I 0xbf // Port 1 Data In Register
87 #define iP2I 0xcf // Port 2 Data In Register
88 #define iP1O 0xdf // Port 1 Data Out Register
89 #define iP2O 0xef // Port 2 Data Out Register
90 #define iSRA 0xff // Serial Reset Address
92 #define iMSGCTL0 0x00 /* First Control register */
93 #define iMSGCTL1 0x01 /* Second Control register */
94 #define iMSGID0 0x02 /* First Byte of Message ID */
98 #define iMSGCFG 0x06 /* Message Configuration */
99 #define iMSGDAT0 0x07 /* First Data Byte */
100 #define iMSGDAT1 0x08
101 #define iMSGDAT2 0x09
102 #define iMSGDAT3 0x0a
103 #define iMSGDAT4 0x0b
104 #define iMSGDAT5 0x0c
105 #define iMSGDAT6 0x0d
106 #define iMSGDAT7 0x0e
108 /* Control Register (0x00) */
110 iCTL_INI = 1, // Initialization
111 iCTL_IE = 1<<1, // Interrupt Enable
112 iCTL_SIE = 1<<2, // Status Interrupt Enable
113 iCTL_EIE = 1<<3, // Error Interrupt Enable
114 iCTL_CCE = 1<<6 // Change Configuration Enable
117 /* Status Register (0x01) */
119 iSTAT_TXOK = 1<<3, // Transmit Message Successfully
120 iSTAT_RXOK = 1<<4, // Receive Message Successfully
121 iSTAT_WAKE = 1<<5, // Wake Up Status
122 iSTAT_WARN = 1<<6, // Warning Status
123 iSTAT_BOFF = 1<<7 // Bus Off Status
126 /* CPU Interface Register (0x02) */
128 iCPU_CEN = 1, // Clock Out Enable
129 iCPU_MUX = 1<<2, // Multiplex
130 iCPU_SLP = 1<<3, // Sleep
131 iCPU_PWD = 1<<4, // Power Down Mode
132 iCPU_DMC = 1<<5, // Divide Memory Clock
133 iCPU_DSC = 1<<6, // Divide System Clock
134 iCPU_RST = 1<<7 // Hardware Reset Status
137 /* Clock Out Register (0x1f) */
139 iCLK_CD0 = 1, // Clock Divider bit 0
143 iCLK_SL0 = 1<<4, // Slew Rate bit 0
147 /* Bus Configuration Register (0x2f) */
149 iBUS_DR0 = 1, // Disconnect RX0 Input
150 iBUS_DR1 = 1<<1, // Disconnect RX1 Input
151 iBUS_DT1 = 1<<3, // Disconnect TX1 Output
152 iBUS_POL = 1<<5, // Polarity
153 iBUS_CBY = 1<<6 // Comparator Bypass
156 #define RESET 1 // Bit Pair Reset Status
157 #define SET 2 // Bit Pair Set Status
158 #define UNCHANGED 3 // Bit Pair Unchanged
160 /* Message Control Register 0 (Base Address + 0x0) */
161 enum i82527_iMSGCTL0 {
162 INTPD_SET = SET, // Interrupt pending
163 INTPD_RES = RESET, // No Interrupt pending
164 INTPD_UNC = UNCHANGED,
165 RXIE_SET = SET<<2, // Receive Interrupt Enable
166 RXIE_RES = RESET<<2, // Receive Interrupt Disable
167 RXIE_UNC = UNCHANGED<<2,
168 TXIE_SET = SET<<4, // Transmit Interrupt Enable
169 TXIE_RES = RESET<<4, // Transmit Interrupt Disable
170 TXIE_UNC = UNCHANGED<<4,
171 MVAL_SET = SET<<6, // Message Valid
172 MVAL_RES = RESET<<6, // Message Invalid
173 MVAL_UNC = UNCHANGED<<6
176 /* Message Control Register 1 (Base Address + 0x01) */
177 enum i82527_iMSGCTL1 {
178 NEWD_SET = SET, // New Data
179 NEWD_RES = RESET, // No New Data
180 NEWD_UNC = UNCHANGED,
181 MLST_SET = SET<<2, // Message Lost
182 MLST_RES = RESET<<2, // No Message Lost
183 MLST_UNC = UNCHANGED<<2,
184 CPUU_SET = SET<<2, // CPU Updating
185 CPUU_RES = RESET<<2, // No CPU Updating
186 CPUU_UNC = UNCHANGED<<2,
187 TXRQ_SET = SET<<4, // Transmission Request
188 TXRQ_RES = RESET<<4, // No Transmission Request
189 TXRQ_UNC = UNCHANGED<<4,
190 RMPD_SET = SET<<6, // Remote Request Pending
191 RMPD_RES = RESET<<6, // No Remote Request Pending
192 RMPD_UNC = UNCHANGED<<6
195 /* Message Configuration Register (Base Address + 0x06) */
196 enum i82527_iMSGCFG {
197 MCFG_XTD = 1<<2, // Extended Identifier
198 MCFG_DIR = 1<<3 // Direction is Transmit
201 void i82527_seg_write_reg(const struct canchip_t *chip, unsigned char data, unsigned address);
202 unsigned i82527_seg_read_reg(const struct canchip_t *chip, unsigned address);