2 * Linux CAN-bus device driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
5 * email:pisa@cmp.felk.cvut.cz
6 * This software is released under the GPL-License.
7 * Version lincan-0.2 9 Jul 2003
10 #include "../include/can.h"
11 #include "../include/can_sysdep.h"
12 #include "../include/main.h"
13 #include "../include/sja1000.h"
15 void sja1000_irq_read_handler(struct chip_t *chip, struct msgobj_t *obj);
16 void sja1000_irq_write_handler(struct chip_t *chip, struct msgobj_t *obj);
18 int sja1000_enable_configuration(struct chip_t *chip)
23 can_disable_irq(chip->chip_irq);
25 flags=can_read_reg(chip,SJACR);
27 while ((!(flags & CR_RR)) && (i<=10)) {
28 can_write_reg(chip,flags|CR_RR,SJACR);
31 flags=can_read_reg(chip,SJACR);
34 CANMSG("Reset error\n");
35 can_enable_irq(chip->chip_irq);
42 int sja1000_disable_configuration(struct chip_t *chip)
47 flags=can_read_reg(chip,SJACR);
49 while ( (flags & CR_RR) && (i<=10) ) {
50 can_write_reg(chip,flags & (CR_RIE|CR_TIE|CR_EIE|CR_OIE),SJACR);
53 flags=can_read_reg(chip,SJACR);
56 CANMSG("Error leaving reset status\n");
60 can_enable_irq(chip->chip_irq);
65 int sja1000_chip_config(struct chip_t *chip)
67 if (sja1000_enable_configuration(chip))
70 /* Set mode, clock out, comparator */
71 can_write_reg(chip,chip->sja_cdr_reg,SJACDR);
72 /* Set driver output configuration */
73 can_write_reg(chip,chip->sja_ocr_reg,SJAOCR);
75 if (sja1000_standard_mask(chip,0x0000, 0xffff))
79 chip->baudrate=1000000;
80 if (sja1000_baud_rate(chip,chip->baudrate,chip->clock,0,75,0))
83 /* Enable hardware interrupts */
84 can_write_reg(chip,(CR_RIE|CR_TIE|CR_EIE|CR_OIE),SJACR);
86 sja1000_disable_configuration(chip);
91 int sja1000_standard_mask(struct chip_t *chip, unsigned short code, unsigned short mask)
93 unsigned char write_code, write_mask;
95 if (sja1000_enable_configuration(chip))
98 /* The acceptance code bits (SJAACR bits 0-7) and the eight most
99 * significant bits of the message identifier (id.10 to id.3) must be
100 * equal to those bit positions which are marked relevant by the
101 * acceptance mask bits (SJAAMR bits 0-7).
102 * (id.10 to id.3) = (SJAACR.7 to SJAACR.0) v (SJAAMR.7 to SJAAMR.0)
103 * (Taken from Philips sja1000 Data Sheet)
105 write_code = (unsigned char) code >> 3;
106 write_mask = (unsigned char) mask >> 3;
108 can_write_reg(chip,write_code,SJAACR);
109 can_write_reg(chip,write_mask,SJAAMR);
111 DEBUGMSG("Setting acceptance code to 0x%lx\n",(unsigned long)code);
112 DEBUGMSG("Setting acceptance mask to 0x%lx\n",(unsigned long)mask);
114 sja1000_disable_configuration(chip);
119 /* Set communication parameters.
120 * param rate baud rate in Hz
121 * param clock frequency of sja1000 clock in Hz (ISA osc is 14318000)
122 * param sjw synchronization jump width (0-3) prescaled clock cycles
123 * param sampl_pt sample point in % (0-100) sets (TSEG1+2)/(TSEG1+TSEG2+3) ratio
124 * param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP
126 int sja1000_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,
127 int sampl_pt, int flags)
129 int best_error = 1000000000, error;
130 int best_tseg=0, best_brp=0, best_rate=0, brp=0;
131 int tseg=0, tseg1=0, tseg2=0;
133 if (sja1000_enable_configuration(chip))
138 /* tseg even = round down, odd = round up */
139 for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++) {
140 brp = clock/((1+tseg/2)*rate)+tseg%2;
141 if (brp == 0 || brp > 64)
143 error = rate - clock/(brp*(1+tseg/2));
146 if (error <= best_error) {
150 best_rate = clock/(brp*(1+tseg/2));
153 if (best_error && (rate/best_error < 10)) {
154 CANMSG("baud rate %d is not possible with %d Hz clock\n",
156 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
157 best_rate, best_brp, best_tseg, tseg1, tseg2);
160 tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
163 if (tseg2 > MAX_TSEG2)
165 tseg1 = best_tseg-tseg2-2;
166 if (tseg1 > MAX_TSEG1) {
168 tseg2 = best_tseg-tseg1-2;
171 DEBUGMSG("Setting %d bps.\n", best_rate);
172 DEBUGMSG("brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
173 best_brp, best_tseg, tseg1, tseg2,
174 (100*(best_tseg-tseg2)/(best_tseg+1)));
177 can_write_reg(chip, sjw<<6 | best_brp, SJABTR0);
178 can_write_reg(chip, ((flags & BTR1_SAM) != 0)<<7 | tseg2<<4 | tseg1,
180 // can_write_reg(chip, OCR_MODE_NORMAL | OCR_TX0_LH | OCR_TX1_ZZ, SJAOCR);
181 /* BASIC mode, bypass input comparator */
182 // can_write_reg(chip, CDR_CBP| /* CDR_CLK_OFF | */ 7, SJACDR);
184 sja1000_disable_configuration(chip);
189 int sja1000_pre_read_config(struct chip_t *chip, struct msgobj_t *obj)
193 i=can_read_reg(chip,SJASR);
197 for (i=0; i<0x20; i++)
198 CANMSG("0x%x is 0x%x\n",i,can_read_reg(chip,i));
201 sja1000_start_chip(chip);
203 // disable interrupts for a moment
204 can_write_reg(chip, 0, SJACR);
206 sja1000_irq_read_handler(chip, obj);
209 can_write_reg(chip, CR_OIE | CR_EIE | CR_TIE | CR_RIE, SJACR);
215 #define MAX_TRANSMIT_WAIT_LOOPS 10
217 int sja1000_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
218 struct canmsg_t *msg)
223 sja1000_start_chip(chip); //sja1000 goes automatically into reset mode on errors
225 /* Wait until Transmit Buffer Status is released */
226 while ( !(can_read_reg(chip, SJASR) & SR_TBS) &&
227 i++<MAX_TRANSMIT_WAIT_LOOPS) {
231 if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
232 CANMSG("Transmit timed out, cancelling\n");
233 can_write_reg(chip, CMR_AT, SJACMR);
235 while ( !(can_read_reg(chip, SJASR) & SR_TBS) &&
236 i++<MAX_TRANSMIT_WAIT_LOOPS) {
239 if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
240 CANMSG("Could not cancel, please reset\n");
246 if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
247 id = (msg->id<<5) | ((msg->flags&MSG_RTR)?ID0_RTR:0) | len;
249 can_write_reg(chip, id>>8, SJATXID1);
250 can_write_reg(chip, id & 0xff , SJATXID0);
252 for (i=0; i<len; i++)
253 can_write_reg(chip, msg->data[i], SJATXDAT0+i);
258 int sja1000_send_msg(struct chip_t *chip, struct msgobj_t *obj,
259 struct canmsg_t *msg)
261 can_write_reg(chip, CMR_TR, SJACMR);
266 int sja1000_check_tx_stat(struct chip_t *chip)
268 if (can_read_reg(chip,SJASR) & SR_TCS)
274 int sja1000_set_btregs(struct chip_t *chip, unsigned short btr0,
277 if (sja1000_enable_configuration(chip))
280 can_write_reg(chip, btr0, SJABTR0);
281 can_write_reg(chip, btr1, SJABTR1);
283 sja1000_disable_configuration(chip);
288 int sja1000_start_chip(struct chip_t *chip)
290 unsigned short flags = 0;
292 flags = can_read_reg(chip, SJACR) & (CR_RIE|CR_TIE|CR_EIE|CR_OIE);
293 can_write_reg(chip, flags, SJACR);
298 int sja1000_stop_chip(struct chip_t *chip)
300 unsigned short flags = 0;
302 flags = can_read_reg(chip, SJACR) & (CR_RIE|CR_TIE|CR_EIE|CR_OIE);
303 can_write_reg(chip, flags|CR_RR, SJACR);
308 int sja1000_remote_request(struct chip_t *chip, struct msgobj_t *obj)
310 CANMSG("sja1000_remote_request not implemented\n");
314 int sja1000_extended_mask(struct chip_t *chip, unsigned long code,
317 CANMSG("sja1000_extended_mask not implemented\n");
321 int sja1000_clear_objects(struct chip_t *chip)
323 CANMSG("sja1000_clear_objects not implemented\n");
327 int sja1000_config_irqs(struct chip_t *chip, short irqs)
329 CANMSG("sja1000_config_irqs not implemented\n");
334 can_irqreturn_t sja1000_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
336 unsigned irq_register;
337 struct chip_t *chip=(struct chip_t *)dev_id;
338 struct msgobj_t *obj=chip->msgobj[0];
340 irq_register=can_read_reg(chip, SJAIR);
341 // DEBUGMSG("sja1000_irq_handler: SJAIR:%02x\n",irq_register);
342 // DEBUGMSG("sja1000_irq_handler: SJASR:%02x\n",
343 // can_read_reg(chip, SJASR));
345 if ((irq_register & (IR_WUI|IR_DOI|IR_EI|IR_TI|IR_RI)) == 0)
348 if ((irq_register & IR_RI) != 0)
349 sja1000_irq_read_handler(chip, obj);
351 if ((irq_register & IR_TI) != 0) {
352 can_msgobj_set_fl(obj,TX_REQUEST);
353 while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
354 can_msgobj_clear_fl(obj,TX_REQUEST);
356 if (can_read_reg(chip, SJASR) & SR_TBS)
357 sja1000_irq_write_handler(chip, obj);
359 can_msgobj_clear_fl(obj,TX_LOCK);
360 if(!can_msgobj_test_fl(obj,TX_REQUEST)) break;
364 if ((irq_register & (IR_EI|IR_DOI)) != 0) {
365 // Some error happened
366 // FIXME: chip should be brought to usable state. Transmission cancelled if in progress.
367 // Reset flag set to 0 if chip is already off the bus. Full state report
368 CANMSG("Error: status register: 0x%x irq_register: 0x%02x\n",
369 can_read_reg(chip, SJASR), irq_register);
373 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_BUS);
374 /*canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
379 return CAN_IRQ_HANDLED;
382 void sja1000_irq_read_handler(struct chip_t *chip, struct msgobj_t *obj)
387 id = can_read_reg(chip, SJARXID0) | (can_read_reg(chip, SJARXID1)<<8);
388 obj->rx_msg.length = len = id & 0x0f;
389 obj->rx_msg.flags = id&ID0_RTR ? MSG_RTR : 0;
390 obj->rx_msg.timestamp = 0;
392 obj->rx_msg.id = id>>5;
394 if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
395 for (i=0; i<len; i++)
396 obj->rx_msg.data[i]=can_read_reg(chip, SJARXDAT0 + i);
398 can_write_reg(chip, CMR_RRB, SJACMR);
400 canque_filter_msg2edges(obj->qends, &obj->rx_msg);
401 } while(can_read_reg(chip, SJASR) & SR_RBS);
404 void sja1000_irq_write_handler(struct chip_t *chip, struct msgobj_t *obj)
409 /* Do local transmitted message distribution if enabled */
411 obj->tx_slot->msg.flags |= MSG_LOCAL;
412 canque_filter_msg2edges(obj->qends, &obj->tx_slot->msg);
414 /* Free transmitted slot */
415 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
419 cmd=canque_test_outslot(obj->qends, &obj->tx_qedge, &obj->tx_slot);
423 if (chip->chipspecops->pre_write_config(chip, obj, &obj->tx_slot->msg)) {
425 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_PREP);
426 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
430 if (chip->chipspecops->send_msg(chip, obj, &obj->tx_slot->msg)) {
432 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_SEND);
433 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
440 * sja1000_wakeup_tx: - wakeups TX processing
441 * @chip: pointer to chip state structure
442 * @obj: pointer to message object structure
444 * Return Value: negative value reports error.
445 * File: src/sja1000.c
447 int sja1000_wakeup_tx(struct chip_t *chip, struct msgobj_t *obj)
449 can_preempt_disable();
451 can_msgobj_set_fl(obj,TX_REQUEST);
452 while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
453 can_msgobj_clear_fl(obj,TX_REQUEST);
455 if (can_read_reg(chip, SJASR) & SR_TBS)
456 sja1000_irq_write_handler(chip, obj);
458 can_msgobj_clear_fl(obj,TX_LOCK);
459 if(!can_msgobj_test_fl(obj,TX_REQUEST)) break;
462 can_preempt_enable();
466 int sja1000_register(struct chipspecops_t *chipspecops)
468 chipspecops->chip_config = sja1000_chip_config;
469 chipspecops->baud_rate = sja1000_baud_rate;
470 chipspecops->standard_mask = sja1000_standard_mask;
471 chipspecops->extended_mask = sja1000_extended_mask;
472 chipspecops->message15_mask = sja1000_extended_mask;
473 chipspecops->clear_objects = sja1000_clear_objects;
474 chipspecops->config_irqs = sja1000_config_irqs;
475 chipspecops->pre_read_config = sja1000_pre_read_config;
476 chipspecops->pre_write_config = sja1000_pre_write_config;
477 chipspecops->send_msg = sja1000_send_msg;
478 chipspecops->check_tx_stat = sja1000_check_tx_stat;
479 chipspecops->wakeup_tx=sja1000_wakeup_tx;
480 chipspecops->remote_request = sja1000_remote_request;
481 chipspecops->enable_configuration = sja1000_enable_configuration;
482 chipspecops->disable_configuration = sja1000_disable_configuration;
483 chipspecops->set_btregs = sja1000_set_btregs;
484 chipspecops->start_chip = sja1000_start_chip;
485 chipspecops->stop_chip = sja1000_stop_chip;
486 chipspecops->irq_handler = sja1000_irq_handler;