lincan/src/sja1000p.c

   1 /* sja1000.c
   2  * Linux CAN-bus device driver.
   3  * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
   4  * This software is released under the GPL-License.
   5  * Version 0.6 18 Sept 2000
   6  * Changed for PeliCan mode SJA1000 by Tomasz Motylewski (BFAD GmbH)
   7  * T.Motylewski@bfad.de
   8  */
   9
  10 #include <linux/autoconf.h>
  11 #if defined (CONFIG_MODVERSIONS) && !defined (MODVERSIONS)
  12 #define MODVERSIONS
  13 #endif
  14
  15 #if defined (MODVERSIONS)
  16 #include <linux/modversions.h>
  17 #endif
  18
  19 #include <linux/sched.h>
  20 #include <linux/delay.h>
  21 #include <asm/irq.h>
  22
  23 #include "../include/main.h"
  24 #include "../include/sja1000p.h"
  25
  26 int sja1000p_enable_configuration(struct chip_t *chip)
  27 {
  28         int i=0;
  29         enum sja1000_PeliCAN_MOD flags;
  30
  31         disable_irq(chip->chip_irq);
  32
  33         flags=can_read_reg(chip,SJAMOD);
  34
  35         while ((!(flags & MOD_RM)) && (i<=10)) {
  36                 can_write_reg(chip, MOD_RM, SJAMOD);
  37 // TODO: configurable MOD_AFM (32/16 bit acceptance filter)
  38 // config MOD_LOM (listen only)
  39                 udelay(100);
  40                 i++;
  41                 flags=can_read_reg(chip, SJAMOD);
  42         }
  43         if (i>=10) {
  44                 CANMSG("Reset error\n");
  45                 enable_irq(chip->chip_irq);
  46                 return -ENODEV;
  47         }
  48
  49         return 0;
  50 }
  51
  52 int sja1000p_disable_configuration(struct chip_t *chip)
  53 {
  54         int i=0;
  55         enum sja1000_PeliCAN_MOD flags;
  56
  57         flags=can_read_reg(chip,SJAMOD);
  58
  59         while ( (flags & MOD_RM) && (i<=50) ) {
  60 // could be as long as 11*128 bit times after buss-off
  61                 can_write_reg(chip, 0, SJAMOD);
  62 // TODO: configurable MOD_AFM (32/16 bit acceptance filter)
  63 // config MOD_LOM (listen only)
  64                 udelay(100);
  65                 i++;
  66                 flags=can_read_reg(chip, SJAMOD);
  67         }
  68         if (i>=10) {
  69                 CANMSG("Error leaving reset status\n");
  70                 return -ENODEV;
  71         }
  72
  73         enable_irq(chip->chip_irq);
  74
  75         return 0;
  76 }
  77
  78 int sja1000p_chip_config(struct chip_t *chip)
  79 {
  80         if (sja1000p_enable_configuration(chip))
  81                 return -ENODEV;
  82
  83         /* Set mode, clock out, comparator */
  84         can_write_reg(chip,CDR_PELICAN|chip->sja_cdr_reg,SJACDR);
  85         /* Set driver output configuration */
  86         can_write_reg(chip,chip->sja_ocr_reg,SJAOCR);
  87
  88         if (sja1000p_extended_mask(chip,0x00000000, 0xffffffff))
  89                 return -ENODEV;
  90
  91         if (!baudrate)
  92                 baudrate=1000;
  93         if (sja1000p_baud_rate(chip,1000*baudrate,chip->clock,0,75,0))
  94                 return -ENODEV;
  95
  96         /* Enable hardware interrupts */
  97         can_write_reg(chip, ENABLE_INTERRUPTS, SJAIER);
  98
  99         sja1000p_disable_configuration(chip);
 100
 101         return 0;
 102 }
 103
 104 int sja1000p_extended_mask(struct chip_t *chip, unsigned long code, unsigned  long mask)
 105 {
 106         int i;
 107
 108         if (sja1000p_enable_configuration(chip))
 109                 return -ENODEV;
 110
 111 // LSB to +3, MSB to +0
 112         for(i=SJA_PeliCAN_AC_LEN; --i>=0;) {
 113                 can_write_reg(chip,code&0xff,SJAACR0+i);
 114                 can_write_reg(chip,mask&0xff,SJAAMR0+i);
 115                 code >>= 8;
 116                 mask >>= 8;
 117         }
 118
 119         DEBUGMSG("Setting acceptance code to 0x%lx\n",(unsigned long)code);
 120         DEBUGMSG("Setting acceptance mask to 0x%lx\n",(unsigned long)mask);
 121
 122         sja1000p_disable_configuration(chip);
 123
 124         return 0;
 125 }
 126
 127 /* Set communication parameters.
 128  * param rate baud rate in Hz
 129  * param clock frequency of sja1000 clock in Hz (ISA osc is 14318000)
 130  * param sjw synchronization jump width (0-3) prescaled clock cycles
 131  * param sampl_pt sample point in % (0-100) sets (TSEG1+1)/(TSEG1+TSEG2+2) ratio
 132  * param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP
 133  */
 134 int sja1000p_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,
 135                                                         int sampl_pt, int flags)
 136 {
 137         int best_error = 1000000000, error;
 138         int best_tseg=0, best_brp=0, best_rate=0, brp=0;
 139         int tseg=0, tseg1=0, tseg2=0;
 140
 141         if (sja1000p_enable_configuration(chip))
 142                 return -ENODEV;
 143
 144         clock /=2;
 145
 146         /* tseg even = round down, odd = round up */
 147         for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++) {
 148                 brp = clock/((1+tseg/2)*rate)+tseg%2;
 149                 if (brp == 0 || brp > 64)
 150                         continue;
 151                 error = rate - clock/(brp*(1+tseg/2));
 152                 if (error < 0)
 153                         error = -error;
 154                 if (error <= best_error) {
 155                         best_error = error;
 156                         best_tseg = tseg/2;
 157                         best_brp = brp-1;
 158                         best_rate = clock/(brp*(1+tseg/2));
 159                 }
 160         }
 161         if (best_error && (rate/best_error < 10)) {
 162                 CANMSG("baud rate %d is not possible with %d Hz clock\n",
 163                                                                 rate, 2*clock);
 164                 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
 165                                 best_rate, best_brp, best_tseg, tseg1, tseg2);
 166                 return -EINVAL;
 167         }
 168         tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
 169         if (tseg2 < 0)
 170                 tseg2 = 0;
 171         if (tseg2 > MAX_TSEG2)
 172                 tseg2 = MAX_TSEG2;
 173         tseg1 = best_tseg-tseg2-2;
 174         if (tseg1>MAX_TSEG1) {
 175                 tseg1 = MAX_TSEG1;
 176                 tseg2 = best_tseg-tseg1-2;
 177         }
 178
 179         DEBUGMSG("Setting %d bps.\n", best_rate);
 180         DEBUGMSG("brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
 181                                         best_brp, best_tseg, tseg1, tseg2,
 182                                         (100*(best_tseg-tseg2)/(best_tseg+1)));
 183
 184
 185         can_write_reg(chip, sjw<<6 | best_brp, SJABTR0);
 186         can_write_reg(chip, ((flags & BTR1_SAM) != 0)<<7 | (tseg2<<4)
 187                                         | tseg1, SJABTR1);
 188
 189         sja1000p_disable_configuration(chip);
 190
 191         return 0;
 192 }
 193
 194 void sja1000p_read(struct chip_t *chip, struct canfifo_t *fifo) {
 195         int i, flags, len, datastart;
 196         do {
 197                 flags = can_read_reg(chip,SJAFRM);
 198                 if(flags&FRM_FF) {
 199                         fifo->rx_writep->id =
 200                                 (can_read_reg(chip,SJAID0)<<21) +
 201                                 (can_read_reg(chip,SJAID1)<<13) +
 202                                 (can_read_reg(chip,SJAID2)<<5) +
 203                                 (can_read_reg(chip,SJAID3)>>3);
 204                         datastart = SJADATE;
 205                 } else {
 206                         fifo->rx_writep->id =
 207                                 (can_read_reg(chip,SJAID0)<<3) +
 208                                 (can_read_reg(chip,SJAID1)>>5);
 209                         datastart = SJADATS;
 210                 }
 211                 fifo->rx_writep->flags =
 212                         ((flags & FRM_RTR) ? MSG_RTR : 0) |
 213                         ((flags & FRM_FF) ? MSG_EXT : 0);
 214                 len = flags & FRM_DLC_M;
 215                 for(i=0; i< len; i++) {
 216                         fifo->rx_writep->data[i]=can_read_reg(chip,datastart+i);
 217                 }
 218                 fifo->rx_writep->length = len;
 219
 220                 fifo->rx_writep++;
 221                 if (fifo->rx_writep >= fifo->buf_rx_entry + MAX_BUF_LENGTH)
 222                         fifo->rx_writep = fifo->buf_rx_entry;
 223
 224 // FIXME: what if fifo->rx_writep == fifo->rx_readp again ?
 225
 226                 can_write_reg(chip, CMR_RRB, SJACMR);
 227         } while (can_read_reg(chip, SJASR) & SR_RBS);
 228 }
 229
 230 int sja1000p_pre_read_config(struct chip_t *chip, struct msgobj_t *obj)
 231 {
 232         int status;
 233         status=can_read_reg(chip,SJASR);
 234
 235         if(status  & SR_BS) {
 236                 /* Try to recover from error condition */
 237                 DEBUGMSG("sja1000p_pre_read_config bus-off recover 0x%x\n",status);
 238                 sja1000p_enable_configuration(chip);
 239                 can_write_reg(chip, 0, SJARXERR);
 240                 can_write_reg(chip, 0, SJATXERR1);
 241                 can_read_reg(chip, SJAECC);
 242                 sja1000p_disable_configuration(chip);
 243         }
 244
 245         if (!(status&SR_RBS)) {
 246                 return 0;
 247         }
 248
 249         can_write_reg(chip, DISABLE_INTERRUPTS, SJAIER); //disable interrupts for a moment
 250         sja1000p_read(chip, obj->fifo);
 251         can_write_reg(chip, ENABLE_INTERRUPTS, SJAIER); //enable interrupts
 252         return 1;
 253 }
 254
 255 #define MAX_TRANSMIT_WAIT_LOOPS 200
 256 int sja1000p_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
 257                                                         struct canmsg_t *msg)
 258 {
 259         int i=0;
 260         unsigned int id;
 261         int status;
 262
 263         /* Wait until Transmit Buffer Status is released */
 264         while ( !((status=can_read_reg(chip, SJASR)) & SR_TBS) &&
 265                                                 i++<MAX_TRANSMIT_WAIT_LOOPS) {
 266                 udelay(i);
 267         }
 268
 269         if(status & SR_BS) {
 270                 /* Try to recover from error condition */
 271                 DEBUGMSG("sja1000p_pre_write_config bus-off recover 0x%x\n",status);
 272                 sja1000p_enable_configuration(chip);
 273                 can_write_reg(chip, 0, SJARXERR);
 274                 can_write_reg(chip, 0, SJATXERR1);
 275                 can_read_reg(chip, SJAECC);
 276                 sja1000p_disable_configuration(chip);
 277         }
 278         if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
 279                 CANMSG("Transmit timed out, cancelling\n");
 280 // here we should check if there is no write/select waiting for this
 281 // transmit. If so, set error ret and wake up.
 282 // CHECKME: if we do not disable IER_TIE (TX IRQ) here we get interrupt
 283 // immediately
 284                 can_write_reg(chip, CMR_AT, SJACMR);
 285                 i=0;
 286                 while ( !(can_read_reg(chip, SJASR) & SR_TBS) &&
 287                                                 i++<MAX_TRANSMIT_WAIT_LOOPS) {
 288                         udelay(i);
 289                 }
 290                 if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
 291                         CANMSG("Could not cancel, please reset\n");
 292                         return -EIO;
 293                 }
 294         }
 295         msg->length &= FRM_DLC_M;
 296         can_write_reg(chip, ((msg->flags&MSG_EXT)?FRM_FF:0) |
 297                 ((msg->flags & MSG_RTR) ? FRM_RTR : 0) |
 298                 msg->length, SJAFRM);
 299         if(msg->flags&MSG_EXT) {
 300                 id=msg->id<<3;
 301                 can_write_reg(chip, id & 0xff, SJAID3);
 302                 id >>= 8;
 303                 can_write_reg(chip, id & 0xff, SJAID2);
 304                 id >>= 8;
 305                 can_write_reg(chip, id & 0xff, SJAID1);
 306                 id >>= 8;
 307                 can_write_reg(chip, id, SJAID0);
 308                 for(i=0; i < msg->length; i++) {
 309                         can_write_reg(chip, msg->data[i], SJADATE+i);
 310                 }
 311         } else {
 312                 id=msg->id<<5;
 313                 can_write_reg(chip, (id >> 8) & 0xff, SJAID0);
 314                 can_write_reg(chip, id & 0xff, SJAID1);
 315                 for(i=0; i < msg->length; i++) {
 316                         can_write_reg(chip, msg->data[i], SJADATS+i);
 317                 }
 318         }
 319         return 0;
 320 }
 321
 322 int sja1000p_send_msg(struct chip_t *chip, struct msgobj_t *obj,
 323                                                         struct canmsg_t *msg)
 324 {
 325         can_write_reg(chip, CMR_TR, SJACMR);
 326
 327         return 0;
 328 }
 329
 330 int sja1000p_check_tx_stat(struct chip_t *chip)
 331 {
 332         if (can_read_reg(chip,SJASR) & SR_TCS)
 333                 return 0;
 334         else
 335                 return 1;
 336 }
 337
 338 int sja1000p_set_btregs(struct chip_t *chip, unsigned short btr0,
 339                                                         unsigned short btr1)
 340 {
 341         if (sja1000p_enable_configuration(chip))
 342                 return -ENODEV;
 343
 344         can_write_reg(chip, btr0, SJABTR0);
 345         can_write_reg(chip, btr1, SJABTR1);
 346
 347         sja1000p_disable_configuration(chip);
 348
 349         return 0;
 350 }
 351
 352 int sja1000p_start_chip(struct chip_t *chip)
 353 {
 354         enum sja1000_PeliCAN_MOD flags;
 355
 356         flags = can_read_reg(chip, SJAMOD) & (MOD_LOM|MOD_STM|MOD_AFM|MOD_SM);
 357         can_write_reg(chip, flags, SJAMOD);
 358
 359         return 0;
 360 }
 361
 362 int sja1000p_stop_chip(struct chip_t *chip)
 363 {
 364         enum sja1000_PeliCAN_MOD flags;
 365
 366         flags = can_read_reg(chip, SJAMOD) & (MOD_LOM|MOD_STM|MOD_AFM|MOD_SM);
 367         can_write_reg(chip, flags|MOD_RM, SJAMOD);
 368
 369         return 0;
 370 }
 371
 372
 373 int sja1000p_remote_request(struct chip_t *chip, struct msgobj_t *obj)
 374 {
 375         CANMSG("sja1000p_remote_request not implemented\n");
 376         return -ENOSYS;
 377 }
 378
 379 int sja1000p_standard_mask(struct chip_t *chip, unsigned short code,
 380                 unsigned short mask)
 381 {
 382         CANMSG("sja1000p_standard_mask not implemented\n");
 383         return -ENOSYS;
 384 }
 385
 386 int sja1000p_clear_objects(struct chip_t *chip)
 387 {
 388         CANMSG("sja1000p_clear_objects not implemented\n");
 389         return -ENOSYS;
 390 }
 391
 392 int sja1000p_config_irqs(struct chip_t *chip, short irqs)
 393 {
 394         CANMSG("sja1000p_config_irqs not implemented\n");
 395         return -ENOSYS;
 396 }
 397
 398 void sja1000p_irq_write_handler(struct chip_t *chip, struct canfifo_t *fifo)
 399 {
 400         fifo->tx_readp++;
 401         if (fifo->tx_readp >= fifo->buf_tx_entry + MAX_BUF_LENGTH)
 402                 fifo->tx_readp = fifo->buf_tx_entry;
 403         if (fifo->tx_readp == fifo->tx_writep) { // Output buffer is empty
 404                 fifo->tx_in_progress = 0;
 405                 if (waitqueue_active(&fifo->writeq)) {
 406                         chip->msgobj[0]->ret = 0; //CHECKME or 26?
 407                         wake_up_interruptible(&fifo->writeq);
 408                 }
 409                 return;
 410         }
 411         if (chip->chipspecops->pre_write_config(chip, chip->msgobj[0],
 412                                 fifo->tx_readp)) {
 413                 if (waitqueue_active(&fifo->writeq)) {
 414                         chip->msgobj[0]->ret = -1;
 415                         wake_up_interruptible(&fifo->writeq);
 416                         return;
 417                 }
 418         }
 419         if (chip->chipspecops->send_msg(chip, chip->msgobj[0],
 420                 fifo->tx_readp)) {
 421                 if (waitqueue_active(&fifo->writeq)) {
 422                         chip->msgobj[0]->ret = -1;
 423                         wake_up_interruptible(&fifo->writeq);
 424                         return;
 425                 }
 426         }
 427
 428 }
 429
 430 #define MAX_RETR 10
 431
 432 void sja1000p_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
 433 {
 434         int irq_register, status, error_code;
 435         int static retransmitted=0; /* FIXME - should go into chip struct */
 436         struct chip_t *chip=(struct chip_t *)dev_id;
 437         struct canfifo_t *fifo;
 438
 439         irq_register=can_read_reg(chip,SJAIR);
 440 //      DEBUGMSG("sja1000_irq_handler: SJAIR:%02x\n",irq_register);
 441 //      DEBUGMSG("sja1000_irq_handler: SJASR:%02x\n",
 442 //                                      can_read_reg(chip,SJASR));
 443
 444         if ((irq_register & (IR_BEI|IR_EPI|IR_DOI|IR_EI|IR_TI|IR_RI)) == 0)
 445                 return;
 446
 447         if(!chip->msgobj[0]->flags & BUFFERS_ALLOCATED) {
 448                 CANMSG("sja1000p_irq_handler: called with device closed, irq_register 0x%02x\n", irq_register);
 449                 return;
 450         }
 451         fifo=chip->msgobj[0]->fifo;
 452
 453         if ((irq_register & IR_RI) != 0) {
 454                 sja1000p_read(chip,fifo);
 455                 chip->msgobj[0]->ret = 0;
 456                 if (waitqueue_active(&fifo->readq))
 457                         wake_up_interruptible(&fifo->readq);
 458         }
 459         if ((irq_register & IR_TI) != 0) {
 460                 chip->msgobj[0]->ret = 0;
 461                 sja1000p_irq_write_handler(chip,fifo);
 462         }
 463         if ((irq_register & (IR_EI|IR_BEI|IR_EPI|IR_DOI)) != 0) {
 464                 // Some error happened
 465                 status=can_read_reg(chip,SJASR);
 466                 error_code=can_read_reg(chip,SJAECC);
 467                 CANMSG("Error: status register: 0x%x irq_register: 0x%02x error: 0x%02x\n",
 468                         status, irq_register, error_code);
 469 // FIXME: chip should be brought to usable state. Transmission cancelled if in progress.
 470 // Reset flag set to 0 if chip is already off the bus. Full state report
 471                 chip->msgobj[0]->ret=-1;
 472
 473                 if(error_code == 0xd9) {
 474                         chip->msgobj[0]->ret= -ENXIO;
 475                         /* no such device or address - no ACK received */
 476                 }
 477                 if(retransmitted++>MAX_RETR) {
 478                         can_write_reg(chip, CMR_AT, SJACMR); // cancel any transmition
 479                         retransmitted = 0;
 480                 }
 481                 if(status&SR_BS) {
 482                         CANMSG("bus-off, resetting sja1000p\n");
 483                         can_write_reg(chip, 0, SJAMOD);
 484                 }
 485
 486                 if (waitqueue_active(&fifo->writeq))
 487                         wake_up_interruptible(&fifo->writeq);
 488                 if (waitqueue_active(&fifo->readq))
 489                         wake_up_interruptible(&fifo->readq);
 490         } else {
 491                 retransmitted=0;
 492         }
 493
 494         return;
 495 }
 496
 497 int sja1000p_register(struct chipspecops_t *chipspecops)
 498 {
 499         CANMSG("initializing sja1000p chip operations\n");
 500         chipspecops->chip_config=sja1000p_chip_config;
 501         chipspecops->baud_rate=sja1000p_baud_rate;
 502         chipspecops->standard_mask=sja1000p_standard_mask;
 503         chipspecops->extended_mask=sja1000p_extended_mask;
 504         chipspecops->message15_mask=sja1000p_extended_mask;
 505         chipspecops->clear_objects=sja1000p_clear_objects;
 506         chipspecops->config_irqs=sja1000p_config_irqs;
 507         chipspecops->pre_read_config=sja1000p_pre_read_config;
 508         chipspecops->pre_write_config=sja1000p_pre_write_config;
 509         chipspecops->send_msg=sja1000p_send_msg;
 510         chipspecops->check_tx_stat=sja1000p_check_tx_stat;
 511         chipspecops->remote_request=sja1000p_remote_request;
 512         chipspecops->enable_configuration=sja1000p_enable_configuration;
 513         chipspecops->disable_configuration=sja1000p_disable_configuration;
 514         chipspecops->set_btregs=sja1000p_set_btregs;
 515         chipspecops->start_chip=sja1000p_start_chip;
 516         chipspecops->stop_chip=sja1000p_stop_chip;
 517         chipspecops->irq_handler=sja1000p_irq_handler;
 518         return 0;
 519 }