1 #include "local_config.h"
2 #include <system_def.h>
6 #include <lpciap_kvpb.h>
7 #endif /* CONFIG_KEYVAL */
8 #ifdef CONFIG_STDIO_COM_PORT
11 #ifdef CONFIG_OC_UL_DRV_SYSLESS
12 #include <ul_lib/ulan.h>
14 #include <ul_drv_init.h>
15 #include <ul_drv_iac.h>
16 #include <ul_lib/ul_drvdef.h>
17 extern long int uld_jiffies;
18 #endif /* CONFIG_OC_UL_DRV_SYSLESS */
19 #ifdef CONFIG_OC_I2C_DRV_SYSLESS
21 #endif /* CONFIG_OC_I2C_DRV_SYSLESS */
22 #include <hal_machperiph.h>
26 volatile lt_ticks_t sys_timer_ticks;
28 static void sysInit(void)
34 // setup & enable the MAM
36 MAMTIM = MAMTIM_CYCLES;
39 // set the peripheral bus speed
40 // value computed from config.h
41 VPBDIV = VPBDIV_VALUE; // set the peripheral bus clock speed
43 // setup the parallel port pin
44 IO0CLR = P0IO_ZERO_BITS; // clear the ZEROs output
45 IO0SET = P0IO_ONE_BITS; // set the ONEs output
46 IO0DIR = P0IO_OUTPUT_BITS; // set the output bit direction
48 #ifdef P1IO_OUTPUT_BITS
49 IO1CLR = P1IO_ZERO_BITS; // clear the ZEROs output
50 IO1SET = P1IO_ONE_BITS; // set the ONEs output
51 IO1DIR = P1IO_OUTPUT_BITS; // set the output bit direction
54 IO0CLR = LED1_BIT; // Indicate functional state on the LED1
63 T0MR0+=PCLK/SYS_TIMER_HZ;
64 T0IR=TIR_MR0I; // Clear match0 interrupt
65 #ifdef CONFIG_OC_UL_DRV_SYSLESS
69 } while (((int32_t)(T0MR0-T0TC))<0);
77 HAL_INTERRUPT_ATTACH(HAL_INTERRUPT_TIMER0,timer0_isr,0);
78 HAL_INTERRUPT_UNMASK(HAL_INTERRUPT_TIMER0);
83 T0MR0=PCLK/SYS_TIMER_HZ; /* ms tics */
86 T0TCR = TCR_ENABLE; //Run timer 0
89 #ifdef CONFIG_STDIO_COM_PORT
91 int uartcon_write(int file, char * ptr, int len)
95 for(cnt=0;cnt<len;cnt++,ptr++){
104 void init_system_stub(void) {
105 system_stub_ops.write=uartcon_write;
108 #endif /* CONFIG_STDIO_COM_PORT */
110 #ifdef CONFIG_OC_UL_DRV_SYSLESS
112 extern unsigned uld_debug_flg; /* Left application set defaults */
114 #ifndef CONFIG_KEYVAL
115 unsigned long lpciap_buff[ISP_RAM2FLASH_BLOCK_SIZE/4];
116 #endif /* CONFIG_KEYVAL */
118 #define UL_MTYPE_START32BIT 0x100
120 static inline int ul_iac_mem_head_rd(uint8_t *buf, int len,
121 uint32_t* pmtype, uint32_t* pstart, uint32_t* plen)
124 if (len<6) return -1;
125 mtype=*(buf++); /* memory type */
127 val=*(buf++); /* start address */
129 if(mtype&UL_MTYPE_START32BIT){
130 if (len<8) return -1;
131 val+=(uint32_t)*(buf++)<<16;
132 val+=(uint32_t)*(buf++)<<24;
135 val=*(buf++); /* length */
137 if(mtype&UL_MTYPE_START32BIT){
139 val+=(uint32_t)*(buf++)<<16;
140 val+=(uint32_t)*(buf++)<<24;
144 mtype&=~UL_MTYPE_START32BIT; /* 32-bit start address */
149 int ul_iac_call_rdm(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data)
151 uint32_t mtype,start,len;
155 if(ul_iac_mem_head_rd((uint8_t *)ibuff, msginfo->len,&mtype,&start,&len))
156 return UL_IAC_RC_PROC;
160 data->buff=(unsigned char*)start;
161 return UL_IAC_RC_FREEMSG;
163 return UL_IAC_RC_PROC;
166 int ul_iac_call_erm(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data)
168 uint32_t mtype,start,len;
172 if(ul_iac_mem_head_rd((uint8_t *)ibuff, msginfo->len,&mtype,&start,&len))
173 return UL_IAC_RC_PROC;
177 lpcisp_erase((void*)start,len);
179 return UL_IAC_RC_FREEMSG;
181 #endif /* CONFIG_KEYVAL */
182 return UL_IAC_RC_PROC;
185 int ul_iac_call_wrm(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data)
187 uint32_t mtype,start,len;
191 if(ul_iac_mem_head_rd((uint8_t *)ibuff, msginfo->len,&mtype,&start,&len))
192 return UL_IAC_RC_PROC;
195 memcpy((void*)start,data->buff,data->len);
196 return UL_IAC_RC_FREEMSG;
200 lpcisp_write((char*)start, data->buff, ISP_RAM2FLASH_BLOCK_SIZE);
201 return UL_IAC_RC_FREEMSG;
203 #endif /* CONFIG_KEYVAL */
204 return UL_IAC_RC_PROC;
208 int ul_iac_call_deb(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data)
210 uint32_t debcmd,mtype,start;
211 uint8_t *p=(uint8_t*)ibuff;
213 if (msginfo->len<1) return UL_IAC_RC_PROC;
216 case 0x10: /* goto */
218 if (msginfo->len<5) return UL_IAC_RC_PROC;
223 if(mtype&UL_MTYPE_START32BIT){
224 mtype&=~UL_MTYPE_START32BIT;
225 if (msginfo->len<7) return UL_IAC_RC_PROC;
226 start+=(uint32_t)*(p++)<<16;
227 start+=(uint32_t)*(p++)<<24;
230 ((void (*)())start)();
233 return UL_IAC_RC_PROC;
236 int ul_iac_call_res(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data)
238 uint32_t rescmd,pass;
239 uint8_t *p=(uint8_t*)ibuff;
241 if (msginfo->len<1) return UL_IAC_RC_PROC;
244 case ULRES_CPU: /* CPU */
246 if (msginfo->len<3) return UL_IAC_RC_PROC;
251 lpc_watchdog_init(1,10); /* 10ms */
257 return UL_IAC_RC_PROC;
264 /* set rs485 mode for UART1 */
265 PINSEL0 = (PINSEL0 & ~0xFFFF0000) | 0x01550000; /* dsr(txd), cts(rxd), rts(rs485_dir), rxd, txd */
267 udrv=ul_drv_new(UL_DRV_SYSLESS_PORT, /* port */
268 UL_DRV_SYSLESS_IRQ, /* irq */
269 UL_DRV_SYSLESS_BAUD, /* baud */
270 UL_DRV_SYSLESS_MY_ADR_DEFAULT, /* my adr */
271 #ifdef CONFIG_OC_UL_DRV_U450_VARPINS
272 #ifdef CONFIG_OC_UL_DRV_U450_VARPINS_MSRSWAP
273 "16450-msrswap", /* chip name */
274 #elif defined(CONFIG_OC_UL_DRV_U450_VARPINS_DIRNEG)
275 "16450-dirneg", /* chip name */
277 "16450", /* chip name */
279 #else /*CONFIG_OC_UL_DRV_U450_VARPINS*/
280 "16450", /* chip name */
281 #endif /*CONFIG_OC_UL_DRV_U450_VARPINS*/
282 0); /* baud base - default */
287 ul_drv_add_iac(udrv,UL_CMD_RDM,UL_IAC_OP_SND,ul_iac_call_rdm,NULL,0,0,NULL);
288 ul_drv_add_iac(udrv,UL_CMD_ERM,UL_IAC_OP_CALLBACK,ul_iac_call_erm,NULL,0,0,NULL);
289 ul_drv_add_iac(udrv,UL_CMD_WRM,UL_IAC_OP_REC,ul_iac_call_wrm,(char*)lpciap_buff,0,0,NULL);
290 ul_drv_add_iac(udrv,UL_CMD_DEB,UL_IAC_OP_CALLBACK,ul_iac_call_deb,NULL,0,0,NULL);
291 ul_drv_add_iac(udrv,UL_CMD_RES,UL_IAC_OP_CALLBACK,ul_iac_call_res,NULL,0,0,NULL);
293 return ul_drv_add_dev(udrv);
295 #endif /* CONFIG_OC_UL_DRV_SYSLESS */
297 #ifdef CONFIG_OC_I2C_DRV_SYSLESS
306 PINSEL0 = (PINSEL0 & ~0x000000F0) | 0x00000050; /* I2C - SCL, SDA */
308 if (i2c_drv_init(&i2c_drv,
309 I2C_DRV_SYSLESS_PORT,
311 I2C_DRV_SYSLESS_BITRATE,
312 I2C_DRV_SYSLESS_SLADR)<0) return -1;
317 #endif /*CONFIG_OC_I2C_DRV_SYSLESS*/
321 // initialize the system
324 #ifdef WATCHDOG_ENABLED
325 lpc_watchdog_init(1,WATCHDOG_TIMEOUT_MS);
327 #endif /* WATCHDOG_ENABLED */
329 // initialize the system timer
332 #ifdef CONFIG_STDIO_COM_PORT
333 uart0Init( B57600 , UART_8N1, UART_FIFO_8);
335 #endif /* CONFIG_STDIO_COM_PORT */
337 #ifdef CONFIG_OC_UL_DRV_SYSLESS
338 // uld_debug_flg=0x3ff;
340 #endif /* CONFIG_OC_UL_DRV_SYSLESS */
342 #ifdef CONFIG_OC_I2C_DRV_SYSLESS
344 #endif /* CONFIG_OC_I2C_DRV_SYSLESS */