1 /******************************************************************************
3 * $RCSfile: lpcSCB.h,v $
6 * Header file for Philips LPC ARM Processors.
7 * Copyright 2004 R O SoftWare
9 * No guarantees, warrantees, or promises, implied or otherwise.
10 * May be used for hobby or commercial purposes provided copyright
11 * notice remains intact.
13 *****************************************************************************/
17 // System Control Block Registers
20 // Memory Accelerator Module Registers (MAM)
23 REG_8 cr; // Control Register
25 REG_8 tim; // Timing Control Register
29 // Memory Mapping Control Register
33 // Phase Locked Loop Registers (PLL)
36 REG_8 con; // Control Register
38 REG_8 cfg; // Configuration Register
40 REG16 stat; // Status Register
42 REG_8 feed; // Feed Register
49 REG_8 con; // Control Register
51 REG_8 cfg; // Configuration Register
53 REG16 stat; // Status Register
55 REG_8 feed; // Feed Register
60 // Power Control Registers
63 REG_8 con; // Control Register
65 REG32 conp; // Peripherals Register
69 // VPB Divider Register
73 // External Interrupt Registers
76 REG_8 flag; // Flag Register
78 REG_8 wake; // Wakeup Register
80 REG_8 mode; // Mode Register
82 REG_8 polar; // Polarity Register
88 ///////////////////////////////////////////////////////////////////////////////
94 #define MAMTIM_CYCLES (((CCLK) + 19999999) / 20000000)
96 ///////////////////////////////////////////////////////////////////////////////
98 #define MEMMAP_BBLK 0 // Interrupt Vectors in Boot Block
99 #define MEMMAP_FLASH 1 // Interrupt Vectors in Flash
100 #define MEMMAP_SRAM 2 // Interrupt Vectors in SRAM
102 ///////////////////////////////////////////////////////////////////////////////
103 // PLL defines & computations
104 // Compute the value of PLL_DIV and test range validity
105 // FOSC & PLL_MUL should be defined in project configuration file (config.h)
107 #define CCLK (FOSC * PLL_MUL) // CPU Clock Freq.
110 #define FCCO_MAX (320000000) // Max CC Osc Freq.
111 #define PLL_DIV (FCCO_MAX / (2 * CCLK)) // PLL Divider
112 #define FCCO (FOSC * PLL_MUL * 2 * PLL_DIV) // CC Osc. Freq.
114 // PLLCON Register Bit Definitions
115 #define PLLCON_PLLE (1 << 0) // PLL Enable
116 #define PLLCON_PLLC (1 << 1) // PLL Connect
118 // PLLCFG Register Bit Definitions
119 #define PLLCFG_MSEL ((PLL_MUL - 1) << 0) // PLL Multiplier
120 #define PLLCFG_PSEL ((PLL_DIV - 1) << 5) // PLL Divider
122 // PLLSTAT Register Bit Definitions
123 #define PLLSTAT_LOCK (1 << 10) // PLL Lock Status Bit
125 ///////////////////////////////////////////////////////////////////////////////
126 // VPBDIV defines & computations
127 #define VPBDIV_VALUE (PBSD & 0x03) // VPBDIV value