2 * Header file for the Linux CAN-bus driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
5 * email:pisa@cmp.felk.cvut.cz
6 * This software is released under the GPL-License.
7 * Version lincan-0.2 9 Jul 2003
11 #include "./constants.h"
12 #include "./can_sysdep.h"
13 #include "./can_queue.h"
14 #include "lincan_config.h"
16 #ifdef CONFIG_OC_LINCANVME
17 #define CAN_ENABLE_VME_SUPPORT
21 #define DEBUGMSG(fmt,args...) can_printk(KERN_ERR "can.o (debug): " fmt,\
24 #define DEBUGMSG(fmt,args...)
27 #define CANMSG(fmt,args...) can_printk(KERN_ERR "can.o: " fmt,##args)
30 extern can_spinlock_t canuser_manipulation_lock;
33 * struct canhardware_t - structure representing pointers to all CAN boards
34 * @nr_boards: number of present boards
35 * @rtr_queue: RTR - remote transmission request queue (expect some changes there)
36 * @rtr_lock: locking for RTR queue
37 * @candevice: array of pointers to CAN devices/boards
39 struct canhardware_t {
41 struct rtr_id *rtr_queue;
42 can_spinlock_t rtr_lock;
43 struct candevice_t *candevice[MAX_HW_CARDS];
47 * struct candevice_t - CAN device/board structure
48 * @hwname: text string with board type
49 * @candev_idx: board index in canhardware_t.candevice[]
50 * @io_addr: IO/physical MEM address
51 * @res_addr: optional reset register port
52 * @dev_base_addr: CPU translated IO/virtual MEM address
53 * @flags: board flags: %PROGRAMMABLE_IRQ .. interrupt number
54 * can be programmed into board
55 * @nr_all_chips: number of chips present on the board
56 * @nr_82527_chips: number of Intel 8257 chips
57 * @nr_sja1000_chips: number of Philips SJA100 chips
58 * @chip: array of pointers to the chip structures
59 * @hwspecops: pointer to board specific operations
60 * @hosthardware_p: pointer to the root hardware structure
61 * @sysdevptr: union reserved for pointer to bus specific
62 * device structure (case @pcidev is used for PCI devices)
64 * The structure represent configuration and state of associated board.
65 * The driver infrastructure prepares this structure and calls
66 * board type specific board_register() function. The board support provided
67 * register function fills right function pointers in @hwspecops structure.
68 * Then driver setup calls functions init_hw_data(), init_chip_data(),
69 * init_chip_data(), init_obj_data() and program_irq(). Function init_hw_data()
70 * and init_chip_data() have to specify number and types of connected chips
71 * or objects respectively.
72 * The use of @nr_all_chips is preferred over use of fields @nr_82527_chips
73 * and @nr_sja1000_chips in the board non-specific functions.
74 * The @io_addr and @dev_base_addr is filled from module parameters
75 * to the same value. The request_io function can fix-up @dev_base_addr
76 * field if virtual address is different than bus address.
79 char *hwname; /* text board type */
80 int candev_idx; /* board index in canhardware_t.candevice[] */
81 unsigned long io_addr; /* IO/physical MEM address */
82 unsigned long res_addr; /* optional seset register port */
83 unsigned long dev_base_addr; /* CPU translated IO/virtual MEM address */
88 struct chip_t *chip[MAX_HW_CHIPS];
90 struct hwspecops_t *hwspecops;
92 struct canhardware_t *hosthardware_p;
96 #ifdef CAN_ENABLE_PCI_SUPPORT
97 struct pci_dev *pcidev;
98 #endif /*CAN_ENABLE_PCI_SUPPORT*/
104 * struct chip_t - CAN chip state and type information
105 * @chip_type: text string describing chip type
106 * @chip_idx: index of the chip in candevice_t.chip[] array
107 * @chip_irq: chip interrupt number if any
108 * @chip_base_addr: chip base address in the CPU IO or virtual memory space
109 * @flags: chip flags: %CHIP_CONFIGURED .. chip is configured,
110 * %CHIP_SEGMENTED .. access to the chip is segmented (mainly for i82527 chips)
111 * @clock: chip base clock frequency in Hz
112 * @baudrate: selected chip baudrate in Hz
113 * @write_register: write chip register function copy
114 * @read_register: read chip register function copy
115 * @chip_data: pointer for optional chip specific data extension
116 * @sja_cdr_reg: SJA specific register -
117 * holds hardware specific options for the Clock Divider
118 * register. Options defined in the sja1000.h file:
119 * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
120 * @sja_ocr_reg: SJA specific register -
121 * hold hardware specific options for the Output Control
122 * register. Options defined in the sja1000.h file:
123 * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
124 * %OCR_TX0_LH, %OCR_TX1_ZZ.
125 * @int_cpu_reg: Intel specific register -
126 * holds hardware specific options for the CPU Interface
127 * register. Options defined in the i82527.h file:
128 * %iCPU_CEN, %iCPU_MUX, %iCPU_SLP, %iCPU_PWD, %iCPU_DMC, %iCPU_DSC, %iCPU_RST.
129 * @int_clk_reg: Intel specific register -
130 * holds hardware specific options for the Clock Out
131 * register. Options defined in the i82527.h file:
132 * %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
133 * @int_bus_reg: Intel specific register -
134 * holds hardware specific options for the Bus Configuration
135 * register. Options defined in the i82527.h file:
136 * %iBUS_DR0, %iBUS_DR1, %iBUS_DT1, %iBUS_POL, %iBUS_CBY.
137 * @msgobj: array of pointers to individual communication objects
138 * @chipspecops: pointer to the set of chip specific object filled by init_chip_data() function
139 * @hostdevice: pointer to chip hosting board
140 * @max_objects: maximal number of communication objects connected to this chip
141 * @chip_lock: reserved for synchronization of the chip supporting routines
142 * (not used in the current driver version)
143 * @worker_thread: chip worker thread ID (RT-Linux specific field)
144 * @pend_flags: holds information about pending interrupt and tx_wake() operations
145 * (RT-Linux specific field). Masks values:
146 * %MSGOBJ_TX_REQUEST .. some of the message objects requires tx_wake() call,
147 * %MSGOBJ_IRQ_REQUEST .. chip interrupt processing required
148 * %MSGOBJ_WORKER_WAKE .. marks, that worker thread should be waked
149 * for some of above reasons
151 * The fields @write_register and @read_register are copied from
152 * corresponding fields from @hwspecops structure
153 * (chip->hostdevice->hwspecops->write_register and
154 * chip->hostdevice->hwspecops->read_register)
155 * to speedup can_write_reg() and can_read_reg() functions.
159 int chip_idx; /* chip index in candevice_t.chip[] */
161 unsigned long chip_base_addr;
163 long clock; /* Chip clock in Hz */
166 void (*write_register)(unsigned char data,unsigned long address);
167 unsigned (*read_register)(unsigned long address);
171 unsigned short sja_cdr_reg; /* sja1000 only! */
172 unsigned short sja_ocr_reg; /* sja1000 only! */
173 unsigned short int_cpu_reg; /* intel 82527 only! */
174 unsigned short int_clk_reg; /* intel 82527 only! */
175 unsigned short int_bus_reg; /* intel 82527 only! */
177 struct msgobj_t *msgobj[MAX_MSGOBJS];
179 struct chipspecops_t *chipspecops;
181 struct candevice_t *hostdevice;
183 int max_objects; /* 1 for sja1000, 15 for i82527 */
185 can_spinlock_t chip_lock;
188 pthread_t worker_thread;
189 unsigned long pend_flags;
190 #endif /*CAN_WITH_RTL*/
194 * struct msgobj_t - structure holding communication object state
196 * @minor: associated device minor number
197 * @object: object number in chip_t structure +1
198 * @flags: message object flags
199 * @ret: field holding status of the last Tx operation
200 * @qends: pointer to message object corresponding ends structure
201 * @tx_qedge: edge corresponding to transmitted message
202 * @tx_slot: slot holding transmitted message, slot is taken from
203 * canque_test_outslot() call and is freed by canque_free_outslot()
204 * or rescheduled canque_again_outslot()
205 * @tx_retry_cnt: transmission attempt counter
206 * @tx_timeout: can be used by chip driver to check for the transmission timeout
207 * @rx_msg: temporary storage to hold received messages before
208 * calling to canque_filter_msg2edges()
209 * @hostchip: pointer to the &chip_t structure this object belongs to
210 * @obj_used: counter of users (associated file structures for Linux
211 * userspace clients) of this object
212 * @obj_users: list of user structures of type &canuser_t.
213 * @obj_flags: message object specific flags. Masks values:
214 * %MSGOBJ_TX_REQUEST .. the message object requests TX activation
215 * %MSGOBJ_TX_LOCK .. some IRQ routine or callback on some CPU
216 * is running inside TX activation processing code
219 unsigned long obj_base_addr;
220 unsigned int minor; /* associated device minor number */
221 unsigned int object; /* object number in chip_t +1 for debug printk */
222 unsigned long obj_flags;
225 struct canque_ends_t *qends;
227 struct canque_edge_t *tx_qedge;
228 struct canque_slot_t *tx_slot;
230 struct timer_list tx_timeout;
232 struct canmsg_t rx_msg;
234 struct chip_t *hostchip;
237 struct list_head obj_users;
240 #define CAN_USER_MAGIC 0x05402033
243 * struct canuser_t - structure holding CAN user/client state
244 * @flags: used to distinguish Linux/RT-Linux type
245 * @peers: for connection into list of object users
246 * @qends: pointer to the ends structure corresponding for this user
247 * @msgobj: communication object the user is connected to
248 * @rx_edge0: default receive queue for filter IOCTL
249 * @userinfo: stores user context specific information.
250 * The field @fileinfo.file holds pointer to open device file state structure
251 * for the Linux user-space client applications
252 * @magic: magic number to check consistency when pointer is retrieved
253 * from file private field
257 struct list_head peers;
258 struct canque_ends_t *qends;
259 struct msgobj_t *msgobj;
260 struct canque_edge_t *rx_edge0; /* simplifies IOCTL */
263 struct file *file; /* back ptr to file */
267 struct rtl_file *file;
269 #endif /*CAN_WITH_RTL*/
275 * struct hwspecops_t - hardware/board specific operations
276 * @request_io: reserve io or memory range for can board
277 * @release_io: free reserved io memory range
278 * @reset: hardware reset routine
279 * @init_hw_data: called to initialize &candevice_t structure, mainly
280 * @res_add, @nr_all_chips, @nr_82527_chips, @nr_sja1000_chips
282 * @init_chip_data: called initialize each &chip_t structure, mainly
283 * @chip_type, @chip_base_addr, @clock and chip specific registers.
284 * It is responsible to setup &chip_t->@chipspecops functions
285 * for non-standard chip types (type other than "i82527", "sja1000" or "sja1000p")
286 * @init_obj_data: called initialize each &msgobj_t structure,
287 * mainly @obj_base_addr field.
288 * @program_irq: program interrupt generation hardware of the board
289 * if flag %PROGRAMMABLE_IRQ is present for specified device/board
290 * @write_register: low level write register routine
291 * @read_register: low level read register routine
294 int (*request_io)(struct candevice_t *candev);
295 int (*release_io)(struct candevice_t *candev);
296 int (*reset)(struct candevice_t *candev);
297 int (*init_hw_data)(struct candevice_t *candev);
298 int (*init_chip_data)(struct candevice_t *candev, int chipnr);
299 int (*init_obj_data)(struct chip_t *chip, int objnr);
300 int (*program_irq)(struct candevice_t *candev);
301 void (*write_register)(unsigned char data,unsigned long address);
302 unsigned (*read_register)(unsigned long address);
306 * struct chipspecops_t - can controller chip specific operations
307 * @chip_config: CAN chip configuration
308 * @baud_rate: set communication parameters
309 * @standard_mask: setup of mask for message filtering
310 * @extended_mask: setup of extended mask for message filtering
311 * @message15_mask: set mask of i82527 message object 15
312 * @clear_objects: clears state of all message object residing in chip
313 * @config_irqs: tunes chip hardware interrupt delivery
314 * @pre_read_config: prepares message object for message reception
315 * @pre_write_config: prepares message object for message transmission
316 * @send_msg: initiate message transmission
317 * @remote_request: configures message object and asks for RTR message
318 * @check_tx_stat: checks state of transmission engine
319 * @wakeup_tx: wakeup TX processing
320 * @filtch_rq: optional routine for propagation of outgoing edges filters to HW
321 * @enable_configuration: enable chip configuration mode
322 * @disable_configuration: disable chip configuration mode
323 * @set_btregs: configures bitrate registers
324 * @start_chip: starts chip message processing
325 * @stop_chip: stops chip message processing
326 * @irq_handler: interrupt service routine
328 struct chipspecops_t {
329 int (*chip_config)(struct chip_t *chip);
330 int (*baud_rate)(struct chip_t *chip, int rate, int clock, int sjw,
331 int sampl_pt, int flags);
332 int (*standard_mask)(struct chip_t *chip, unsigned short code,
333 unsigned short mask);
334 int (*extended_mask)(struct chip_t *chip, unsigned long code,
336 int (*message15_mask)(struct chip_t *chip, unsigned long code,
338 int (*clear_objects)(struct chip_t *chip);
339 int (*config_irqs)(struct chip_t *chip, short irqs);
340 int (*pre_read_config)(struct chip_t *chip, struct msgobj_t *obj);
341 int (*pre_write_config)(struct chip_t *chip, struct msgobj_t *obj,
342 struct canmsg_t *msg);
343 int (*send_msg)(struct chip_t *chip, struct msgobj_t *obj,
344 struct canmsg_t *msg);
345 int (*remote_request)(struct chip_t *chip, struct msgobj_t *obj);
346 int (*check_tx_stat)(struct chip_t *chip);
347 int (*wakeup_tx)(struct chip_t *chip, struct msgobj_t *obj);
348 int (*filtch_rq)(struct chip_t *chip, struct msgobj_t *obj);
349 int (*enable_configuration)(struct chip_t *chip);
350 int (*disable_configuration)(struct chip_t *chip);
351 int (*set_btregs)(struct chip_t *chip, unsigned short btr0,
352 unsigned short btr1);
353 int (*start_chip)(struct chip_t *chip);
354 int (*stop_chip)(struct chip_t *chip);
355 can_irqreturn_t (*irq_handler)(int irq, void *dev_id, struct pt_regs *regs);
360 struct mem_addr *next;
364 /* Structure for the RTR queue */
367 struct canmsg_t *rtr_message;
368 wait_queue_head_t rtr_wq;
373 extern int minor[MAX_TOT_CHIPS];
375 extern int baudrate[MAX_TOT_CHIPS];
376 extern char *hw[MAX_HW_CARDS];
377 extern int irq[MAX_IRQ];
378 extern unsigned long io[MAX_HW_CARDS];
379 extern int processlocal;
381 extern struct canhardware_t *hardware_p;
382 extern struct chip_t *chips_p[MAX_TOT_CHIPS];
383 extern struct msgobj_t *objects_p[MAX_TOT_MSGOBJS];
385 extern struct mem_addr *mem_head;
388 #if defined(CONFIG_OC_LINCAN_PORTIO_ONLY)
389 extern inline void can_write_reg(const struct chip_t *chip, unsigned char data, unsigned address)
391 outb(data, chip->chip_base_addr+address);
393 extern inline unsigned can_read_reg(const struct chip_t *chip, unsigned address)
395 return inb(chip->chip_base_addr+address);
397 extern inline void canobj_write_reg(const struct chip_t *chip, const struct msgobj_t *obj,
398 unsigned char data, unsigned address)
400 outb(data, obj->obj_base_addr+address);
402 extern inline unsigned canobj_read_reg(const struct chip_t *chip, const struct msgobj_t *obj,
405 return inb(obj->obj_base_addr+address);
408 #elif defined(CONFIG_OC_LINCAN_MEMIO_ONLY)
409 extern inline void can_write_reg(const struct chip_t *chip, unsigned char data, unsigned address)
411 writeb(data, chip->chip_base_addr+address);
413 extern inline unsigned can_read_reg(const struct chip_t *chip, unsigned address)
415 return readb(chip->chip_base_addr+address);
417 extern inline void canobj_write_reg(const struct chip_t *chip, const struct msgobj_t *obj,
418 unsigned char data, unsigned address)
420 writeb(data, obj->obj_base_addr+address);
422 extern inline unsigned canobj_read_reg(const struct chip_t *chip, const struct msgobj_t *obj,
425 return readb(obj->obj_base_addr+address);
428 #else /*CONFIG_OC_LINCAN_DYNAMICIO*/
429 #ifndef CONFIG_OC_LINCAN_DYNAMICIO
430 #define CONFIG_OC_LINCAN_DYNAMICIO
433 /* Inline function to write to the hardware registers. The argument address is
434 * relative to the memory map of the chip and not the absolute memory address.
436 extern inline void can_write_reg(const struct chip_t *chip, unsigned char data, unsigned address)
438 unsigned long address_to_write;
439 address_to_write = chip->chip_base_addr+address;
440 chip->write_register(data, address_to_write);
443 extern inline unsigned can_read_reg(const struct chip_t *chip, unsigned address)
445 unsigned long address_to_read;
446 address_to_read = chip->chip_base_addr+address;
447 return chip->read_register(address_to_read);
450 extern inline void canobj_write_reg(const struct chip_t *chip, const struct msgobj_t *obj,
451 unsigned char data, unsigned address)
453 unsigned long address_to_write;
454 address_to_write = obj->obj_base_addr+address;
455 chip->write_register(data, address_to_write);
458 extern inline unsigned canobj_read_reg(const struct chip_t *chip, const struct msgobj_t *obj,
461 unsigned long address_to_read;
462 address_to_read = obj->obj_base_addr+address;
463 return chip->read_register(address_to_read);
466 #endif /*CONFIG_OC_LINCAN_DYNAMICIO*/
468 int can_base_addr_fixup(struct candevice_t *candev, unsigned long new_base);
469 int can_request_io_region(unsigned long start, unsigned long n, const char *name);
470 void can_release_io_region(unsigned long start, unsigned long n);
471 int can_request_mem_region(unsigned long start, unsigned long n, const char *name);
472 void can_release_mem_region(unsigned long start, unsigned long n);
475 const char *boardtype;
476 int (*board_register)(struct hwspecops_t *hwspecops);
480 const struct boardtype_t* boardtype_find(const char *str);
482 int can_check_dev_taken(void *anydev);
485 extern int can_rtl_priority;
486 #endif /*CAN_WITH_RTL*/