The first phase of integration of Hynix HMS30c7202 C_CAN support
[lincan.git] / lincan / src / i82527.c
1 /* i82527.c
2  * Linux CAN-bus device driver.
3  * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4  * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
5  * email:pisa@cmp.felk.cvut.cz
6  * This software is released under the GPL-License.
7  * Version lincan-0.2  9 Jul 2003
8  */
9
10 #include "../include/can.h"
11 #include "../include/can_sysdep.h"
12 #include "../include/main.h"
13 #include "../include/i82527.h"
14
15 void i82527_irq_rtr_handler(struct chip_t *chip, struct msgobj_t *obj, 
16                             struct rtr_id *rtr_search, unsigned long message_id);
17
18
19 extern int stdmask;
20 extern int extmask;
21 extern int mo15mask;
22
23 /* helper functions for segmented cards read and write configuration and status registers
24    above 0xf offset */
25
26 void i82527_seg_write_reg(const struct chip_t *chip, unsigned char data, unsigned address)
27 {
28         if((address > 0xf) && (chip->flags & CHIP_SEGMENTED))
29                 canobj_write_reg(chip, chip->msgobj[(address>>4)-1],data, address & 0xf);
30         else
31                 can_write_reg(chip, data, address);
32 }
33
34 unsigned i82527_seg_read_reg(const struct chip_t *chip, unsigned address)
35 {
36         if((address > 0xf) && (chip->flags & CHIP_SEGMENTED))
37                 return canobj_read_reg(chip, chip->msgobj[(address>>4)-1], address & 0xf);
38         else
39                 return can_read_reg(chip, address);
40 }
41
42 int i82527_enable_configuration(struct chip_t *chip)
43 {
44         unsigned short flags=0;
45
46         flags = can_read_reg(chip, iCTL) & (iCTL_IE|iCTL_SIE|iCTL_EIE);
47         can_write_reg(chip, flags|iCTL_CCE, iCTL);
48         
49         return 0;
50 }
51
52 int i82527_disable_configuration(struct chip_t *chip)
53 {
54         unsigned short flags=0;
55
56         flags = can_read_reg(chip, iCTL) & (iCTL_IE|iCTL_SIE|iCTL_EIE);
57         can_write_reg(chip, flags, iCTL);
58
59         return 0;
60 }
61
62 int i82527_chip_config(struct chip_t *chip)
63 {
64         can_write_reg(chip,chip->int_cpu_reg,iCPU); // Configure cpu interface
65         can_write_reg(chip,(iCTL_CCE|iCTL_INI),iCTL); // Enable configuration
66         i82527_seg_write_reg(chip,chip->int_clk_reg,iCLK); // Set clock out slew rates 
67         i82527_seg_write_reg(chip,chip->int_bus_reg,iBUS); /* Bus configuration */
68         can_write_reg(chip,0x00,iSTAT); /* Clear error status register */
69
70         /* Check if we can at least read back some arbitrary data from the 
71          * card. If we can not, the card is not properly configured!
72          */
73         canobj_write_reg(chip,chip->msgobj[1],0x25,iMSGDAT1);
74         canobj_write_reg(chip,chip->msgobj[2],0x52,iMSGDAT3);
75         canobj_write_reg(chip,chip->msgobj[10],0xc3,iMSGDAT6);
76         if ( (canobj_read_reg(chip,chip->msgobj[1],iMSGDAT1) != 0x25) ||
77               (canobj_read_reg(chip,chip->msgobj[2],iMSGDAT3) != 0x52) ||
78               (canobj_read_reg(chip,chip->msgobj[10],iMSGDAT6) != 0xc3) ) {
79                 CANMSG("Could not read back from the hardware.\n");
80                 CANMSG("This probably means that your hardware is not correctly configured!\n");
81                 return -1;
82         }
83         else
84                 DEBUGMSG("Could read back, hardware is probably configured correctly\n");
85
86         if (chip->baudrate == 0)
87                 chip->baudrate=1000000;
88
89         if (i82527_baud_rate(chip,chip->baudrate,chip->clock,0,75,0)) {
90                 CANMSG("Error configuring baud rate\n");
91                 return -ENODEV;
92         }
93         if (i82527_standard_mask(chip,0x0000,stdmask)) {
94                 CANMSG("Error configuring standard mask\n");
95                 return -ENODEV;
96         }
97         if (i82527_extended_mask(chip,0x00000000,extmask)) {
98                 CANMSG("Error configuring extended mask\n");
99                 return -ENODEV;
100         }
101         if (i82527_message15_mask(chip,0x00000000,mo15mask)) {
102                 CANMSG("Error configuring message 15 mask\n");
103                 return -ENODEV;
104         }
105         if (i82527_clear_objects(chip)) {
106                 CANMSG("Error clearing message objects\n");
107                 return -ENODEV;
108         }
109         if (i82527_config_irqs(chip,iCTL_IE|iCTL_EIE)) { /* has been 0x0a */
110                 CANMSG("Error configuring interrupts\n");
111                 return -ENODEV;
112         }
113
114         return 0;
115 }
116
117 /* Set communication parameters.
118  * param rate baud rate in Hz
119  * param clock frequency of i82527 clock in Hz (ISA osc is 14318000)
120  * param sjw synchronization jump width (0-3) prescaled clock cycles
121  * param sampl_pt sample point in % (0-100) sets (TSEG1+2)/(TSEG1+TSEG2+3) ratio
122  * param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP
123  */
124 int i82527_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,
125                                                         int sampl_pt, int flags)
126 {
127         int best_error = 1000000000, error;
128         int best_tseg=0, best_brp=0, best_rate=0, brp=0;
129         int tseg=0, tseg1=0, tseg2=0;
130         
131         if (i82527_enable_configuration(chip))
132                 return -ENODEV;
133
134         clock /=2;
135
136         /* tseg even = round down, odd = round up */
137         for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++) {
138                 brp = clock/((1+tseg/2)*rate)+tseg%2;
139                 if (brp == 0 || brp > 64)
140                         continue;
141                 error = rate - clock/(brp*(1+tseg/2));
142                 if (error < 0)
143                         error = -error;
144                 if (error <= best_error) {
145                         best_error = error;
146                         best_tseg = tseg/2;
147                         best_brp = brp-1;
148                         best_rate = clock/(brp*(1+tseg/2));
149                 }
150         }
151         if (best_error && (rate/best_error < 10)) {
152                 CANMSG("baud rate %d is not possible with %d Hz clock\n",
153                                                                 rate, 2*clock);
154                 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
155                                 best_rate, best_brp, best_tseg, tseg1, tseg2);
156                 return -EINVAL;
157         }
158         tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
159         if (tseg2 < 0)
160                 tseg2 = 0;
161         if (tseg2 > MAX_TSEG2)
162                 tseg2 = MAX_TSEG2;
163         
164         tseg1 = best_tseg-tseg2-2;
165         if (tseg1>MAX_TSEG1) {
166                 tseg1 = MAX_TSEG1;
167                 tseg2 = best_tseg-tseg1-2;
168         }
169
170         DEBUGMSG("Setting %d bps.\n", best_rate);
171         DEBUGMSG("brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
172                                         best_brp, best_tseg, tseg1, tseg2,
173                                         (100*(best_tseg-tseg2)/(best_tseg+1)));
174                                         
175                                 
176         i82527_seg_write_reg(chip, sjw<<6 | best_brp, iBT0);
177         can_write_reg(chip, ((flags & BTR1_SAM) != 0)<<7 | tseg2<<4 | tseg1,
178                                                                 iBT1);
179         DEBUGMSG("Writing 0x%x to iBT0\n",(sjw<<6 | best_brp));
180         DEBUGMSG("Writing 0x%x to iBT1\n",((flags & BTR1_SAM) != 0)<<7 | 
181                                                         tseg2<<4 | tseg1);
182
183         i82527_disable_configuration(chip);
184
185         return 0;
186 }
187
188 int i82527_standard_mask(struct chip_t *chip, unsigned short code, unsigned short mask)
189 {
190         unsigned char mask0, mask1;
191
192         mask0 = (unsigned char) (mask >> 3);
193         mask1 = (unsigned char) (mask << 5);
194         
195         can_write_reg(chip,mask0,iSGM0);
196         can_write_reg(chip,mask1,iSGM1);
197
198         DEBUGMSG("Setting standard mask to 0x%lx\n",(unsigned long)mask);
199
200         return 0;
201 }
202
203 int i82527_extended_mask(struct chip_t *chip, unsigned long code, unsigned long mask)
204 {
205         unsigned char mask0, mask1, mask2, mask3;
206
207         mask0 = (unsigned char) (mask >> 21);
208         mask1 = (unsigned char) (mask >> 13);
209         mask2 = (unsigned char) (mask >> 5);
210         mask3 = (unsigned char) (mask << 3);
211
212         can_write_reg(chip,mask0,iEGM0);
213         can_write_reg(chip,mask1,iEGM1);
214         can_write_reg(chip,mask2,iEGM2);
215         can_write_reg(chip,mask3,iEGM3);
216
217         DEBUGMSG("Setting extended mask to 0x%lx\n",(unsigned long)mask);
218
219         return 0;
220 }
221
222 int i82527_message15_mask(struct chip_t *chip, unsigned long code, unsigned long mask)
223 {
224         unsigned char mask0, mask1, mask2, mask3;
225
226         mask0 = (unsigned char) (mask >> 21);
227         mask1 = (unsigned char) (mask >> 13);
228         mask2 = (unsigned char) (mask >> 5);
229         mask3 = (unsigned char) (mask << 3);
230
231         can_write_reg(chip,mask0,i15M0);
232         can_write_reg(chip,mask1,i15M1);
233         can_write_reg(chip,mask2,i15M2);
234         can_write_reg(chip,mask3,i15M3);
235
236         DEBUGMSG("Setting message 15 mask to 0x%lx\n",mask);
237
238         return 0;
239
240
241 }
242
243 int i82527_clear_objects(struct chip_t *chip)
244 {
245         int i=0,id=0,data=0;
246         struct msgobj_t *obj;
247
248         DEBUGMSG("Cleared all message objects on chip\n");
249
250         for (i=1; i<=15; i++) {
251                 obj=chip->msgobj[i];
252                 canobj_write_reg(chip,obj,(INTPD_RES|RXIE_RES|TXIE_RES|MVAL_RES),iMSGCTL0);
253                 canobj_write_reg(chip,obj,(NEWD_RES|MLST_RES|TXRQ_RES|RMPD_RES), iMSGCTL1);
254                 for (data=0x07; data<0x0f; data++)
255                         canobj_write_reg(chip,obj,0x00,data);
256                 for (id=2; id<6; id++) {
257                         canobj_write_reg(chip,obj,0x00,id);
258                 }
259                 if (extended==0) {
260                         canobj_write_reg(chip,obj,0x00,iMSGCFG);
261                 }
262                 else {
263                         canobj_write_reg(chip,obj,MCFG_XTD,iMSGCFG);
264                 }
265         }
266         if (extended==0)
267                 DEBUGMSG("All message ID's set to standard\n");
268         else
269                 DEBUGMSG("All message ID's set to extended\n");
270         
271         return 0;
272 }
273
274 int i82527_config_irqs(struct chip_t *chip, short irqs)
275 {
276         can_write_reg(chip,irqs,iCTL);
277         DEBUGMSG("Configured hardware interrupt delivery\n");
278         return 0;
279 }
280
281 int i82527_pre_read_config(struct chip_t *chip, struct msgobj_t *obj)
282 {
283         unsigned long id=obj->rx_preconfig_id;
284
285         can_msgobj_set_fl(obj,RX_MODE);
286
287         if (extended || can_msgobj_test_fl(obj,RX_MODE_EXT)) {
288                 id<<=3;
289                 canobj_write_reg(chip,obj,id,iMSGID3);
290                 canobj_write_reg(chip,obj,id>>8,iMSGID2);
291                 canobj_write_reg(chip,obj,id>>16,iMSGID1);
292                 canobj_write_reg(chip,obj,id>>24,iMSGID0);
293                 canobj_write_reg(chip,obj,MCFG_XTD,iMSGCFG);
294         } else {
295                 id<<=5;
296                 canobj_write_reg(chip,obj,id,iMSGID1);
297                 canobj_write_reg(chip,obj,id>>8,iMSGID0);
298                 canobj_write_reg(chip,obj,0x00,iMSGCFG);
299         }
300
301         canobj_write_reg(chip,obj,(NEWD_RES|MLST_RES|TXRQ_RES|RMPD_RES), iMSGCTL1);
302         canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
303
304         DEBUGMSG("i82527_pre_read_config: configured obj at 0x%08lx\n",obj->obj_base_addr);
305
306         return 0;
307 }
308
309 int i82527_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
310                                                         struct canmsg_t *msg)
311 {
312         int i=0,id0=0,id1=0,id2=0,id3=0;
313         int len;
314         
315         len = msg->length;
316         if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
317
318         can_msgobj_clear_fl(obj,RX_MODE);
319
320         canobj_write_reg(chip,obj,(MVAL_SET|TXIE_SET|RXIE_RES|INTPD_RES),iMSGCTL0);
321         canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|CPUU_SET|NEWD_RES),iMSGCTL1);
322
323         if (extended || (msg->flags&MSG_EXT)) {
324                 canobj_write_reg(chip,obj,(len<<4)|(MCFG_DIR|MCFG_XTD),iMSGCFG);
325                 id0 = (unsigned char) (msg->id<<3);
326                 id1 = (unsigned char) (msg->id>>5);
327                 id2 = (unsigned char) (msg->id>>13);
328                 id3 = (unsigned char) (msg->id>>21);
329                 canobj_write_reg(chip,obj,id0,iMSGID3);
330                 canobj_write_reg(chip,obj,id1,iMSGID2);
331                 canobj_write_reg(chip,obj,id2,iMSGID1);
332                 canobj_write_reg(chip,obj,id3,iMSGID0);
333         }
334         else {
335                 canobj_write_reg(chip,obj,(len<<4)|MCFG_DIR,iMSGCFG);
336                 id1 = (unsigned char) (msg->id<<5);
337                 id0 = (unsigned char) (msg->id>>3);
338                 canobj_write_reg(chip,obj,id1,iMSGID1);
339                 canobj_write_reg(chip,obj,id0,iMSGID0);
340         }
341         canobj_write_reg(chip,obj,RMPD_UNC|TXRQ_UNC|CPUU_SET|NEWD_SET,iMSGCTL1);
342         for (i=0; i<len; i++) {
343                 canobj_write_reg(chip,obj,msg->data[i],iMSGDAT0+i);
344         }
345
346         return 0;
347 }
348
349 int i82527_send_msg(struct chip_t *chip, struct msgobj_t *obj,
350                                                         struct canmsg_t *msg)
351 {
352         canobj_write_reg(chip,obj,(MVAL_SET|TXIE_SET|RXIE_RES|INTPD_RES),iMSGCTL0);
353
354         if (msg->flags & MSG_RTR) {
355                 canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|CPUU_RES|NEWD_SET),iMSGCTL1);
356         }
357         else {
358                 canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_SET|CPUU_RES|NEWD_SET),iMSGCTL1);
359         }
360
361         return 0;
362 }
363
364 int i82527_check_tx_stat(struct chip_t *chip)
365 {
366         if (can_read_reg(chip,iSTAT) & iSTAT_TXOK) {
367                 can_write_reg(chip,0x0,iSTAT);
368                 return 0;
369         }
370         else {
371                 can_write_reg(chip,0x0,iSTAT);
372                 return 1;
373         }
374 }
375
376 int i82527_remote_request(struct chip_t *chip, struct msgobj_t *obj)
377 {
378         canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
379         canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_SET|MLST_RES|NEWD_RES),iMSGCTL1);
380         
381         return 0;
382 }
383
384 int i82527_set_btregs(struct chip_t *chip, unsigned short btr0,
385                                                         unsigned short btr1)
386 {
387         if (i82527_enable_configuration(chip))
388                 return -ENODEV;
389
390         i82527_seg_write_reg(chip, btr0, iBT0);
391         i82527_seg_write_reg(chip, btr1, iBT1);
392
393         i82527_disable_configuration(chip);
394
395         return 0;
396 }
397
398 int i82527_start_chip(struct chip_t *chip)
399 {
400         unsigned short flags = 0;
401
402         flags = can_read_reg(chip, iCTL) & (iCTL_IE|iCTL_SIE|iCTL_EIE);
403         can_write_reg(chip, flags, iCTL);
404         
405         return 0;
406 }
407
408 int i82527_stop_chip(struct chip_t *chip)
409 {
410         unsigned short flags = 0;
411
412         flags = can_read_reg(chip, iCTL) & (iCTL_IE|iCTL_SIE|iCTL_EIE);
413         can_write_reg(chip, flags|(iCTL_CCE|iCTL_INI), iCTL);
414
415         return 0;
416 }
417
418 static inline 
419 void i82527_irq_write_handler(struct chip_t *chip, struct msgobj_t *obj)
420 {
421         int cmd;
422
423         canobj_write_reg(chip,obj,(MVAL_RES|TXIE_RES|RXIE_RES|INTPD_RES),iMSGCTL0);
424
425         if(obj->tx_slot){
426                 /* Do local transmitted message distribution if enabled */
427                 if (processlocal){
428                         obj->tx_slot->msg.flags |= MSG_LOCAL;
429                         canque_filter_msg2edges(obj->qends, &obj->tx_slot->msg);
430                 }
431                 /* Free transmitted slot */
432                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
433                 obj->tx_slot=NULL;
434         }
435
436         cmd=canque_test_outslot(obj->qends, &obj->tx_qedge, &obj->tx_slot);
437         if(cmd<0)
438                 return;
439
440         if (chip->chipspecops->pre_write_config(chip, obj, &obj->tx_slot->msg)) {
441                 obj->ret = -1;
442                 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_PREP);
443                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
444                 obj->tx_slot=NULL;
445                 return;
446         }
447         if (chip->chipspecops->send_msg(chip, obj, &obj->tx_slot->msg)) {
448                 obj->ret = -1;
449                 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_SEND);
450                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
451                 obj->tx_slot=NULL;
452                 return;
453         }
454         return;
455 }
456
457 static inline
458 void i82527_irq_read_handler(struct chip_t *chip, struct msgobj_t *obj, int objnum)
459 {
460         int i;
461         unsigned long message_id;
462         int msgcfg, msgctl1;
463         
464         msgctl1=canobj_read_reg(chip,obj,iMSGCTL1);
465         if(msgctl1 & NEWD_RES)
466                 return;
467         
468         do {
469                 if(objnum != 14) {
470                         canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|MLST_UNC|NEWD_RES),iMSGCTL1);
471                         canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
472                 }
473
474                 msgcfg = canobj_read_reg(chip,obj,iMSGCFG);
475
476                 if (msgcfg&MCFG_XTD) {
477                         message_id =canobj_read_reg(chip,obj,iMSGID3);
478                         message_id|=canobj_read_reg(chip,obj,iMSGID2)<<8;
479                         message_id|=canobj_read_reg(chip,obj,iMSGID1)<<16;
480                         message_id|=canobj_read_reg(chip,obj,iMSGID0)<<24;
481                         message_id>>=3;
482                         obj->rx_msg.flags = MSG_EXT;
483
484                 }
485                 else {
486                         message_id =canobj_read_reg(chip,obj,iMSGID1);
487                         message_id|=canobj_read_reg(chip,obj,iMSGID0)<<8;
488                         message_id>>=5;
489                         obj->rx_msg.flags = 0;
490                 }
491
492                 obj->rx_msg.length = (msgcfg >> 4) & 0xf;
493                 if(obj->rx_msg.length > CAN_MSG_LENGTH) obj->rx_msg.length = CAN_MSG_LENGTH;
494
495                 obj->rx_msg.id = message_id;
496
497                 for (i=0; i < obj->rx_msg.length; i++)
498                         obj->rx_msg.data[i] = canobj_read_reg(chip,obj,iMSGDAT0+i);
499
500                 
501                 if(objnum != 14) {
502                         /* if NEWD is set after data read, then read data are likely inconsistent */
503                         msgctl1=canobj_read_reg(chip,obj,iMSGCTL1);
504                         if(msgctl1 & NEWD_SET) {
505                                 CANMSG("i82527_irq_read_handler: object %d data overwritten\n",objnum);
506                                 continue;
507                         }
508                 }
509                 else {
510                         /* this object is special and data are queued in the shadow register */
511                         canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
512                         canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|MLST_UNC|NEWD_RES),iMSGCTL1);
513                         msgctl1=canobj_read_reg(chip,obj,iMSGCTL1);
514                 }
515                 
516
517                 canque_filter_msg2edges(obj->qends, &obj->rx_msg);
518                 
519                 if (msgctl1 & NEWD_SET)
520                         continue;
521                 
522                 if (msgctl1 & MLST_SET) {
523                         canobj_write_reg(chip,obj,(RMPD_UNC|TXRQ_UNC|MLST_RES|NEWD_UNC),iMSGCTL1);
524                         CANMSG("i82527_irq_read_handler: object %d message lost\n",objnum);
525                 }
526                 
527                 return;
528
529         } while(1);
530 }
531
532 /*
533                         if (msgcfg&MCFG_XTD) {
534                                 message_id =canobj_read_reg(chip,obj,iMSGID3);
535                                 message_id|=canobj_read_reg(chip,obj,iMSGID2)<<8;
536                                 message_id|=canobj_read_reg(chip,obj,iMSGID1)<<16;
537                                 message_id|=canobj_read_reg(chip,obj,iMSGID0)<<24;
538                                 message_id>>=3;
539                         }
540                         else {
541                                 message_id =canobj_read_reg(chip,obj,iMSGID1);
542                                 message_id|=canobj_read_reg(chip,obj,iMSGID0)<<8;
543                                 message_id>>=5;
544                         }
545
546                         can_spin_lock(&hardware_p->rtr_lock);
547                         rtr_search=hardware_p->rtr_queue;
548                         while (rtr_search != NULL) {
549                                 if (rtr_search->id == message_id)
550                                         break;
551                                 rtr_search=rtr_search->next;
552                         }
553                         can_spin_unlock(&hardware_p->rtr_lock);
554                         if ((rtr_search!=NULL) && (rtr_search->id==message_id))
555                                 i82527_irq_rtr_handler(chip, obj, rtr_search, message_id);
556                         else
557                                 i82527_irq_read_handler(chip, obj, message_id); 
558 */
559
560
561 static inline 
562 void i82527_irq_update_filter(struct chip_t *chip, struct msgobj_t *obj)
563 {
564         struct canfilt_t filt;
565
566         if(canqueue_ends_filt_conjuction(obj->qends, &filt)) {
567                 obj->rx_preconfig_id=filt.id;
568                 canobj_write_reg(chip,obj,(MVAL_RES|TXIE_RES|RXIE_RES|INTPD_RES),iMSGCTL0);
569                 if(obj->object == 15) {
570                         i82527_message15_mask(chip,filt.id,filt.mask);
571                 }
572                 if (filt.flags&MSG_EXT)
573                         can_msgobj_set_fl(obj,RX_MODE_EXT);
574                 else
575                         can_msgobj_clear_fl(obj,RX_MODE_EXT);
576
577                 i82527_pre_read_config(chip, obj);
578
579                 CANMSG("i82527_irq_update_filter: obj at 0x%08lx\n",obj->obj_base_addr);
580         }
581 }
582
583
584 void i82527_irq_sync_activities(struct chip_t *chip, struct msgobj_t *obj)
585 {
586         while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)) {
587
588                 if(can_msgobj_test_and_clear_fl(obj,TX_REQUEST)) {
589                         if(canobj_read_reg(chip,obj,iMSGCTL1)&TXRQ_RES)
590                                 i82527_irq_write_handler(chip, obj);
591                 }
592
593                 if(!obj->tx_slot) {
594                         if(can_msgobj_test_and_clear_fl(obj,FILTCH_REQUEST)) {
595                                 i82527_irq_update_filter(chip, obj);
596                         }
597                 }
598
599                 can_msgobj_clear_fl(obj,TX_LOCK);
600                 if(can_msgobj_test_fl(obj,TX_REQUEST))
601                         continue;
602                 if(can_msgobj_test_fl(obj,FILTCH_REQUEST) && !obj->tx_slot)
603                         continue;
604                 break;
605         }
606 }
607
608 can_irqreturn_t i82527_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
609 {
610         unsigned char msgcfg;
611
612         unsigned irq_register;
613         unsigned object;
614         struct chip_t *chip=(struct chip_t *)dev_id;
615         struct msgobj_t *obj;
616
617         /*put_reg=device->hwspecops->write_register;*/
618         /*get_reg=device->hwspecops->read_register;*/
619
620         irq_register = i82527_seg_read_reg(chip, iIRQ);
621
622         if(!irq_register) {
623                 DEBUGMSG("i82527: spurious IRQ\n");
624                 return CAN_IRQ_NONE;
625         }
626
627
628         do {
629
630                 DEBUGMSG("i82527: iIRQ 0x%02x\n",irq_register);
631                 
632                 if (irq_register == 0x01) {
633                         DEBUGMSG("Status register: 0x%x\n",can_read_reg(chip, iSTAT));
634                         continue;
635                         /*return CAN_IRQ_NONE;*/
636                 }
637                 
638                 if (irq_register == 0x02)
639                         object = 14;
640                 else if(irq_register < 14)
641                         object = irq_register-3;
642                 else
643                         return CAN_IRQ_NONE;
644
645                 obj=chip->msgobj[object];
646                 
647                 msgcfg = canobj_read_reg(chip,obj,iMSGCFG);
648                 if (msgcfg & MCFG_DIR) {
649                         can_msgobj_set_fl(obj,TX_REQUEST);
650                         
651                         /* calls i82527_irq_write_handler synchronized with other invocations */
652                         i82527_irq_sync_activities(chip, obj);
653                 }
654                 else { 
655
656                         i82527_irq_read_handler(chip, obj, object); 
657                 }
658
659         } while((irq_register=i82527_seg_read_reg(chip, iIRQ)) != 0);
660
661         return CAN_IRQ_HANDLED;
662 }
663
664 void i82527_irq_rtr_handler(struct chip_t *chip, struct msgobj_t *obj,
665                             struct rtr_id *rtr_search, unsigned long message_id)
666 {
667         short int i=0;
668
669         canobj_write_reg(chip,obj,(MVAL_RES|TXIE_RES|RXIE_RES|INTPD_RES),iMSGCTL0);
670         canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|MLST_RES|NEWD_RES),iMSGCTL1);
671         
672         can_spin_lock(&hardware_p->rtr_lock);
673
674         rtr_search->rtr_message->id=message_id;
675         rtr_search->rtr_message->length=(canobj_read_reg(chip,obj,iMSGCFG) & 0xf0)>>4;
676         for (i=0; i<rtr_search->rtr_message->length; i++)
677                 rtr_search->rtr_message->data[i]=canobj_read_reg(chip,obj,iMSGDAT0+i);
678         
679         can_spin_unlock(&hardware_p->rtr_lock);
680
681         if (waitqueue_active(&rtr_search->rtr_wq))
682                 wake_up(&rtr_search->rtr_wq);
683 }
684
685 /**
686  * i82527_wakeup_tx: - wakeups TX processing
687  * @chip: pointer to chip state structure
688  * @obj: pointer to message object structure
689  *
690  * Function is responsible for initiating message transmition.
691  * It is responsible for clearing of object TX_REQUEST flag
692  *
693  * Return Value: negative value reports error.
694  * File: src/i82527.c
695  */
696 int i82527_wakeup_tx(struct chip_t *chip, struct msgobj_t *obj)
697 {
698         can_preempt_disable();
699         
700         can_msgobj_set_fl(obj,TX_REQUEST);
701
702         /* calls i82527_irq_write_handler synchronized with other invocations
703           from kernel and IRQ context */
704         i82527_irq_sync_activities(chip, obj);
705
706         can_preempt_enable();
707         return 0;
708 }
709
710 int i82527_filtch_rq(struct chip_t *chip, struct msgobj_t *obj)
711 {
712         can_preempt_disable();
713         
714         can_msgobj_set_fl(obj,FILTCH_REQUEST);
715
716         /* setups filter synchronized with other invocations from kernel and IRQ context */
717         i82527_irq_sync_activities(chip, obj);
718
719         can_preempt_enable();
720         return 0;
721 }
722
723 int i82527_register(struct chipspecops_t *chipspecops)
724 {
725         chipspecops->chip_config = i82527_chip_config;
726         chipspecops->baud_rate = i82527_baud_rate;
727         chipspecops->standard_mask = i82527_standard_mask;
728         chipspecops->extended_mask = i82527_extended_mask;
729         chipspecops->message15_mask = i82527_message15_mask;
730         chipspecops->clear_objects = i82527_clear_objects;
731         chipspecops->config_irqs = i82527_config_irqs;
732         chipspecops->pre_read_config = i82527_pre_read_config;
733         chipspecops->pre_write_config = i82527_pre_write_config;
734         chipspecops->send_msg = i82527_send_msg;
735         chipspecops->check_tx_stat = i82527_check_tx_stat;
736         chipspecops->wakeup_tx = i82527_wakeup_tx;
737         chipspecops->filtch_rq = i82527_filtch_rq;
738         chipspecops->remote_request = i82527_remote_request;
739         chipspecops->enable_configuration = i82527_enable_configuration;
740         chipspecops->disable_configuration = i82527_disable_configuration;
741         chipspecops->set_btregs = i82527_set_btregs;
742         chipspecops->start_chip = i82527_start_chip;
743         chipspecops->stop_chip = i82527_stop_chip;
744         chipspecops->irq_handler = i82527_irq_handler;
745         return 0;
746 }