1 /* ems_cpcpci.c - support for EMS-WUENSCHE CPC-PCI card
2 * Linux CAN-bus device driver.
3 * The card support added by Paolo Grisleri <grisleri@ce.unipr.it>
4 * This software is released under the GPL-License.
5 * Version lincan-0.3 17 Jun 2004
8 #include "../include/can.h"
9 #include "../include/can_sysdep.h"
10 #include "../include/main.h"
11 #include "../include/sja1000p.h"
13 #ifdef CAN_ENABLE_PCI_SUPPORT
16 /* the only one supported: EMS CPC-PCI */
17 // PGX: check identifiers name
18 # define EMS_CPCPCI_PCICAN_VENDOR 0x110a
19 # define EMS_CPCPCI_PCICAN_ID 0x2104
21 /*The Infineon PSB4610 PITA-2 is used as PCI to local bus bridge*/
22 /*BAR0 - MEM - bridge control registers*/
24 /*BAR1 - MEM - parallel interface*/
25 /* 0 more EMS control registers
26 * 0x400 the first SJA1000
27 * 0x600 the second SJA1000
28 * each register occupies 4 bytes
31 /*PSB4610 PITA-2 bridge control registers*/
32 #define PITA2_ICR 0x00 /* Interrupt Control Register */
33 #define PITA2_ICR_INT0 0x00000002 /* [RC] INT0 Active/Clear */
34 #define PITA2_ICR_INT0_En 0x00020000 /* [RW] Enable INT0 */
36 #define PITA2_MISC 0x1C /* Miscellaneous Register */
37 #define PITA2_MISC_CONFIG 0x04000000
38 /* Multiplexed Parallel_interface_mode */
40 #define EMS_CPCPCI_BYTES_PER_CIRCUIT 0x200
41 /* Each CPC register occupies 4 bytes */
42 #define EMS_CPCPCI_BYTES_PER_REG 0x4
44 // Standard value: Pushpull (OCTP1|OCTN1|OCTP0|OCTN0|OCM1)
45 #define EMS_CPCPCI_OCR_DEFAULT_STD 0xDA
46 // For Galathea piggyback.
47 #define EMS_CPCPCI_OCR_DEFAULT_GAL 0xDB
51 The board configuration is probably following:
52 " RX1 is connected to ground.
53 " TX1 is not connected.
54 " CLKO is not connected.
55 " Setting the OCR register to 0xDA is a good idea.
56 This means normal output mode , push-pull and the correct polarity.
57 " In the CDR register, you should set CBP to 1.
58 You will probably also want to set the clock divider value to 7
59 (meaning direct oscillator output) because the second SJA1000 chip
60 is driven by the first one CLKOUT output.
66 void ems_cpcpci_disconnect_irq(struct candevice_t *candev)
68 /* Disable interrupts from card */
69 writel(0, candev->dev_base_addr + PITA2_ICR);
72 void ems_cpcpci_connect_irq(struct candevice_t *candev)
74 /* Enable interrupts from card */
75 writel(PITA2_ICR_INT0_En, candev->dev_base_addr + PITA2_ICR);
79 int ems_cpcpci_request_io(struct candevice_t *candev)
81 unsigned long pita2_addr;
82 unsigned long io_addr;
85 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))
86 if(pci_request_region(candev->sysdevptr.pcidev, 0, "ems_cpcpci_pita2") != 0){
87 CANMSG("Request of ems_cpcpci_pita2 range failed\n");
89 }else if(pci_request_region(candev->sysdevptr.pcidev, 1, "ems_cpcpci_io") != 0){
90 CANMSG("Request of ems_cpcpci_io range failed\n");
93 #else /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
94 if(pci_request_regions(candev->sysdevptr.pcidev, "EMS_CPCPCI") != 0){
95 CANMSG("Request of ems_cpcpci_s5920 regions failed\n");
98 #endif /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
100 pita2_addr=pci_resource_start(candev->sysdevptr.pcidev,0);
101 if (!(candev->dev_base_addr = (long) ioremap(pita2_addr,
102 pci_resource_len(candev->sysdevptr.pcidev,0)))) {
103 CANMSG("Unable to access I/O memory at: 0x%lx\n", pita2_addr);
104 goto error_ioremap_pita2;
107 io_addr=pci_resource_start(candev->sysdevptr.pcidev,1);;
108 if (!(candev->io_addr = (long) ioremap(io_addr,
109 pci_resource_len(candev->sysdevptr.pcidev,1)))) {
110 CANMSG("Unable to access I/O memory at: 0x%lx\n", io_addr);
111 goto error_ioremap_io;
114 candev->res_addr=candev->io_addr;
117 * this is redundant with chip initialization, but remap address
118 * can change when resources are temporarily released
120 for(i=0;i<candev->nr_all_chips;i++) {
121 struct chip_t *chip=candev->chip[i];
123 chip->chip_base_addr = candev->io_addr+
124 0x400 + i*EMS_CPCPCI_BYTES_PER_CIRCUIT;
125 if(!chip->msgobj[0]) continue;
126 chip->msgobj[0]->obj_base_addr=chip->chip_base_addr;
129 /* Configure PITA-2 parallel interface */
130 writel(PITA2_MISC_CONFIG, candev->dev_base_addr + PITA2_MISC);
132 ems_cpcpci_disconnect_irq(candev);
137 iounmap((void*)candev->dev_base_addr);
139 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))
140 pci_release_region(candev->sysdevptr.pcidev, 1);
142 pci_release_region(candev->sysdevptr.pcidev, 0);
143 #else /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
144 pci_release_regions(candev->sysdevptr.pcidev);
145 #endif /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
150 int ems_cpcpci_release_io(struct candevice_t *candev)
152 ems_cpcpci_disconnect_irq(candev);
154 iounmap((void*)candev->io_addr);
155 iounmap((void*)candev->dev_base_addr);
156 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))
157 pci_release_region(candev->sysdevptr.pcidev, 1);
158 pci_release_region(candev->sysdevptr.pcidev, 0);
159 #else /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
160 pci_release_regions(candev->sysdevptr.pcidev);
161 #endif /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
167 void ems_cpcpci_write_register(unsigned data, unsigned long address)
169 address += ((address&(EMS_CPCPCI_BYTES_PER_CIRCUIT-1))
170 *(EMS_CPCPCI_BYTES_PER_REG-1));
171 writeb(data,address);
174 unsigned ems_cpcpci_read_register(unsigned long address)
176 address += ((address&(EMS_CPCPCI_BYTES_PER_CIRCUIT-1))
177 *(EMS_CPCPCI_BYTES_PER_REG-1));
178 return readb(address);
181 extern can_irqreturn_t sja1000p_irq_handler(int irq, void *dev_id, struct pt_regs *regs);
183 can_irqreturn_t ems_cpcpci_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
185 struct chip_t *chip=(struct chip_t *)dev_id;
186 struct candevice_t *candev=chip->hostdevice;
190 icr=readl(candev->dev_base_addr + PITA2_ICR);
191 if(!(icr & PITA2_ICR_INT0)) return IRQ_NONE;
193 /* correct way to handle interrupts from all chips connected to the one PITA-2 */
195 writel(PITA2_ICR_INT0_En | PITA2_ICR_INT0, candev->dev_base_addr + PITA2_ICR);
196 for(i=0;i<candev->nr_all_chips;i++){
197 chip=candev->chip[i];
198 if(!chip || !(chip->flags&CHIP_CONFIGURED))
200 sja1000p_irq_handler(irq, dev_id, regs);
202 icr=readl(candev->dev_base_addr + PITA2_ICR);
203 } while(icr & PITA2_ICR_INT0);
207 int ems_cpcpci_reset(struct candevice_t *candev)
213 DEBUGMSG("Resetting EMS_CPCPCI hardware ...\n");
215 /* Assert PTADR# - we're in passive mode so the other bits are not important */
217 ems_cpcpci_disconnect_irq(candev);
219 for(chip_nr=0;chip_nr<candev->nr_all_chips;chip_nr++){
220 if(!candev->chip[chip_nr]) continue;
221 chip=candev->chip[chip_nr];
223 ems_cpcpci_write_register(sjaMOD_RM, chip->chip_base_addr+SJAMOD);
226 cdr=ems_cpcpci_read_register(chip->chip_base_addr+SJACDR);
227 ems_cpcpci_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
229 ems_cpcpci_write_register(0, chip->chip_base_addr+SJAIER);
232 ems_cpcpci_write_register(0, chip->chip_base_addr+SJAMOD);
233 while (ems_cpcpci_read_register(chip->chip_base_addr+SJAMOD)&sjaMOD_RM){
234 if(!i--) return -ENODEV;
236 ems_cpcpci_write_register(0, chip->chip_base_addr+SJAMOD);
239 cdr=ems_cpcpci_read_register(chip->chip_base_addr+SJACDR);
240 ems_cpcpci_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
242 ems_cpcpci_write_register(0, chip->chip_base_addr+SJAIER);
244 ems_cpcpci_read_register(chip->chip_base_addr+SJAIR);
248 ems_cpcpci_connect_irq(candev);
253 int ems_cpcpci_init_hw_data(struct candevice_t *candev)
255 struct pci_dev *pcidev = NULL;
259 pcidev = pci_find_device(EMS_CPCPCI_PCICAN_VENDOR, EMS_CPCPCI_PCICAN_ID, pcidev);
260 if(pcidev == NULL) return -ENODEV;
262 if (pci_enable_device (pcidev)){
263 printk(KERN_CRIT "Setup of EMS_CPCPCI failed\n");
266 candev->sysdevptr.pcidev=pcidev;
269 if(!(pci_resource_flags(pcidev,0)&IORESOURCE_MEM)){
270 printk(KERN_CRIT "EMS_CPCPCI region %d is not memory\n",i);
275 /*request IO access temporarily to check card presence*/
276 if(ems_cpcpci_request_io(candev)<0)
279 /*** candev->dev_base_addr=pci_resource_start(pcidev,0); ***/
280 /* some control registers */
281 /*** candev->io_addr=pci_resource_start(pcidev,1); ***/
282 /* 0 more EMS control registers
283 * 0x400 the first SJA1000
284 * 0x600 the second SJA1000
285 * each register occupies 4 bytes
288 /*candev->flags |= CANDEV_PROGRAMMABLE_IRQ;*/
290 for(l=0,i=0;i<4;i++){
292 l|=readb(candev->io_addr + i*4);
294 i=readb(candev->io_addr + i*5);
296 CANMSG("EMS CPC-PCI check value %04lx, ID %d\n", l, i);
298 if((l!=0x55aa01cb)||(i!=0x11)) {
299 CANMSG("EMS CPC-PCI unexpected check values\n");
302 /*if (!strcmp(candev->hwname,"ems_cpcpci"))*/
303 candev->nr_82527_chips=0;
304 candev->nr_sja1000_chips=2;
305 candev->nr_all_chips=2;
307 ems_cpcpci_release_io(candev);
312 int ems_cpcpci_init_chip_data(struct candevice_t *candev, int chipnr)
314 if(candev->sysdevptr.pcidev==NULL)
317 /* initialize common routines for the SJA1000 chip */
318 sja1000p_fill_chipspecops(candev->chip[chipnr]);
320 /* special version of the IRQ handler is required for CPC-PCI board */
321 candev->chip[chipnr]->chipspecops->irq_handler=ems_cpcpci_irq_handler;
323 candev->chip[chipnr]->chip_irq=candev->sysdevptr.pcidev->irq;
325 candev->chip[chipnr]->chip_base_addr = candev->io_addr+
326 0x400 + chipnr*EMS_CPCPCI_BYTES_PER_CIRCUIT;
327 candev->chip[chipnr]->flags = 0;
328 candev->chip[chipnr]->int_cpu_reg = 0;
329 candev->chip[chipnr]->int_clk_reg = 0;
330 candev->chip[chipnr]->int_bus_reg = 0;
331 /* CLKOUT has to be equal to oscillator frequency to drive second chip */
332 candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | 7;
333 candev->chip[chipnr]->sja_ocr_reg = EMS_CPCPCI_OCR_DEFAULT_STD;
334 candev->chip[chipnr]->clock = 16000000;
335 candev->chip[chipnr]->flags |= CHIP_IRQ_PCI;
340 int ems_cpcpci_init_obj_data(struct chip_t *chip, int objnr)
342 chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr;
346 int ems_cpcpci_program_irq(struct candevice_t *candev)
352 int ems_cpcpci_register(struct hwspecops_t *hwspecops)
354 hwspecops->request_io = ems_cpcpci_request_io;
355 hwspecops->release_io = ems_cpcpci_release_io;
356 hwspecops->reset = ems_cpcpci_reset;
357 hwspecops->init_hw_data = ems_cpcpci_init_hw_data;
358 hwspecops->init_chip_data = ems_cpcpci_init_chip_data;
359 hwspecops->init_obj_data = ems_cpcpci_init_obj_data;
360 hwspecops->write_register = ems_cpcpci_write_register;
361 hwspecops->read_register = ems_cpcpci_read_register;
362 hwspecops->program_irq = ems_cpcpci_program_irq;
367 #endif /*CAN_ENABLE_PCI_SUPPORT*/