1 /**************************************************************************/
2 /* File: sja1000.c - Philips/NXP SJA1000 chip legacy mode (deprecated) */
4 /* LinCAN - (Not only) Linux CAN bus driver */
5 /* Copyright (C) 2002-2009 DCE FEE CTU Prague <http://dce.felk.cvut.cz> */
6 /* Copyright (C) 2002-2009 Pavel Pisa <pisa@cmp.felk.cvut.cz> */
7 /* Funded by OCERA and FRESCOR IST projects */
8 /* Based on CAN driver code by Arnaud Westenberg <arnaud@wanadoo.nl> */
10 /* LinCAN is free software; you can redistribute it and/or modify it */
11 /* under terms of the GNU General Public License as published by the */
12 /* Free Software Foundation; either version 2, or (at your option) any */
13 /* later version. LinCAN is distributed in the hope that it will be */
14 /* useful, but WITHOUT ANY WARRANTY; without even the implied warranty */
15 /* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */
16 /* General Public License for more details. You should have received a */
17 /* copy of the GNU General Public License along with LinCAN; see file */
18 /* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, */
19 /* Cambridge, MA 02139, USA. */
21 /* To allow use of LinCAN in the compact embedded systems firmware */
22 /* and RT-executives (RTEMS for example), main authors agree with next */
23 /* special exception: */
25 /* Including LinCAN header files in a file, instantiating LinCAN generics */
26 /* or templates, or linking other files with LinCAN objects to produce */
27 /* an application image/executable, does not by itself cause the */
28 /* resulting application image/executable to be covered by */
29 /* the GNU General Public License. */
30 /* This exception does not however invalidate any other reasons */
31 /* why the executable file might be covered by the GNU Public License. */
32 /* Publication of enhanced or derived LinCAN files is required although. */
33 /**************************************************************************/
35 #include "../include/can.h"
36 #include "../include/can_sysdep.h"
37 #include "../include/main.h"
38 #include "../include/sja1000.h"
40 void sja1000_irq_read_handler(struct canchip_t *chip, struct msgobj_t *obj);
41 void sja1000_irq_write_handler(struct canchip_t *chip, struct msgobj_t *obj);
43 int sja1000_enable_configuration(struct canchip_t *chip)
48 can_disable_irq(chip->chip_irq);
50 flags=can_read_reg(chip,SJACR);
52 while ((!(flags & sjaCR_RR)) && (i<=10)) {
53 can_write_reg(chip,flags|sjaCR_RR,SJACR);
56 flags=can_read_reg(chip,SJACR);
59 CANMSG("Reset error\n");
60 can_enable_irq(chip->chip_irq);
67 int sja1000_disable_configuration(struct canchip_t *chip)
72 flags=can_read_reg(chip,SJACR);
74 while ( (flags & sjaCR_RR) && (i<=10) ) {
75 can_write_reg(chip,flags & (sjaCR_RIE|sjaCR_TIE|sjaCR_EIE|sjaCR_OIE),SJACR);
78 flags=can_read_reg(chip,SJACR);
81 CANMSG("Error leaving reset status\n");
85 can_enable_irq(chip->chip_irq);
90 int sja1000_chip_config(struct canchip_t *chip)
92 if (sja1000_enable_configuration(chip))
95 /* Set mode, clock out, comparator */
96 can_write_reg(chip,chip->sja_cdr_reg,SJACDR);
97 /* Set driver output configuration */
98 can_write_reg(chip,chip->sja_ocr_reg,SJAOCR);
100 if (sja1000_standard_mask(chip,0x0000, 0xffff))
104 chip->baudrate=1000000;
105 if (sja1000_baud_rate(chip,chip->baudrate,chip->clock,0,75,0))
108 /* Enable hardware interrupts */
109 can_write_reg(chip,(sjaCR_RIE|sjaCR_TIE|sjaCR_EIE|sjaCR_OIE),SJACR);
111 sja1000_disable_configuration(chip);
116 int sja1000_standard_mask(struct canchip_t *chip, unsigned short code, unsigned short mask)
118 unsigned char write_code, write_mask;
120 if (sja1000_enable_configuration(chip))
123 /* The acceptance code bits (SJAACR bits 0-7) and the eight most
124 * significant bits of the message identifier (id.10 to id.3) must be
125 * equal to those bit positions which are marked relevant by the
126 * acceptance mask bits (SJAAMR bits 0-7).
127 * (id.10 to id.3) = (SJAACR.7 to SJAACR.0) v (SJAAMR.7 to SJAAMR.0)
128 * (Taken from Philips sja1000 Data Sheet)
130 write_code = (unsigned char) code >> 3;
131 write_mask = (unsigned char) mask >> 3;
133 can_write_reg(chip,write_code,SJAACR);
134 can_write_reg(chip,write_mask,SJAAMR);
136 DEBUGMSG("Setting acceptance code to 0x%lx\n",(unsigned long)code);
137 DEBUGMSG("Setting acceptance mask to 0x%lx\n",(unsigned long)mask);
139 sja1000_disable_configuration(chip);
144 /* Set communication parameters.
145 * param rate baud rate in Hz
146 * param clock frequency of sja1000 clock in Hz (ISA osc is 14318000)
147 * param sjw synchronization jump width (0-3) prescaled clock cycles
148 * param sampl_pt sample point in % (0-100) sets (TSEG1+2)/(TSEG1+TSEG2+3) ratio
149 * param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP
151 int sja1000_baud_rate(struct canchip_t *chip, int rate, int clock, int sjw,
152 int sampl_pt, int flags)
154 int best_error = 1000000000, error;
155 int best_tseg=0, best_brp=0, best_rate=0, brp=0;
156 int tseg=0, tseg1=0, tseg2=0;
158 if (sja1000_enable_configuration(chip))
163 /* tseg even = round down, odd = round up */
164 for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++) {
165 brp = clock/((1+tseg/2)*rate)+tseg%2;
166 if (brp == 0 || brp > 64)
168 error = rate - clock/(brp*(1+tseg/2));
171 if (error <= best_error) {
175 best_rate = clock/(brp*(1+tseg/2));
178 if (best_error && (rate/best_error < 10)) {
179 CANMSG("baud rate %d is not possible with %d Hz clock\n",
181 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
182 best_rate, best_brp, best_tseg, tseg1, tseg2);
185 tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
188 if (tseg2 > MAX_TSEG2)
190 tseg1 = best_tseg-tseg2-2;
191 if (tseg1 > MAX_TSEG1) {
193 tseg2 = best_tseg-tseg1-2;
196 DEBUGMSG("Setting %d bps.\n", best_rate);
197 DEBUGMSG("brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
198 best_brp, best_tseg, tseg1, tseg2,
199 (100*(best_tseg-tseg2)/(best_tseg+1)));
202 can_write_reg(chip, sjw<<6 | best_brp, SJABTR0);
203 can_write_reg(chip, ((flags & BTR1_SAM) != 0)<<7 | tseg2<<4 | tseg1,
205 // can_write_reg(chip, sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH | sjaOCR_TX1_ZZ, SJAOCR);
206 /* BASIC mode, bypass input comparator */
207 // can_write_reg(chip, sjaCDR_CBP| /* sjaCDR_CLK_OFF | */ 7, SJACDR);
209 sja1000_disable_configuration(chip);
214 int sja1000_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj)
218 i=can_read_reg(chip,SJASR);
220 if (!(i&sjaSR_RBS)) {
222 for (i=0; i<0x20; i++)
223 CANMSG("0x%x is 0x%x\n",i,can_read_reg(chip,i));
226 sja1000_start_chip(chip);
228 // disable interrupts for a moment
229 can_write_reg(chip, 0, SJACR);
231 sja1000_irq_read_handler(chip, obj);
234 can_write_reg(chip, sjaCR_OIE | sjaCR_EIE | sjaCR_TIE | sjaCR_RIE, SJACR);
240 #define MAX_TRANSMIT_WAIT_LOOPS 10
242 int sja1000_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
243 struct canmsg_t *msg)
248 sja1000_start_chip(chip); //sja1000 goes automatically into reset mode on errors
250 /* Wait until Transmit Buffer Status is released */
251 while ( !(can_read_reg(chip, SJASR) & sjaSR_TBS) &&
252 i++<MAX_TRANSMIT_WAIT_LOOPS) {
256 if (!(can_read_reg(chip, SJASR) & sjaSR_TBS)) {
257 CANMSG("Transmit timed out, cancelling\n");
258 can_write_reg(chip, sjaCMR_AT, SJACMR);
260 while ( !(can_read_reg(chip, SJASR) & sjaSR_TBS) &&
261 i++<MAX_TRANSMIT_WAIT_LOOPS) {
264 if (!(can_read_reg(chip, SJASR) & sjaSR_TBS)) {
265 CANMSG("Could not cancel, please reset\n");
271 if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
272 id = (msg->id<<5) | ((msg->flags&MSG_RTR)?sjaID0_RTR:0) | len;
274 can_write_reg(chip, id>>8, SJATXID1);
275 can_write_reg(chip, id & 0xff , SJATXID0);
277 for (i=0; i<len; i++)
278 can_write_reg(chip, msg->data[i], SJATXDAT0+i);
283 int sja1000_send_msg(struct canchip_t *chip, struct msgobj_t *obj,
284 struct canmsg_t *msg)
286 can_write_reg(chip, sjaCMR_TR, SJACMR);
291 int sja1000_check_tx_stat(struct canchip_t *chip)
293 if (can_read_reg(chip,SJASR) & sjaSR_TCS)
299 int sja1000_set_btregs(struct canchip_t *chip, unsigned short btr0,
302 if (sja1000_enable_configuration(chip))
305 can_write_reg(chip, btr0, SJABTR0);
306 can_write_reg(chip, btr1, SJABTR1);
308 sja1000_disable_configuration(chip);
313 int sja1000_start_chip(struct canchip_t *chip)
315 unsigned short flags = 0;
317 flags = can_read_reg(chip, SJACR) & (sjaCR_RIE|sjaCR_TIE|sjaCR_EIE|sjaCR_OIE);
318 can_write_reg(chip, flags, SJACR);
323 int sja1000_stop_chip(struct canchip_t *chip)
325 unsigned short flags = 0;
327 flags = can_read_reg(chip, SJACR) & (sjaCR_RIE|sjaCR_TIE|sjaCR_EIE|sjaCR_OIE);
328 can_write_reg(chip, flags|sjaCR_RR, SJACR);
333 int sja1000_attach_to_chip(struct canchip_t *chip)
338 int sja1000_release_chip(struct canchip_t *chip)
340 sja1000_stop_chip(chip);
341 can_write_reg(chip,sjaCR_RR,SJACR);
346 int sja1000_remote_request(struct canchip_t *chip, struct msgobj_t *obj)
348 CANMSG("sja1000_remote_request not implemented\n");
352 int sja1000_extended_mask(struct canchip_t *chip, unsigned long code,
355 CANMSG("sja1000_extended_mask not implemented\n");
359 int sja1000_clear_objects(struct canchip_t *chip)
361 CANMSG("sja1000_clear_objects not implemented\n");
365 int sja1000_config_irqs(struct canchip_t *chip, short irqs)
367 CANMSG("sja1000_config_irqs not implemented\n");
372 int sja1000_irq_handler(int irq, struct canchip_t *chip)
374 unsigned irq_register;
375 struct msgobj_t *obj=chip->msgobj[0];
376 int loop_cnt=CHIP_MAX_IRQLOOP;
378 irq_register=can_read_reg(chip, SJAIR);
379 // DEBUGMSG("sja1000_irq_handler: SJAIR:%02x\n",irq_register);
380 // DEBUGMSG("sja1000_irq_handler: SJASR:%02x\n",
381 // can_read_reg(chip, SJASR));
383 if ((irq_register & (sjaIR_WUI|sjaIR_DOI|sjaIR_EI|sjaIR_TI|sjaIR_RI)) == 0)
384 return CANCHIP_IRQ_NONE;
389 CANMSG("sja1000_irq_handler IRQ %d stuck\n",irq);
390 return CANCHIP_IRQ_STUCK;
393 if ((irq_register & sjaIR_RI) != 0)
394 sja1000_irq_read_handler(chip, obj);
396 if ((irq_register & sjaIR_TI) != 0) {
397 can_msgobj_set_fl(obj,TX_REQUEST);
398 while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
399 can_msgobj_clear_fl(obj,TX_REQUEST);
401 if (can_read_reg(chip, SJASR) & sjaSR_TBS)
402 sja1000_irq_write_handler(chip, obj);
404 can_msgobj_clear_fl(obj,TX_LOCK);
405 if(!can_msgobj_test_fl(obj,TX_REQUEST)) break;
409 if ((irq_register & (sjaIR_EI|sjaIR_DOI)) != 0) {
410 // Some error happened
411 // FIXME: chip should be brought to usable state. Transmission cancelled if in progress.
412 // Reset flag set to 0 if chip is already off the bus. Full state report
413 CANMSG("Error: status register: 0x%x irq_register: 0x%02x\n",
414 can_read_reg(chip, SJASR), irq_register);
418 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_BUS);
419 /*canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
424 irq_register=can_read_reg(chip, SJAIR);
426 } while(irq_register & (sjaIR_WUI|sjaIR_DOI|sjaIR_EI|sjaIR_TI|sjaIR_RI));
428 return CANCHIP_IRQ_HANDLED;
431 void sja1000_irq_read_handler(struct canchip_t *chip, struct msgobj_t *obj)
436 id = can_read_reg(chip, SJARXID0) | (can_read_reg(chip, SJARXID1)<<8);
437 obj->rx_msg.length = len = id & 0x0f;
438 obj->rx_msg.flags = id&sjaID0_RTR ? MSG_RTR : 0;
440 obj->rx_msg.id = id>>5;
442 if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
443 for (i=0; i<len; i++)
444 obj->rx_msg.data[i]=can_read_reg(chip, SJARXDAT0 + i);
446 can_write_reg(chip, sjaCMR_RRB, SJACMR);
448 /* fill CAN message timestamp */
449 can_filltimestamp(&obj->rx_msg.timestamp);
451 canque_filter_msg2edges(obj->qends, &obj->rx_msg);
452 } while(can_read_reg(chip, SJASR) & sjaSR_RBS);
455 void sja1000_irq_write_handler(struct canchip_t *chip, struct msgobj_t *obj)
460 /* Do local transmitted message distribution if enabled */
462 /* fill CAN message timestamp */
463 can_filltimestamp(&obj->tx_slot->msg.timestamp);
465 obj->tx_slot->msg.flags |= MSG_LOCAL;
466 canque_filter_msg2edges(obj->qends, &obj->tx_slot->msg);
468 /* Free transmitted slot */
469 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
473 cmd=canque_test_outslot(obj->qends, &obj->tx_qedge, &obj->tx_slot);
477 if (chip->chipspecops->pre_write_config(chip, obj, &obj->tx_slot->msg)) {
479 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_PREP);
480 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
484 if (chip->chipspecops->send_msg(chip, obj, &obj->tx_slot->msg)) {
486 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_SEND);
487 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
494 * sja1000_wakeup_tx: - wakeups TX processing
495 * @chip: pointer to chip state structure
496 * @obj: pointer to message object structure
498 * Return Value: negative value reports error.
499 * File: src/sja1000.c
501 int sja1000_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj)
503 can_preempt_disable();
505 can_msgobj_set_fl(obj,TX_REQUEST);
506 while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
507 can_msgobj_clear_fl(obj,TX_REQUEST);
509 if (can_read_reg(chip, SJASR) & sjaSR_TBS)
510 sja1000_irq_write_handler(chip, obj);
512 can_msgobj_clear_fl(obj,TX_LOCK);
513 if(!can_msgobj_test_fl(obj,TX_REQUEST)) break;
516 can_preempt_enable();
520 int sja1000_register(struct chipspecops_t *chipspecops)
522 chipspecops->chip_config = sja1000_chip_config;
523 chipspecops->baud_rate = sja1000_baud_rate;
524 chipspecops->standard_mask = sja1000_standard_mask;
525 chipspecops->extended_mask = sja1000_extended_mask;
526 chipspecops->message15_mask = sja1000_extended_mask;
527 chipspecops->clear_objects = sja1000_clear_objects;
528 chipspecops->config_irqs = sja1000_config_irqs;
529 chipspecops->pre_read_config = sja1000_pre_read_config;
530 chipspecops->pre_write_config = sja1000_pre_write_config;
531 chipspecops->send_msg = sja1000_send_msg;
532 chipspecops->check_tx_stat = sja1000_check_tx_stat;
533 chipspecops->wakeup_tx=sja1000_wakeup_tx;
534 chipspecops->remote_request = sja1000_remote_request;
535 chipspecops->enable_configuration = sja1000_enable_configuration;
536 chipspecops->disable_configuration = sja1000_disable_configuration;
537 chipspecops->set_btregs = sja1000_set_btregs;
538 chipspecops->attach_to_chip=sja1000_attach_to_chip;
539 chipspecops->release_chip=sja1000_release_chip;
540 chipspecops->start_chip = sja1000_start_chip;
541 chipspecops->stop_chip = sja1000_stop_chip;
542 chipspecops->irq_handler = sja1000_irq_handler;
543 chipspecops->irq_accept = NULL;
547 int sja1000_fill_chipspecops(struct canchip_t *chip)
549 chip->chip_type="sja1000";
551 sja1000_register(chip->chipspecops);