1 /**************************************************************************/
2 /* File: mscan.c - Freescale MPC5200 MSCAN controller support */
4 /* LinCAN - (Not only) Linux CAN bus driver */
5 /* Copyright (C) 2002-2009 DCE FEE CTU Prague <http://dce.felk.cvut.cz> */
6 /* Copyright (C) 2002-2009 Pavel Pisa <pisa@cmp.felk.cvut.cz> */
7 /* Copyright (C) 2007-2008 Martin Petera <peterm4@fel.cvut.cz> */
8 /* Funded by OCERA and FRESCOR IST projects */
9 /* Based on CAN driver code by Arnaud Westenberg <arnaud@wanadoo.nl> */
11 /* LinCAN is free software; you can redistribute it and/or modify it */
12 /* under terms of the GNU General Public License as published by the */
13 /* Free Software Foundation; either version 2, or (at your option) any */
14 /* later version. LinCAN is distributed in the hope that it will be */
15 /* useful, but WITHOUT ANY WARRANTY; without even the implied warranty */
16 /* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */
17 /* General Public License for more details. You should have received a */
18 /* copy of the GNU General Public License along with LinCAN; see file */
19 /* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, */
20 /* Cambridge, MA 02139, USA. */
22 /* To allow use of LinCAN in the compact embedded systems firmware */
23 /* and RT-executives (RTEMS for example), main authors agree with next */
24 /* special exception: */
26 /* Including LinCAN header files in a file, instantiating LinCAN generics */
27 /* or templates, or linking other files with LinCAN objects to produce */
28 /* an application image/executable, does not by itself cause the */
29 /* resulting application image/executable to be covered by */
30 /* the GNU General Public License. */
31 /* This exception does not however invalidate any other reasons */
32 /* why the executable file might be covered by the GNU Public License. */
33 /* Publication of enhanced or derived LinCAN files is required although. */
34 /**************************************************************************/
36 #include "../include/can.h"
37 #include "../include/can_sysdep.h"
38 #include "../include/main.h"
39 #include "../include/mscan.h"
40 #include "../include/mpc5200.h"
42 #define myDEBUG 1 /* enable debug for MPC5200 with MSCAN only */
45 #define DEBUGMSG(fmt,args...) can_printk(KERN_ERR "lincan (debug): " fmt,##args)
49 #define MSCAN_MAX_TRANSMIT_WAIT_LOOPS 20
50 #define MSCAN_MAX_SETTING_WAIT_LOOPS 25 /* maximal loop count while checking Chip reply to action */
51 #define MSCAN_MAX_IRQ_WAIT_LOOPS 25
54 void mscan_irq_read_handler(struct canchip_t *chip, struct msgobj_t *obj);
55 void mscan_irq_write_handler(struct canchip_t *chip, struct msgobj_t *obj);
57 int mscan_clear_irq_flags(struct canchip_t *chip);
58 void mscan_setup_ctrl_regs(struct canmsg_t * msg, uint16_t * ctrl0, uint16_t * ctrl1, uint16_t * ctrl2);
60 void mscan_msg_from_rxbuffer(struct canchip_t * chip, struct canmsg_t * msg);
61 void mscan_setup_txbuffer(struct canchip_t * chip, struct canmsg_t * msg, int buffer);
63 void mscan_notifyRXends(struct msgobj_t * obj, int what);
64 int mscan_check_txbuff_stat(struct canchip_t *chip, int buffer);
66 static int mscan_update_samplept(int sampl_pt, int tseg, int *tseg1, int *tseg2);
68 static int mscan_init_mode_active(struct canchip_t *chip);
69 static int mscan_sleep_mode_active(struct canchip_t *chip);
71 static reg_t mscan_get_flags(struct canchip_t * chip, reg_t flags, unsigned reg_addr);
72 static void mscan_set_flags(struct canchip_t * chip, reg_t flags, unsigned reg_addr);
73 static void mscan_clear_flags(struct canchip_t * chip, reg_t flags, unsigned reg_addr);
75 static void mscan_clear_buffer(struct canchip_t * chip, unsigned start_addr);
77 /* Enable folowing IRQs
78 * MSCAN_TIER_TXE - Transmit Empty Interrupt
79 * MSCAN_RIER_RXFIE - Receive Buffer Full
80 * MSCAN_RIER_OVRIE - Overrun
81 * MSCAN_RIER_CSCIE - CAN Status Change
83 uint16_t mscan_IRQs = (MSCAN_TIER_TXE << 8) | MSCAN_RIER_RXFIE | MSCAN_RIER_OVRIE | MSCAN_RIER_CSCIE; /* TX interrupt flag is held shifter */
84 /* 1 - enable interrupt, 0 - interrupt is masked */
87 /* ************************************************************************************************************************************* */
90 int mscan_chip_config(struct canchip_t *chip)
92 /* Do not clear buffers here, they may contain valid data ! */
95 DEBUGMSG("Configuring chip...\n");
97 if (!(err = mscan_enable_configuration(chip)))
101 chip->baudrate=1000000; /* default baudrate set to 1Mbit */
102 if (!(err = mscan_baud_rate(chip, chip->baudrate, chip->clock, 0, 750, 0)))
105 if (!(err = mscan_disable_configuration(chip)))
108 /* IRQ mask could be set only when NOT in INIT mode */
109 if (!(err = mscan_config_irqs(chip, mscan_IRQs)))
115 /* enter initialization AND sleep mode */
116 int mscan_enable_configuration(struct canchip_t *chip)
118 /* Do not clear buffers here, they may contain valid data ! */
121 DEBUGMSG("Enabling configuration...\n");
123 if (mscan_init_mode_active(chip)) /* chip is already in config mode */
126 /* Disable interrupt */
127 can_disable_irq(chip->chip_irq);
130 /* Sleep mode - disable CAN activity after completing current operation */
131 mscan_set_flags(chip, MSCAN_CTL0_SLPRQ, MSCAN_CTL0);
133 /* Waits until chip enters Sleep mode - finishes current TX/RX operation */
134 while (!mscan_get_flags(chip, MSCAN_CTL1_SLPAK, MSCAN_CTL1) && i++ < MSCAN_MAX_SETTING_WAIT_LOOPS)
137 if (i >= MSCAN_MAX_SETTING_WAIT_LOOPS) {
138 CANMSG("Error entering Sleep mode (enable configuration) \n");
139 can_enable_irq(chip->chip_irq);
144 /* now we can enter Init mode */
145 mscan_set_flags(chip, MSCAN_CTL0_INITRQ, MSCAN_CTL0);
148 /* Waits until chip enters Init mode */
149 while (!mscan_get_flags(chip, MSCAN_CTL1_INITAK, MSCAN_CTL1) && i++ < MSCAN_MAX_SETTING_WAIT_LOOPS)
152 if (i >= MSCAN_MAX_SETTING_WAIT_LOOPS) {
153 CANMSG("Error entering Init mode (enable configuration) \n");
154 can_enable_irq(chip->chip_irq);
162 int mscan_disable_configuration(struct canchip_t *chip)
164 /* Do not clear buffers here, they may contain valid data ! */
167 DEBUGMSG("Disabling configuration mode...\n");
169 if (!mscan_init_mode_active(chip) && !mscan_sleep_mode_active(chip)) /* chip is already in normal mode */
173 /* disable Init mode */
174 mscan_clear_flags(chip, MSCAN_CTL0_INITRQ, MSCAN_CTL0);
176 /* Waits until chip leaves Sleep mode */
177 while (mscan_get_flags(chip, MSCAN_CTL1_INITAK, MSCAN_CTL1) && i++ < MSCAN_MAX_SETTING_WAIT_LOOPS)
180 if (i >= MSCAN_MAX_SETTING_WAIT_LOOPS) {
181 CANMSG("Error leaving Init mode (disable configuration) \n");
186 /* disable Sleep mode */
187 mscan_clear_flags(chip, MSCAN_CTL0_SLPRQ, MSCAN_CTL0);
190 /* Waits until chip leaves Init mode */
191 while (mscan_get_flags(chip, MSCAN_CTL1_SLPAK, MSCAN_CTL1) && i++ < MSCAN_MAX_SETTING_WAIT_LOOPS)
194 if (i >= MSCAN_MAX_SETTING_WAIT_LOOPS) {
195 CANMSG("Error leaving Sleep mode (disable configuration) \n");
200 /* Enable interrupt */
201 can_enable_irq(chip->chip_irq);
207 /* ************************************************************************************************************************************* */
210 int mscan_baud_rate(struct canchip_t *chip, int bitrate, int clock, int sjw, int sampl_pt, int flags)
212 /* Set communication parameters.
213 * param rate baud rate in Hz
214 * param clock frequency of mscan clock in Hz
215 * param sjw synchronization jump width (0-3) prescaled clock cycles
216 * param sampl_pt sample point (0-1000) sets (TSEG1 + 1)/(TSEG1 + TSEG2 + 2) ratio
221 /* rate = clock / ((tseg1 + tseg2 + 1) * brp ) */
223 long rate, best_rate = 0;
224 long best_error = 1000000000, error = 0;
225 int best_tseg = 0, best_brp = 0, brp = 0;
226 int tsegall, tseg = 0, tseg1 = 0, tseg2 = 0;
227 int spt = 0, spt_error = best_error;
231 DEBUGMSG("Seting Baud rate...\n");
233 /* Use CIA recommended sample points */
236 if (bitrate > 800000)
238 else if (bitrate > 500000)
244 /* tseg even = round down, odd = round up */
245 for (tseg = MSCAN_TSEG_MAX * 2 + 1; tseg >= MSCAN_TSEG_MIN * 2; tseg--)
247 tsegall = 1 + tseg / 2;
248 /* Compute all possible tseg choices (tseg=tseg1+tseg2) */
249 brp = clock / (tsegall * bitrate) + tseg % 2;
251 if ((brp < MSCAN_BRP_MIN) || (brp > MSCAN_BRP_MAX))
254 /* tseg brp biterror */
255 rate = clock / (brp * tsegall);
256 error = bitrate - rate;
260 if (error > best_error)
265 spt = mscan_update_samplept(sampl_pt, tseg / 2, &tseg1, &tseg2);
266 error = sampl_pt - spt;
270 if (error > spt_error)
275 best_tseg = tseg / 2;
283 /* Error in one-tenth of a percent */
284 error = (best_error * 1000) / bitrate;
285 DEBUGMSG("Baudrate error %lu\n", error);
289 /* recompute with best values */
290 spt = mscan_update_samplept(sampl_pt, best_tseg, &tseg1, &tseg2);
292 DEBUGMSG("Setting %lu bps.\n", best_rate);
294 /* all values has offset -1 */
295 brp--; tseg1--; tseg2--;
297 btr0 = (brp & MSCAN_BTR0_BRP) | ((sjw << 6) & MSCAN_BTR0_SJW);
298 btr1 = (tseg1 & MSCAN_BTR1_TSEG1) | ((tseg2 << 4) & MSCAN_BTR1_TSEG2);
300 mscan_set_btregs(chip, btr0, btr1);
302 mscan_disable_configuration(chip);
304 /* DEBUGMSG("Baud rate set successfully\n"); */
308 int mscan_set_btregs(struct canchip_t *chip, unsigned short bcr0, unsigned short bcr1)
310 /* DEBUGMSG("Seting BCR0 and BCR1.\n"); */
316 btr1 &= ~MSCAN_BTR1_SAMP; /* use one-point sample, not three smaples per bit */
318 can_write_reg(chip, btr0, MSCAN_BTR0);
319 can_write_reg(chip, btr1, MSCAN_BTR1);
321 /* DEBUGMSG("BCR0 and BCR1 successfully set.\n"); */
326 /* ************************************************************************************************************************************* */
329 int mscan_start_chip(struct canchip_t *chip)
331 /* DEBUGMSG("Starting chip %d...\n", chip->chip_idx); */
333 /* Stop chip turns chip to Sleep&Init mode - traffic on CAN bus is ignored after completing curent operation.
334 * Start chip only turn chip back from Sleep&Init state - using disable_config
336 mscan_disable_configuration(chip);
338 DEBUGMSG("Chip [%d] started\n", chip->chip_idx);
342 int mscan_stop_chip(struct canchip_t *chip)
344 /* DEBUGMSG("Stopping chip %d...\n", chip->chip_idx); */
346 /* Stop chip turns chip to Sleep&Init mode - traffic on CAN bus is ignored after completing curent operation.
347 * - using enable_config
349 mscan_enable_configuration(chip);
351 DEBUGMSG("Chip [%d] stopped\n", chip->chip_idx);
355 int mscan_attach_to_chip(struct canchip_t *chip)
357 /* DEBUGMSG("Attaching to chip %d.\n", chip->chip_idx); */
360 /* Clear all TX and RX buffers */
361 if (mscan_clear_objects(chip))
364 /* Transmitt Abort Request Register (TARQ) is clean after INIT mode - no need to clear it explicitly */
365 /* Control Register 0 (CTL0) is clean after INIT too (excepts fro WUPE, SLRQ and INITRQ) */
367 /* initialize chip by entering Sleep & Init mode */
368 if (mscan_enable_configuration(chip))
371 /* reset Control Register 1 (CTL1) */
372 ctl1 = MSCAN_CTL1_CANE |
373 (MPC5200_CLKSRC ? MSCAN_CTL1_CLKSRC : 0x00) ;
374 /* MSCAN_CTL1_LOOPB | LoopBack mode not used */
375 /* MSCAN_CTL1_LISTEN | Listen-Only mode not used */
376 /* MSCAN_CTL1_WUPM | WakeUp mode not used */
377 /* MSCAN_CTL1_SLPAK | ReadOnly */
378 /* MSCAN_CTL1_INITAK | ReadOnly */
380 can_write_reg(chip, ctl1, MSCAN_CTL1);
382 /* set Baudrate and Interrupts */
383 if (mscan_chip_config(chip))
386 /* not neccessary, but just to be sure */
387 if (mscan_disable_configuration(chip))
390 /* Enable interrupt */
391 can_enable_irq(chip->chip_irq);
393 CANMSG("Successfully attached to chip [%02d].\n", chip->chip_idx);
397 int mscan_release_chip(struct canchip_t *chip)
399 mscan_stop_chip(chip); /* we are in INIT mode */
400 can_disable_irq(chip->chip_irq);
402 mscan_clear_objects(chip);
405 mscan_clear_flags(chip, MSCAN_CTL1_CANE, MSCAN_CTL1);
407 DEBUGMSG("Chip released [%02d]\n", chip->chip_idx);
412 /* ************************************************************************************************************************************* */
414 /* has to be called in Init & Sleep mode */
415 int mscan_standard_mask(struct canchip_t *chip, unsigned short code, unsigned short mask)
417 /* code - contains 11bit ID and as LSB the RTR flag */
418 /* code - contains 11bit mask and RTR mask as LSB */
420 reg_t idr0, idr1, mr0, mr1; /* ID register 0,1, Mask register 0, 1 */
422 if (code & 0x1ffff800)
423 return mscan_extended_mask(chip, code, mask);
426 /* we use two 32-bit acceptance filters */
427 mscan_set_flags(chip, 0x30, MSCAN_IDAC);
430 idr0 = (reg_t)((code & 0x0ff0) >> 4); /* 8 most significant bits */
431 idr1 = (reg_t)((code & 0x000f) << 4); /* 3 last bits, RTR as MSB, IDE=0 doesnt have to be set explicitly */
432 mr0 = (reg_t)((mask & 0x0ff0) >> 4);
433 mr1 = (reg_t)((mask & 0x000f) << 4);
436 can_write_reg(chip, idr0, MSCAN_IDAR0);
437 can_write_reg(chip, idr1, MSCAN_IDAR1);
439 can_write_reg(chip, mr0, MSCAN_IDMR0);
440 can_write_reg(chip, mr1, MSCAN_IDMR1);
442 DEBUGMSG("Set standard_mask [id:0x%04x RTR=%d, m:0x%04x RTR=%d]\n", code >> 1, code & 0x0001, mask >> 1, mask & 0x0001);
446 /* has to be called in Init & Sleep mode */
447 int mscan_extended_mask(struct canchip_t *chip, unsigned long code, unsigned long mask)
449 /* code - contains 11bit ID and as LSB the RTR flag */
450 /* code - contains 11bit mask and RTR mask as LSB */
452 reg_t idr0, idr1, idr2, idr3; /* ID registers 0,1,2,3 */
453 reg_t mr0, mr1, mr2, mr3; /* Mask registers 0,1,2,3 */
456 /* we use two 32-bit acceptance filters */
457 mscan_set_flags(chip, 0x30, MSCAN_IDAC);
460 idr0 = (reg_t)((code & 0x7fa00000) >> 22); /* EXT_ID {29:21} */
462 idr1 = (reg_t)((code & 0x00380000) >> 14); /* EXT_ID {20:18} */
463 idr1|= 0x18; /* SRR and IDE */
464 idr1|= (reg_t)((code & 0x00070000) >> 16); /* EXT_ID {17:15} */
466 idr2 = (reg_t)((code & 0x0000ff00) >> 8); /* EXT_ID {14:7} */
467 idr3 = (reg_t) (code & 0x000000ff); /* EXT_ID {6:0} and RTR */
470 mr0 = (reg_t)((mask & 0x7fa00000) >> 22); /* EXT_ID {29:21} */
472 mr1 = (reg_t)((mask & 0x00380000) >> 14); /* EXT_ID {20:18} */
473 /* SRR=0 and IDE=0 - do not ignore */
474 mr1|= (reg_t)((mask & 0x00070000) >> 16); /* EXT_ID {17:15} */
476 mr2 = (reg_t)((mask & 0x0000ff00) >> 8); /* EXT_ID {14:7} */
477 mr3 = (reg_t) (mask & 0x000000ff); /* EXT_ID {6:0} and RTR */
480 can_write_reg(chip, idr0, MSCAN_IDAR0);
481 can_write_reg(chip, idr1, MSCAN_IDAR1);
482 can_write_reg(chip, idr2, MSCAN_IDAR2);
483 can_write_reg(chip, idr3, MSCAN_IDAR3);
485 can_write_reg(chip, mr0, MSCAN_IDMR0);
486 can_write_reg(chip, mr1, MSCAN_IDMR1);
487 can_write_reg(chip, mr2, MSCAN_IDMR2);
488 can_write_reg(chip, mr3, MSCAN_IDMR3);
490 DEBUGMSG("Set extended_mask [id:0x%08x RTR=%lu, m:0x%08x RTR=%lu]\n", (uint32_t)(code >> 1), code & 0x00000001, (uint32_t)(mask >> 1), mask & 0x00000001);
496 /* ************************************************************************************************************************************* */
499 int mscan_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj)
501 DEBUGMSG("Pre read config\n");
503 /* MSCAN has only one buffer, which is already initialized */
508 int mscan_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj, struct canmsg_t *msg)
513 DEBUGMSG("Pre write config\n");
515 can_preempt_disable();
517 /* find free buffer */
518 txf = mscan_get_flags(chip, MSCAN_TFLG_TXE, MSCAN_TFLG);
519 for (buff_no = 0; buff_no < 3 && (txf ^ (0x01 << buff_no)); buff_no++) { }
522 return -ENODEV; /* no free buffer found */
524 mscan_setup_txbuffer(chip, msg, buff_no);
526 /* clear TX Buffer Empty flag (by writing '1') to initiate trasmition */
527 mscan_set_flags(chip, (reg_t)(0x01 << buff_no), MSCAN_TFLG);
529 can_preempt_enable();
534 int mscan_send_msg(struct canchip_t *chip, struct msgobj_t *obj, struct canmsg_t *msg)
536 DEBUGMSG("Send Message\n");
538 /* nothing to do here - message is already set to transmit in pre_write_config */
543 int mscan_remote_request(struct canchip_t *chip, struct msgobj_t *obj)
545 CANMSG("mscan_remote_request not implemented\n");
550 /* ************************************************************************************************************************************* */
553 int mscan_irq_handler(int irq, struct canchip_t *chip)
556 MSCAN_RFLG_WUPIF - WakeUp Interrupt Flag - rw
557 MSCAN_RFLG_CSCIF - CAN Status Change Interrupt Flag - rw
558 MSCAN_RFLG_RSTAT - Receiver Status Bits: 0-RxOK, 1-RxWRN, 2-RxERR, 3-BusOff - ro
559 MSCAN_RFLG_TSTAT - Transmitter Status Bits: 0-TxOK, 1-TxWRN, 2-TxErr, 3-BusOff - ro
560 MSCAN_RFLG_OVRIF - Overrun Interrupt Flag - rw
561 MSCAN_RFLG_RXF - Receive Buffer Full - rw
563 MSCAN_TFLG_TXE - Transmitter Buffer Empty */
567 short loop_cnt = MSCAN_MAX_IRQ_WAIT_LOOPS;
569 irq_reg = (mscan_get_flags(chip, (reg_t)((mscan_IRQs >> 8) & 0xff), MSCAN_TFLG) << 8) |
570 (mscan_get_flags(chip, (reg_t)(mscan_IRQs & 0xff), MSCAN_RFLG));
571 DEBUGMSG("irq: %d", irq);
572 DEBUGMSG("IRQ Handler: MSCAN_IRR: 0x%04x\n", irq_reg);
577 CANMSG("mscan_irq_handler IRQ %d stuck\n", irq);
578 return CANCHIP_IRQ_STUCK;
581 /* Received message */
582 if (irq_reg & MSCAN_RFLG_RXF)
584 DEBUGMSG("Received message");
586 mscan_irq_read_handler(chip, chip->msgobj[0]);
587 /* RXPR flag for this msgobj is cleared during irq_read_handler*/
590 mscan_set_flags(chip, MSCAN_RFLG_RXF, MSCAN_RFLG);
593 /* Receive bus off/error/warning */
594 if (irq_reg & MSCAN_RFLG_RSTAT)
596 switch (((irq_reg & MSCAN_RFLG_RSTAT) >> 4) & 0x03)
598 case 3: /* Bus off */
599 CANMSG("Error: entering RX BUS OFF state");
601 chip->msgobj[0]->ret=-1;
604 mscan_notifyRXends(chip->msgobj[0], CANQUEUE_NOTIFY_ERROR);
607 case 2: /* bus - error passive */
608 CANMSG("Warning: entering ERROR PASSIVE state REC: %d\n", (reg_t)can_read_reg(chip, MSCAN_RXERR));
609 /* Show warning only */
612 case 1: /* bus - warning */
613 CANMSG("Bus Warning: REC: %d\n", (reg_t)can_read_reg(chip, MSCAN_RXERR));
614 /* Show warning only */
619 mscan_set_flags(chip, MSCAN_RFLG_RSTAT, MSCAN_RFLG);
622 /* Transmit bus off/error/warning */
623 if (irq_reg & MSCAN_RFLG_TSTAT)
625 switch (((irq_reg & MSCAN_RFLG_TSTAT) >> 1) & 0x03)
627 case 3: /* Bus off */
628 CANMSG("Error: entering TX BUS OFF state");
631 if(chip->msgobj[0]->tx_slot)
632 canque_notify_inends(chip->msgobj[0]->tx_qedge, CANQUEUE_NOTIFY_ERROR);
635 case 2: /* bus - error passive */
636 CANMSG("Warning: entering ERROR PASSIVE state TEC: %d\n", (reg_t)can_read_reg(chip, MSCAN_TXERR));
637 /* Show warning only */
640 case 1: /* bus - warning */
641 CANMSG("Bus Warning: TEC: %d\n", (reg_t)can_read_reg(chip, MSCAN_TXERR));
642 /* Show warning only */
647 mscan_set_flags(chip, MSCAN_RFLG_TSTAT, MSCAN_RFLG);
650 /* Message Overrun/Overwritten */
651 if (irq_reg & MSCAN_RFLG_OVRIF)
653 CANMSG("Error: MESSAGE OVERRUN/OVERWRITTEN");
655 /* notify only injured RXqueue-end */
656 mscan_notifyRXends(chip->msgobj[0], CANQUEUE_NOTIFY_ERROR);
659 mscan_set_flags(chip, MSCAN_RFLG_OVRIF, MSCAN_RFLG);
662 /* Mailbox empty - after message was sent */
663 if ((irq_reg >> 8) & MSCAN_TFLG_TXE)
665 /* Clear TXACK flag */
666 mscan_set_flags(chip, MSCAN_TFLG_TXE, MSCAN_TFLG);
669 mscan_wakeup_tx(chip, chip->msgobj[0]);
672 irq_reg = (mscan_get_flags(chip, (reg_t)((mscan_IRQs >> 8) & 0xff), MSCAN_TFLG) << 8) |
673 (mscan_get_flags(chip, (reg_t)(mscan_IRQs & 0xff), MSCAN_RFLG));
674 } while(irq_reg & mscan_IRQs);
676 return CANCHIP_IRQ_HANDLED;
679 int mscan_irq_accept(int irq, struct canchip_t *chip)
681 CANMSG("mscan_irq_accept NOT IMPLEMENTED\n");
685 int mscan_config_irqs(struct canchip_t *chip, short irqs)
690 if (mscan_init_mode_active(chip))
692 CANMSG("MSCAN: Setting Up IRQs while INIT active \n");
696 tier = (reg_t)((irqs >> 8) & 0x00ff & ~MSCAN_TIER_RSVD);
697 rier = (reg_t)(irqs & 0x00ff);
699 if(!(err = mscan_clear_irq_flags(chip)))
702 can_write_reg(chip, rier, MSCAN_RIER);
703 can_write_reg(chip, tier, MSCAN_TIER);
705 CANMSG("IRQ Mask set [0x%02x]\n", irqs);
710 /* ************************************************************************************************************************************* */
713 int mscan_clear_objects(struct canchip_t *chip)
715 /* clear RX buffer */
716 mscan_clear_buffer(chip, MSCAN_RXFG);
718 /* clear TX buffers, need to set CANTBSEL register */
719 can_write_reg(chip, 0x01, MSCAN_TBSEL);
720 mscan_clear_buffer(chip, MSCAN_TXFG);
722 can_write_reg(chip, 0x02, MSCAN_TBSEL);
723 mscan_clear_buffer(chip, MSCAN_TXFG);
725 can_write_reg(chip, 0x04, MSCAN_TBSEL);
726 mscan_clear_buffer(chip, MSCAN_TXFG);
731 int mscan_check_tx_stat(struct canchip_t *chip)
733 /* DEBUGMSG("Check TX stat\n"); */
734 /* If Transmition is complete return 0 - no error */
735 if (mscan_get_flags(chip, MSCAN_TFLG_TXE, MSCAN_TFLG) == MSCAN_TFLG_TXE) /* all buffers empty */
741 /* Note: this checks TX status of particular buffer */
742 int mscan_check_txbuff_stat(struct canchip_t *chip, int buffer)
744 /* Transmition is complete return 0 - no error */
745 reg_t txf = mscan_get_flags(chip, MSCAN_TFLG_TXE, MSCAN_TFLG);
746 return (txf ^ (0x01 << buffer));
749 int mscan_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj)
751 DEBUGMSG("WakeUP TX\n");
753 can_preempt_disable();
755 can_msgobj_set_fl(obj,TX_REQUEST);
756 if(!can_msgobj_test_and_set_fl(obj,TX_LOCK) &&
757 (!mscan_check_txbuff_stat(chip, 0) ||
758 !mscan_check_txbuff_stat(chip, 1) ||
759 !mscan_check_txbuff_stat(chip, 2)))
760 { /* enable transmition only if MB is empty */
761 can_msgobj_clear_fl(obj,TX_REQUEST);
763 mscan_irq_write_handler(chip, obj);
765 can_msgobj_clear_fl(obj,TX_LOCK);
768 can_msgobj_clear_fl(obj,TX_REQUEST);
771 can_preempt_enable();
773 /* DEBUGMSG("WakeUP TX - END\n"); */
777 int mscan_filtch_rq(struct canchip_t *chip, struct msgobj_t * obj)
779 struct canfilt_t filter;
784 int num = canqueue_ends_filt_conjuction(obj->qends, &filter);
786 canqueue_ends_filt_conjuction(obj->qends, &filter);
789 DEBUGMSG("CNT: %d ID: 0x%08x MASK: 0x%08x\n", num, (uint32_t) (filter.id) & 0x1fffffff, (uint32_t) (~filter.mask) & 0x1fffffff);
791 /* MSCAN uses oposite logic (compared to IP) for LAFM: 1-ignore bit, 0-use bit as mask */
792 mask = (~filter.mask) << 1;
794 /* RTR is LSB of mask */
795 if (filter.flags & MSG_RTR)
798 if (filter.flags & MSG_EXT) /* Extended ID */
799 return mscan_extended_mask(chip, filter.id, mask);
800 else /* Standard ID */
801 return mscan_standard_mask(chip, filter.id, mask);
805 /* ************************************************************************************************************************************* */
808 void mscan_irq_read_handler(struct canchip_t *chip, struct msgobj_t *obj)
811 if (!mscan_get_flags(chip, MSCAN_RFLG_RXF, MSCAN_RFLG))
817 mscan_msg_from_rxbuffer(chip, &(obj->rx_msg));
819 /* fill CAN message timestamp */
820 can_filltimestamp(&obj->rx_msg.timestamp);
822 canque_filter_msg2edges(obj->qends, &obj->rx_msg);
825 void mscan_irq_write_handler(struct canchip_t *chip, struct msgobj_t *obj)
830 /* Do local transmitted message distribution if enabled */
832 /* fill CAN message timestamp */
833 can_filltimestamp(&obj->tx_slot->msg.timestamp);
835 obj->tx_slot->msg.flags |= MSG_LOCAL;
836 canque_filter_msg2edges(obj->qends, &obj->tx_slot->msg);
838 /* Free transmitted slot */
839 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
843 cmd = canque_test_outslot(obj->qends, &obj->tx_qedge, &obj->tx_slot);
847 if (chip->chipspecops->pre_write_config(chip, obj, &obj->tx_slot->msg)) {
849 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_PREP);
850 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
854 if (chip->chipspecops->send_msg(chip, obj, &obj->tx_slot->msg)) {
856 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_SEND);
857 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
864 /* ************************************************************************************************************************************* */
867 int mscan_register(struct chipspecops_t *chipspecops)
869 chipspecops->chip_config = mscan_chip_config;
870 chipspecops->enable_configuration = mscan_enable_configuration;
871 chipspecops->disable_configuration = mscan_disable_configuration;
873 chipspecops->baud_rate = mscan_baud_rate;
874 chipspecops->set_btregs = mscan_set_btregs;
876 chipspecops->start_chip = mscan_start_chip;
877 chipspecops->stop_chip = mscan_stop_chip;
878 chipspecops->attach_to_chip = mscan_attach_to_chip;
879 chipspecops->release_chip = mscan_release_chip;
881 chipspecops->standard_mask = mscan_standard_mask;
882 chipspecops->extended_mask = mscan_extended_mask;
883 chipspecops->message15_mask = NULL; /* mscan_message15_mask; */
885 chipspecops->pre_read_config = mscan_pre_read_config;
886 chipspecops->pre_write_config = mscan_pre_write_config;
887 chipspecops->send_msg = mscan_send_msg;
888 chipspecops->remote_request = mscan_remote_request;
890 chipspecops->irq_handler = mscan_irq_handler;
891 chipspecops->irq_accept = NULL; /* mscan_irq_accept; */
892 chipspecops->config_irqs = mscan_config_irqs;
894 chipspecops->clear_objects = mscan_clear_objects;
895 chipspecops->check_tx_stat = mscan_check_tx_stat;
896 chipspecops->wakeup_tx = mscan_wakeup_tx;
897 chipspecops->filtch_rq = mscan_filtch_rq;
901 int mscan_fill_chipspecops(struct canchip_t *chip)
903 chip->chip_type = "mscan";
904 chip->max_objects = 1;
905 chip->write_register = chip->hostdevice->hwspecops->write_register;
906 chip->read_register = chip->hostdevice->hwspecops->read_register;
927 mscan_register(chip->chipspecops);
932 /* ************************************************************************************************************************************* */
935 int mscan_reset_chip(struct canchip_t * chip)
937 /* reset chip by turning MSCAN off and on in INIT mode */
938 if (mscan_enable_configuration(chip))
941 mscan_clear_flags(chip, MSCAN_CTL1_CANE, MSCAN_CTL1);
942 mscan_set_flags(chip, MSCAN_CTL1_CANE, MSCAN_CTL1);
944 if (mscan_disable_configuration(chip))
950 /* mscan_clear_irq_flags should be called only when not in INIT mode */
951 int mscan_clear_irq_flags(struct canchip_t *chip)
955 if (mscan_init_mode_active(chip))
957 CANMSG("MSCAN: Clearing IRQs while INIT active \n");
961 DEBUGMSG("Clearing IRQ flags...\n");
963 rflg = MSCAN_RFLG_WUPIF | MSCAN_RFLG_CSCIF | MSCAN_RFLG_RSTAT |
964 MSCAN_RFLG_TSTAT | MSCAN_RFLG_OVRIF | MSCAN_RFLG_RXF;
965 tflg = MSCAN_TFLG_TXE;
967 /* reset flags by writing '1' */
968 can_write_reg(chip, rflg, MSCAN_RFLG);
969 can_write_reg(chip, tflg, MSCAN_TFLG);
975 /* ************************************************************************************************************************************* */
978 void mscan_notifyRXends(struct msgobj_t * obj, int what)
980 struct canque_edge_t * edge;
981 canque_for_each_inedge(obj->qends, edge){
982 canque_notify_outends(edge, what);
986 /* Fill message content to one transmit buffers */
987 /* Note: Check whether buffer is empy has to be done before calling this function */
988 void mscan_setup_txbuffer(struct canchip_t * chip, struct canmsg_t * msg, int buffer)
990 volatile struct mscan_msg_buffer * txb = (struct mscan_msg_buffer *)MSCAN_TXFG;
994 mscan_set_flags(chip, (0x01 << buffer) & MSCAN_TBSEL_TX, MSCAN_TBSEL);
997 if (msg->flags & MSG_RTR)
1002 /* set Can mesage ID and local priority */
1003 if (msg->flags & MSG_EXT)
1006 txb->id_0 = (reg_t)((msg->id >> 21) & 0x000000ff);
1007 txb->id_1 = (reg_t)(
1008 ((msg->id >> 18) & 0x000000e0) |
1009 0x00000018 | /* SRR & IDE */
1010 ((msg->id >> 15) & 0x00000003));
1011 txb->id_2 = (reg_t)((msg->id >> 7) & 0x000000ff);
1012 txb->id_3 = (reg_t)(((msg->id << 1) & 0x000000fe) | rtr);
1014 /* local priority is 7 MSB bits followed by IDE flag */
1015 txb->local_prio = (reg_t)((txb->id_0 & 0xfe) | 0x01); /* IDE=1 */
1020 txb->id_0 = (reg_t)((msg->id >> 3) & 0x000000ff);
1021 txb->id_1 = (reg_t)(((msg->id << 5) & 0x000000e0) | (rtr << 4)); /* IDE=0 */
1025 /* local priority are 7 MSB bits folowed by IDE flag */
1026 txb->local_prio = (reg_t)(txb->id_0 & 0xfe); /* IDE=0 */
1030 switch (msg->length)
1032 case 8: txb->data_7 = msg->data[7];
1033 case 7: txb->data_6 = msg->data[6];
1034 case 6: txb->data_5 = msg->data[5];
1035 case 5: txb->data_4 = msg->data[4];
1036 case 4: txb->data_3 = msg->data[3];
1037 case 3: txb->data_2 = msg->data[2];
1038 case 2: txb->data_1 = msg->data[1];
1039 case 1: txb->data_0 = msg->data[0];
1043 txb->data_len = (reg_t)(msg->length & 0x1f);
1046 /* Fill message content from receive buffer */
1047 void mscan_msg_from_rxbuffer(struct canchip_t * chip, struct canmsg_t * msg)
1049 volatile struct mscan_msg_buffer * rxb = (struct mscan_msg_buffer *)MSCAN_RXFG;
1051 /* retrieve Can mesage ID */
1052 msg->flags = 0; /* clear all */
1054 /* check buffer IDE flag */
1055 if (mscan_get_flags(chip, (reg_t)0x08, MSCAN_RXFG + MSCAN_MSGBUFF_ID1)) /* 0x08 - IDE flag in ID1 */
1058 msg->id = (((uint32_t)rxb->id_0 << 21) & 0x3fa00000) |
1059 (((uint32_t)rxb->id_1 << 18) & 0x00380000) |
1060 (((uint32_t)rxb->id_1 << 15) & 0x00070000) |
1061 (((uint32_t)rxb->id_2 << 7 ) & 0x0000ff00) |
1062 (((uint32_t)rxb->id_3 >> 1 ) & 0x000000ff);
1065 if (rxb->id_3 & 0x01)
1066 msg->flags |= MSG_RTR;
1069 msg->flags |= MSG_EXT;
1074 msg->id = (((uint32_t)rxb->id_0 << 3) & 0x000001f8) |
1075 (((uint32_t)rxb->id_1 >> 5) & 0x00000007);
1078 if (rxb->id_1 & 0x08)
1079 msg->flags |= MSG_RTR;
1081 /* no EXT flag is set here */
1085 switch (rxb->data_len)
1087 case 8: msg->data[7] = rxb->data_7;
1088 case 7: msg->data[6] = rxb->data_6;
1089 case 6: msg->data[5] = rxb->data_5;
1090 case 5: msg->data[4] = rxb->data_4;
1091 case 4: msg->data[3] = rxb->data_3;
1092 case 3: msg->data[2] = rxb->data_2;
1093 case 2: msg->data[1] = rxb->data_1;
1094 case 1: msg->data[0] = rxb->data_0;
1098 msg->length = (reg_t)(rxb->data_len & 0x1f);
1100 /* updates the TSEG1 and TSEG2 according to overall TSEG and Sample Point (0-1000) */
1101 static int mscan_update_samplept(int sampl_pt, int tseg, int *tseg1, int *tseg2)
1103 *tseg2 = tseg + 1 - (sampl_pt * (tseg + 1)) / 1000;
1104 if (*tseg2 < MSCAN_TSEG2_MIN)
1105 *tseg2 = MSCAN_TSEG2_MIN;
1106 if (*tseg2 > MSCAN_TSEG2_MAX)
1107 *tseg2 = MSCAN_TSEG2_MAX;
1108 *tseg1 = tseg - *tseg2;
1109 if (*tseg1 > MSCAN_TSEG1_MAX) {
1110 *tseg1 = MSCAN_TSEG1_MAX;
1111 *tseg2 = tseg - *tseg1;
1113 return 1000 * (tseg + 1 - *tseg2) / (tseg + 1);
1117 static int mscan_init_mode_active(struct canchip_t *chip)
1119 /* Init request AND Init ACK */
1120 DEBUGMSG(" is Init active?\n");
1121 return mscan_get_flags(chip, MSCAN_CTL0_INITRQ, MSCAN_CTL0) &&
1122 mscan_get_flags(chip, MSCAN_CTL1_INITAK, MSCAN_CTL1);
1124 static int mscan_sleep_mode_active(struct canchip_t *chip)
1126 /* Sleep Request AND Sleep Ack */
1127 return mscan_get_flags(chip, MSCAN_CTL0_SLPRQ, MSCAN_CTL0) &&
1128 mscan_get_flags(chip, MSCAN_CTL1_SLPAK, MSCAN_CTL1);
1132 static reg_t mscan_get_flags(struct canchip_t * chip, reg_t flags, unsigned reg_addr)
1134 DEBUGMSG(" get flags [%u]\n", reg_addr);
1135 return (reg_t)can_read_reg(chip, reg_addr) & flags;
1137 static void mscan_set_flags(struct canchip_t * chip, reg_t flags, unsigned reg_addr)
1139 reg_t r = can_read_reg(chip, reg_addr);
1140 can_write_reg(chip, r | flags, reg_addr);
1142 static void mscan_clear_flags(struct canchip_t * chip, reg_t flags, unsigned reg_addr)
1144 reg_t r = can_read_reg(chip, reg_addr);
1145 can_write_reg(chip, r & ~flags, reg_addr);
1149 static void mscan_clear_buffer(struct canchip_t * chip, unsigned start_addr)
1151 /* clear 25 registers of buffer, others are reset to 0-no need to clean them */
1153 for (addr = start_addr; addr < 26; addr++)
1154 can_write_reg(chip, 0x00, addr);