2 * Header file for the Linux CAN-bus driver.
3 * This software is released under the GPL-License.
6 int hcan2_chip_config(struct canchip_t *chip);
7 int hcan2_enable_configuration(struct canchip_t *chip);
8 int hcan2_disable_configuration(struct canchip_t *chip);
10 int hcan2_baud_rate(struct canchip_t *chip, int rate, int clock, int sjw, int sampl_pt, int flags);
11 int hcan2_set_btregs(struct canchip_t *chip, unsigned short btr0, unsigned short btr1);
13 int hcan2_start_chip(struct canchip_t *chip);
14 int hcan2_stop_chip(struct canchip_t *chip);
15 int hcan2_attach_to_chip(struct canchip_t *chip);
16 int hcan2_release_chip(struct canchip_t *chip);
18 int hcan2_standard_mask(struct canchip_t *chip, unsigned short code, unsigned short mask);
19 int hcan2_extended_mask(struct canchip_t *chip, unsigned long code, unsigned long mask);
20 int hcan2_message15_mask(int irq, struct canchip_t *chip);
22 int hcan2_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj);
23 int hcan2_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj, struct canmsg_t *msg);
24 int hcan2_send_msg(struct canchip_t *chip, struct msgobj_t *obj, struct canmsg_t *msg);
25 int hcan2_remote_request(struct canchip_t *chip, struct msgobj_t *obj);
27 int hcan2_irq_handler(int irq, struct canchip_t *chip);
28 int hcan2_irq_accept(int irq, struct canchip_t *chip);
29 int hcan2_config_irqs(struct canchip_t *chip, short irqs);
31 int hcan2_clear_objects(struct canchip_t *chip);
32 int hcan2_check_tx_stat(struct canchip_t *chip);
33 int hcan2_check_MB_tx_stat(struct canchip_t *chip, struct msgobj_t *obj);
34 int hcan2_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj);
35 int hcan2_filtch_rq(struct canchip_t *chip, struct msgobj_t * obj);
37 int hcan2_register(struct chipspecops_t *chipspecops);
38 int hcan2_fill_chipspecops(struct canchip_t *chip);
40 int hcan2_reset_chip(struct canchip_t *chip);
43 extern inline void can_write_reg_w(const struct canchip_t *pchip, uint16_t data, unsigned reg)
45 can_ioptr_t address = pchip->chip_base_addr + reg;
46 #ifndef CONFIG_OC_LINCAN_DYNAMICIO
48 #else /*CONFIG_OC_LINCAN_DYNAMICIO*/
49 pchip->write_register(data, address);
50 #endif /*CONFIG_OC_LINCAN_DYNAMICIO*/
53 extern inline uint16_t can_read_reg_w(const struct canchip_t *pchip, unsigned reg)
55 can_ioptr_t address = pchip->chip_base_addr + reg;
56 #ifndef CONFIG_OC_LINCAN_DYNAMICIO
57 return readw(address);
58 #else /*CONFIG_OC_LINCAN_DYNAMICIO*/
59 return pchip->read_register(address);
60 #endif /*CONFIG_OC_LINCAN_DYNAMICIO*/
64 /* BasicCAN mode address map */
65 #define HCAN2_MCR 0x00000000 /* Master control register */
66 #define HCAN2_GSR 0x00000002 /* General status register */
67 #define HCAN2_BCR1 0x00000004 /* Bit configuration register 1 */
68 #define HCAN2_BCR0 0x00000006 /* Bit configuration register 0 */
69 #define HCAN2_IRR 0x00000008 /* Interrupt request register */
70 #define HCAN2_IMR 0x0000000a /* Interrupt mask register */
71 #define HCAN2_TECREC 0x0000000c /* 15:8 Transmit error counter 7:0 Receive error counter */
72 #define HCAN2_TXPR1 0x00000020 /* Transmit pending request register 1 */
73 #define HCAN2_TXPR0 0x00000022 /* Transmit pending request register 0 */
74 #define HCAN2_TXCR1 0x00000028 /* Transmit cancel register 1 */
75 #define HCAN2_TXCR0 0x0000002a /* Transmit cancel register 0 */
76 #define HCAN2_TXACK1 0x00000030 /* Transmit acknowledge register 1 */
77 #define HCAN2_TXACK0 0x00000032 /* Transmit acknowledge register 0 */
78 #define HCAN2_ABACK1 0x00000038 /* Abort acknowledge register 1 */
79 #define HCAN2_ABACK0 0x0000003a /* Abort acknowledge register 0 */
80 #define HCAN2_RXPR1 0x00000040 /* Receive data frame pending register 1 */
81 #define HCAN2_RXPR0 0x00000042 /* Receive data frame pending register 0 */
82 #define HCAN2_RFPR1 0x00000048 /* Remote frame request pending register 1 */
83 #define HCAN2_RFPR0 0x0000004a /* Remote frame request pending register 0 */
84 #define HCAN2_MBIMR1 0x00000050 /* Mailbox interrupt mask register 1 */
85 #define HCAN2_MBIMR0 0x00000052 /* Mailbox interrupt mask register 0 */
86 #define HCAN2_UMSR1 0x00000058 /* Unread message status register 1 */
87 #define HCAN2_UMSR0 0x0000005a /* Unread message status register 0 */
88 #define HCAN2_TCNTR 0x00000080 /* Timer counter register */
89 #define HCAN2_TCR 0x00000082 /* Timer control register */
90 #define HCAN2_TCMR 0x00000084 /* Timer Compare Match register */
91 #define HCAN2_TDCR 0x00000086
92 #define HCAN2_LOSR 0x00000088
93 #define HCAN2_ICR1 0x0000008e
94 #define HCAN2_TCMR0 0x00000090 /* Timer compare match register */
95 #define HCAN2_TCMR1 0x00000092
96 #define HCAN2_TCMR2 0x00000094
97 #define HCAN2_CCR 0x00000096
98 #define HCAN2_CMAX 0x00000098
99 #define HCAN2_TMR 0x0000009a
101 /* BaudRate minimal and maximal TSEG values */
110 /* bits 15 to 8 are used for test mode */
111 HCAN2_MCR_AWAKE = 1 << 7, /* Auto Wake Mode */
112 HCAN2_MCR_SLEEP = 1 << 5, /* Sleep Mode */
113 HCAN2_MCR_TXP = 1 << 2, /* Transmition Priority 0-message ID number priority, 1-mailbox number piority*/
114 HCAN2_MCR_HALT = 1 << 1, /* Halt Request */
115 HCAN2_MCR_RESET = 1 << 0, /* Reset Request */
119 HCAN2_GSR_EPS = 1 << 5, /* Error Passive Status */
120 HCAN2_GSR_HSS = 1 << 4, /* Halt/Sleep Status */
121 HCAN2_GSR_RESET = 1 << 3, /* Reset Status */
122 HCAN2_GSR_TXC = 1 << 2, /* Message Transmission Complete Flag */
123 HCAN2_GSR_TXRXW = 1 << 1, /* Transmit/Receive Warning Flag */
124 HCAN2_GSR_BOFF = 1 << 0, /* Buss Off Flag */
127 /* IRR and IMR register */
129 HCAN2_IRR_TCMI = 1 << 14, /* Time Compare Match Register */
130 HCAN2_IRR_TOI = 1 << 13, /* Time Overrun Interrupt */
131 HCAN2_IRR_WUBA = 1 << 12, /* Wake-up on Bus Activity */
132 HCAN2_IRR_MOOI = 1 << 9, /* Message Overrun/Overwrite Interrupt Flag */
133 HCAN2_IRR_MBEI = 1 << 8, /* Messagebox Empty Interrupt Flag */
134 HCAN2_IRR_OF = 1 << 7, /* Overload Frame */
135 HCAN2_IRR_BOI = 1 << 6, /* Bus Off Interrupt Flag */
136 HCAN2_IRR_EPI = 1 << 5, /* Error Passive Interrupt Flag */
137 HCAN2_IRR_ROWI = 1 << 4, /* Receive Overload Warning Interrupt Flag */
138 HCAN2_IRR_TOWI = 1 << 3, /* Transmit Overload Warining Interrupt Flag */
139 HCAN2_IRR_RFRI = 1 << 2, /* Remote Frame Request Interrupt Flag */
140 HCAN2_IRR_DFRI = 1 << 1, /* Data Frame Received Interrupt Flag */
141 HCAN2_IRR_RHSI = 1 << 0, /* Reset/Halt/Sleep Interrupt Flag */
144 /* Message box 0-31 */
145 #define HCAN2_MB0 0x00000100 /* RECEIVE ONLY */
146 #define HCAN2_MB_OFFSET 0x00000020
148 /* Message box structure offsets */
149 #define HCAN2_MB_CTRL0 0x00000000 /* Control 0 */
150 #define HCAN2_MB_CTRL1 0x00000002 /* Control 1 */
151 #define HCAN2_MB_CTRL2 0x00000004 /* Control 2 */
152 #define HCAN2_MB_TSTP 0x00000006 /* Time stamp */
153 #define HCAN2_MB_DATA0 0x00000009 /* Data 0 */
154 #define HCAN2_MB_DATA1 0x00000008 /* Data 1 */
155 #define HCAN2_MB_DATA2 0x0000000b /* Data 2 */
156 #define HCAN2_MB_DATA3 0x0000000a /* Data 3 */
157 #define HCAN2_MB_DATA4 0x0000000d /* Data 4 */
158 #define HCAN2_MB_DATA5 0x0000000c /* Data 5 */
159 #define HCAN2_MB_DATA6 0x0000000f /* Data 6 */
160 #define HCAN2_MB_DATA7 0x0000000e /* Data 7 */
161 #define HCAN2_MB_MASK 0x00000010 /* Acceptance filter mask 4 bytes */
163 /* Control register 0 */
165 HCAN2_MBCT0_STDID = 0x7ff0, /* STD ID */
166 HCAN2_MBCT0_RTR = 0x0008, /* Remote transmition request 0-DataFrame 1-RemoteFrame */
167 HCAN2_MBCT0_IDE = 0x0004, /* Identifier extension 0-Standard 1-Extended */
168 HCAN2_MBCT0_EXTID = 0x0003 /* EXTID 17:16 */
171 /* Control register 1 */
172 /* whole register is EXTD ID 15:0 */
174 /* Control register 2 */
176 HCAN2_MBCT2_NMC = 1<<13, /* New message control */
177 HCAN2_MBCT2_ATX = 1<<12, /* Automatic transmition of data frame */
178 HCAN2_MBCT2_DART = 1<<11, /* Disable automatic re-transmition */
179 HCAN2_MBCT2_MBC = 7<<8, /* Mailbox configuration */
180 HCAN2_MBCT2_CBE = 1<<5, /* CAN bus error */
181 HCAN2_MBCT2_DLC = 0xf /* Data length code */
184 /* MessageBox modes */
186 HCAN2_MBMOD_TXDR = 0, /* Transmit Data and Remote Frame */
187 HCAN2_MBMOD_TXDR_RXR = 1, /* Transmit Data and Remote Frame, Receive Remote Frame */
188 HCAN2_MBMOD_RXDR = 2, /* Receive Data and Remote Frame */
189 HCAN2_MBMOD_RXD = 3, /* Receive Data Frame */
190 HCAN2_MBMOD_TXR_RXDR = 4, /* Transmit Remote Frame, Receive Data and Remove Frame */
191 HCAN2_MBMOD_TXR_RXD = 5, /* Transmit Remote Frame, Receive Data Frame */
192 /* 6 is not used and prohibited */
193 HCAN2_MBMOD_INNACTIVE = 7, /* Mailboc Innactive */