2 * Header file for the Linux CAN-bus driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * Added by T.Motylewski@bfad.de
5 * See app. note an97076.pdf from Philips Semiconductors
6 * and SJA1000 data sheet
8 * This software is released under the GPL-License.
9 * Version lincan-0.3 17 Jun 2004
15 int sja1000p_chip_config(struct canchip_t *chip);
16 int sja1000p_extended_mask(struct canchip_t *chip, unsigned long code, unsigned long mask);
17 int sja1000p_baud_rate(struct canchip_t *chip, int rate, int clock, int sjw,
18 int sampl_pt, int flags);
19 int sja1000p_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj);
20 int sja1000p_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
21 struct canmsg_t *msg);
22 int sja1000p_send_msg(struct canchip_t *chip, struct msgobj_t *obj,
23 struct canmsg_t *msg);
24 int sja1000p_fill_chipspecops(struct canchip_t *chip);
25 int sja1000p_irq_handler(int irq, struct canchip_t *chip);
29 enum SJA1000_PeliCAN_regs {
35 /// Interrupt register
39 /// Bus Timing register 0
41 /// Bus Timing register 1
43 /// Output Control register
45 /// Arbitration Lost Capture
47 /// Error Code Capture
49 /// Error Warning Limit
56 /// Rx Message Counter (number of msgs. in RX FIFO
58 /// Rx Buffer Start Addr. (address of current MSG)
60 /// Transmit Buffer (write) Receive Buffer (read) Frame Information
62 /// ID bytes (11 bits in 0 and 1 or 16 bits in 0,1 and 13 bits in 2,3 (extended))
63 SJAID0 = 0x11, SJAID1 = 0x12,
64 /// ID cont. for extended frames
65 SJAID2 = 0x13, SJAID3 = 0x14,
66 /// Data start standard frame
68 /// Data start extended frame
70 /// Acceptance Code (4 bytes) in RESET mode
72 /// Acceptance Mask (4 bytes) in RESET mode
75 SJA_PeliCAN_AC_LEN = 4,
80 /** Mode Register 0x00 */
81 enum sja1000_PeliCAN_MOD {
82 sjaMOD_SM = 1<<4, // Sleep Mode (writable only in OPERATING mode)
83 sjaMOD_AFM= 1<<3, // Acceptance Filter Mode (writable only in RESET)
84 sjaMOD_STM= 1<<2, // Self Test Mode (writable only in RESET)
85 sjaMOD_LOM= 1<<1, // Listen Only Mode (writable only in RESET)
86 sjaMOD_RM = 1 // Reset Mode
89 /** Command Register 0x01 */
90 enum sja1000_PeliCAN_CMR {
91 sjaCMR_SRR= 1<<4, // Self Reception Request (GoToSleep in BASIC mode)
92 sjaCMR_CDO= 1<<3, // Clear Data Overrun
93 sjaCMR_RRB= 1<<2, // Release Receive Buffer
94 sjaCMR_AT = 1<<1, // Abort Transmission
95 sjaCMR_TR = 1 }; // Transmission Request
97 /** Status Register 0x02 */
99 sjaSR_BS = 1<<7, // Bus Status
100 sjaSR_ES = 1<<6, // Error Status
101 sjaSR_TS = 1<<5, // Transmit Status
102 sjaSR_RS = 1<<4, // Receive Status
103 sjaSR_TCS = 1<<3, // Transmission Complete Status
104 sjaSR_TBS = 1<<2, // Transmit Buffer Status
105 sjaSR_DOS = 1<<1, // Data Overrun Status
106 sjaSR_RBS = 1 }; // Receive Buffer Status
108 /** Interrupt Enable Register 0x04 */
109 enum sja1000_PeliCAN_IER {
110 sjaIER_BEIE= 1<<7, // Bus Error Interrupt Enable
111 sjaIER_ALIE= 1<<6, // Arbitration Lost Interrupt Enable
112 sjaIER_EPIE= 1<<5, // Error Passive Interrupt Enable
113 sjaIER_WUIE= 1<<4, // Wake-Up Interrupt Enable
114 sjaIER_DOIE= 1<<3, // Data Overrun Interrupt Enable
115 sjaIER_EIE = 1<<2, // Error Warning Interrupt Enable
116 sjaIER_TIE = 1<<1, // Transmit Interrupt Enable
117 sjaIER_RIE = 1, // Receive Interrupt Enable
118 sjaENABLE_INTERRUPTS = sjaIER_BEIE|sjaIER_EPIE|sjaIER_DOIE|sjaIER_EIE|sjaIER_TIE|sjaIER_RIE,
119 sjaDISABLE_INTERRUPTS = 0
120 // WARNING: the chip automatically enters RESET (bus off) mode when
121 // error counter > 255
124 /** Arbitration Lost Capture Register 0x0b.
125 * Counting starts from 0 (bit1 of ID). Bits 5-7 reserved*/
126 enum sja1000_PeliCAN_ALC {
127 sjaALC_SRTR = 0x0b,// Arbitration lost in bit SRTR
128 sjaALC_IDE = 0x1c, // Arbitration lost in bit IDE
129 sjaALC_RTR = 0x1f, // Arbitration lost in RTR
132 /** Error Code Capture Register 0x0c*/
133 enum sja1000_PeliCAN_ECC {
137 sjaECC_FORM = sjaECC_ERCC0,
138 sjaECC_STUFF = sjaECC_ERCC1,
139 sjaECC_OTHER = sjaECC_ERCC0 | sjaECC_ERCC1,
140 sjaECC_DIR = 1<<5, // 1 == RX, 0 == TX
141 sjaECC_SEG_M = (1<<5) -1 // Segment mask, see page 37 of SJA1000 Data Sheet
144 /** Frame format information 0x10 */
145 enum sja1000_PeliCAN_FRM {
146 sjaFRM_FF = 1<<7, // Frame Format 1 == extended, 0 == standard
147 sjaFRM_RTR = 1<<6, // Remote request
148 sjaFRM_DLC_M = (1<<4)-1 // Length Mask
152 /** Interrupt (status) Register 0x03 */
153 enum sja1000_PeliCAN_IR {
154 sjaIR_BEI = 1<<7, // Bus Error Interrupt
155 sjaIR_ALI = 1<<6, // Arbitration Lost Interrupt
156 sjaIR_EPI = 1<<5, // Error Passive Interrupt (entered error passive state or error active state)
157 sjaIR_WUI = 1<<4, // Wake-Up Interrupt
158 sjaIR_DOI = 1<<3, // Data Overrun Interrupt
159 sjaIR_EI = 1<<2, // Error Interrupt
160 sjaIR_TI = 1<<1, // Transmit Interrupt
161 sjaIR_RI = 1 // Receive Interrupt
164 /** Bus Timing 1 Register 0x07 */
170 /** Output Control Register 0x08 */
172 sjaOCR_MODE_BIPHASE = 0,
173 sjaOCR_MODE_TEST = 1,
174 sjaOCR_MODE_NORMAL = 2,
175 sjaOCR_MODE_CLOCK = 3,
176 /// TX0 push-pull not inverted
177 sjaOCR_TX0_LH = 0x18,
178 /// TX1 floating (off)
182 /** Clock Divider register 0x1f */
184 sjaCDR_PELICAN = 1<<7,
185 /// bypass input comparator
187 /// switch TX1 to generate RX INT
188 sjaCDR_RXINPEN = 1<<5,
189 sjaCDR_CLK_OFF = 1<<3,
190 /// f_out = f_osc/(2*(CDR[2:0]+1)) or f_osc if CDR[2:0]==7
191 sjaCDR_CLKOUT_DIV1 = 7,
192 sjaCDR_CLKOUT_DIV2 = 0,
193 sjaCDR_CLKOUT_DIV4 = 1,
194 sjaCDR_CLKOUT_DIV6 = 2,
195 sjaCDR_CLKOUT_DIV8 = 3,
196 sjaCDR_CLKOUT_DIV10 = 4,
197 sjaCDR_CLKOUT_DIV12 = 5,
198 sjaCDR_CLKOUT_DIV14 = 6,
199 sjaCDR_CLKOUT_MASK = 7
202 /** flags for sja1000_baud_rate */
203 #define BTR1_SAM (1<<1)
205 #endif /* SJA1000P_H */