1 /*******************************************************************
2 Components for embedded applications builded for
3 laboratory and medical instruments firmware
5 system_def.h - common cover for definition of hardware adresses,
6 registers, timing and other hardware dependant
7 parts of embedded hardware
9 Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
10 (C) 2002 by PiKRON Ltd. http://www.pikron.com
12 *******************************************************************/
14 #ifndef _SYSTEM_DEF_H_
15 #define _SYSTEM_DEF_H_
18 #include <system_stub.h>
26 #define VER_CODE(major,minor,patch) (major*0x10000+minor*0x100+patch)
27 /* Software version */
28 #define SW_VER_ID "ULMO_1M1I"
29 #define SW_VER_MAJOR 0
30 #define SW_VER_MINOR 2
31 #define SW_VER_PATCH 0
32 #define SW_VER_CODE VER_CODE(SW_VER_MAJOR,SW_VER_MINOR,SW_VER_PATCH)
33 /* Hardware version */
34 #define HW_VER_ID "ULMO_1M1I"
35 #define HW_VER_MAJOR 1
36 #define HW_VER_MINOR 0
37 #define HW_VER_PATCH 0
38 #define HW_VER_CODE VER_CODE(HW_VER_MAJOR,HW_VER_MINOR,HW_VER_PATCH)
39 /* Version of mechanical */
40 #define MECH_VER_ID "ULMO_1M1I"
41 #define MECH_VER_MAJOR 0
42 #define MECH_VER_MINOR 0
43 #define MECH_VER_PATCH 0
44 #define MECH_VER_CODE VER_CODE(MECH_VER_MAJOR,MECH_VER_MINOR,MECH_VER_PATCH)
47 /*--------------------- Clock Configuration ----------------------------------
49 // <e> Clock Configuration
50 // <h> System Controls and Status Register (SCS)
51 // <o1.4> OSCRANGE: Main Oscillator Range Select
52 // <0=> 1 MHz to 20 MHz
53 // <1=> 15 MHz to 24 MHz
54 // <e1.5> OSCEN: Main Oscillator Enable
58 // <h> Clock Source Select Register (CLKSRCSEL)
59 // <o2.0..1> CLKSRC: PLL Clock Source Selection
60 // <0=> Internal RC oscillator
61 // <1=> Main oscillator
62 // <2=> RTC oscillator
65 // <e3> PLL0 Configuration (Main PLL)
66 // <h> PLL0 Configuration Register (PLL0CFG)
67 // <i> F_cco0 = (2 * M * F_in) / N
68 // <i> F_in must be in the range of 32 kHz to 50 MHz
69 // <i> F_cco0 must be in the range of 275 MHz to 550 MHz
70 // <o4.0..14> MSEL: PLL Multiplier Selection
73 // <o4.16..23> NSEL: PLL Divider Selection
79 // <e5> PLL1 Configuration (USB PLL)
80 // <h> PLL1 Configuration Register (PLL1CFG)
81 // <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
82 // <i> F_cco1 = F_osc * M * 2 * P
83 // <i> F_cco1 must be in the range of 156 MHz to 320 MHz
84 // <o6.0..4> MSEL: PLL Multiplier Selection
86 // <i> M Value (for USB maximum value is 4)
87 // <o6.5..6> PSEL: PLL Divider Selection
96 // <h> CPU Clock Configuration Register (CCLKCFG)
97 // <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
101 // <h> USB Clock Configuration Register (USBCLKCFG)
102 // <o8.0..3> USBSEL: Divide Value for USB Clock from PLL1
104 // <i> Divide is USBSEL + 1
107 // <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
108 // <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
109 // <0=> Pclk = Cclk / 4
111 // <2=> Pclk = Cclk / 2
112 // <3=> Pclk = Hclk / 8
113 // <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
114 // <0=> Pclk = Cclk / 4
116 // <2=> Pclk = Cclk / 2
117 // <3=> Pclk = Hclk / 8
118 // <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
119 // <0=> Pclk = Cclk / 4
121 // <2=> Pclk = Cclk / 2
122 // <3=> Pclk = Hclk / 8
123 // <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
124 // <0=> Pclk = Cclk / 4
126 // <2=> Pclk = Cclk / 2
127 // <3=> Pclk = Hclk / 8
128 // <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
129 // <0=> Pclk = Cclk / 4
131 // <2=> Pclk = Cclk / 2
132 // <3=> Pclk = Hclk / 8
133 // <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
134 // <0=> Pclk = Cclk / 4
136 // <2=> Pclk = Cclk / 2
137 // <3=> Pclk = Hclk / 8
138 // <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
139 // <0=> Pclk = Cclk / 4
141 // <2=> Pclk = Cclk / 2
142 // <3=> Pclk = Hclk / 8
143 // <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
144 // <0=> Pclk = Cclk / 4
146 // <2=> Pclk = Cclk / 2
147 // <3=> Pclk = Hclk / 8
148 // <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
149 // <0=> Pclk = Cclk / 4
151 // <2=> Pclk = Cclk / 2
152 // <3=> Pclk = Hclk / 8
153 // <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
154 // <0=> Pclk = Cclk / 4
156 // <2=> Pclk = Cclk / 2
157 // <3=> Pclk = Hclk / 8
158 // <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
159 // <0=> Pclk = Cclk / 4
161 // <2=> Pclk = Cclk / 2
162 // <3=> Pclk = Hclk / 8
163 // <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
164 // <0=> Pclk = Cclk / 4
166 // <2=> Pclk = Cclk / 2
167 // <3=> Pclk = Hclk / 6
168 // <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
169 // <0=> Pclk = Cclk / 4
171 // <2=> Pclk = Cclk / 2
172 // <3=> Pclk = Hclk / 6
173 // <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
174 // <0=> Pclk = Cclk / 4
176 // <2=> Pclk = Cclk / 2
177 // <3=> Pclk = Hclk / 6
180 // <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
181 // <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
182 // <0=> Pclk = Cclk / 4
184 // <2=> Pclk = Cclk / 2
185 // <3=> Pclk = Hclk / 8
186 // <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
187 // <0=> Pclk = Cclk / 4
189 // <2=> Pclk = Cclk / 2
190 // <3=> Pclk = Hclk / 8
191 // <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
192 // <0=> Pclk = Cclk / 4
194 // <2=> Pclk = Cclk / 2
195 // <3=> Pclk = Hclk / 8
196 // <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
197 // <0=> Pclk = Cclk / 4
199 // <2=> Pclk = Cclk / 2
200 // <3=> Pclk = Hclk / 8
201 // <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
202 // <0=> Pclk = Cclk / 4
204 // <2=> Pclk = Cclk / 2
205 // <3=> Pclk = Hclk / 8
206 // <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
207 // <0=> Pclk = Cclk / 4
209 // <2=> Pclk = Cclk / 2
210 // <3=> Pclk = Hclk / 8
211 // <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
212 // <0=> Pclk = Cclk / 4
214 // <2=> Pclk = Cclk / 2
215 // <3=> Pclk = Hclk / 8
216 // <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
217 // <0=> Pclk = Cclk / 4
219 // <2=> Pclk = Cclk / 2
220 // <3=> Pclk = Hclk / 8
221 // <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
222 // <0=> Pclk = Cclk / 4
224 // <2=> Pclk = Cclk / 2
225 // <3=> Pclk = Hclk / 8
226 // <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
227 // <0=> Pclk = Cclk / 4
229 // <2=> Pclk = Cclk / 2
230 // <3=> Pclk = Hclk / 8
231 // <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
232 // <0=> Pclk = Cclk / 4
234 // <2=> Pclk = Cclk / 2
235 // <3=> Pclk = Hclk / 8
236 // <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
237 // <0=> Pclk = Cclk / 4
239 // <2=> Pclk = Cclk / 2
240 // <3=> Pclk = Hclk / 8
241 // <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
242 // <0=> Pclk = Cclk / 4
244 // <2=> Pclk = Cclk / 2
245 // <3=> Pclk = Hclk / 8
246 // <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
247 // <0=> Pclk = Cclk / 4
249 // <2=> Pclk = Cclk / 2
250 // <3=> Pclk = Hclk / 8
253 // <h> Power Control for Peripherals Register (PCONP)
254 // <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
255 // <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
256 // <o11.3> PCUART0: UART 0 power/clock enable
257 // <o11.4> PCUART1: UART 1 power/clock enable
258 // <o11.6> PCPWM1: PWM 1 power/clock enable
259 // <o11.7> PCI2C0: I2C interface 0 power/clock enable
260 // <o11.8> PCSPI: SPI interface power/clock enable
261 // <o11.9> PCRTC: RTC power/clock enable
262 // <o11.10> PCSSP1: SSP interface 1 power/clock enable
263 // <o11.12> PCAD: A/D converter power/clock enable
264 // <o11.13> PCCAN1: CAN controller 1 power/clock enable
265 // <o11.14> PCCAN2: CAN controller 2 power/clock enable
266 // <o11.15> PCGPIO: GPIOs power/clock enable
267 // <o11.16> PCRIT: Repetitive interrupt timer power/clock enable
268 // <o11.17> PCMC: Motor control PWM power/clock enable
269 // <o11.18> PCQEI: Quadrature encoder interface power/clock enable
270 // <o11.19> PCI2C1: I2C interface 1 power/clock enable
271 // <o11.21> PCSSP0: SSP interface 0 power/clock enable
272 // <o11.22> PCTIM2: Timer 2 power/clock enable
273 // <o11.23> PCTIM3: Timer 3 power/clock enable
274 // <o11.24> PCUART2: UART 2 power/clock enable
275 // <o11.25> PCUART3: UART 3 power/clock enable
276 // <o11.26> PCI2C2: I2C interface 2 power/clock enable
277 // <o11.27> PCI2S: I2S interface power/clock enable
278 // <o11.29> PCGPDMA: GP DMA function power/clock enable
279 // <o11.30> PCENET: Ethernet block power/clock enable
280 // <o11.31> PCUSB: USB interface power/clock enable
285 #define CLOCK_SETUP 1
287 #define SCS_Val 0x00000020 /* OSCEN */
288 #define CLKSRCSEL_Val 0x00000001 /* XTAL */
291 #define PLL0CFG_Val 0x0000000B /* 324403200Hz - must be in the range 275HMz-550MHz */
294 #define PLL1CFG_Val 0x00000023
296 #define CCLKCFG_Val 0x00000003 /* pplclk/(CCLKCFG_Val+1)=81100800Hz */
297 #define USBCLKCFG_Val 0x00000000
299 //#define PCLKSEL0_Val 0x00000000 /* all peripherial sysclk/4 */
300 //#define PCLKSEL1_Val 0x00000000
301 //#define PCONP_Val 0x042887DE
303 #define PCONP_CLK_DIV(x) ((x)==0?4:((x)==1?1:((x)==2?2:8)))
305 /*--------------------- Flash Accelerator Configuration ----------------------
307 // <e> Flash Accelerator Configuration
308 // <o1.0..1> FETCHCFG: Fetch Configuration
309 // <0=> Instruction fetches from flash are not buffered
310 // <1=> One buffer is used for all instruction fetch buffering
311 // <2=> All buffers may be used for instruction fetch buffering
312 // <3=> Reserved (do not use this setting)
313 // <o1.2..3> DATACFG: Data Configuration
314 // <0=> Data accesses from flash are not buffered
315 // <1=> One buffer is used for all data access buffering
316 // <2=> All buffers may be used for data access buffering
317 // <3=> Reserved (do not use this setting)
318 // <o1.4> ACCEL: Acceleration Enable
319 // <o1.5> PREFEN: Prefetch Enable
320 // <o1.6> PREFOVR: Prefetch Override
321 // <o1.12..15> FLASHTIM: Flash Access Time
322 // <0=> 1 CPU clock (for CPU clock up to 20 MHz)
323 // <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
324 // <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
325 // <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
326 // <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
327 // <5=> 6 CPU clocks (for any CPU clock)
330 #define FLASH_SETUP 1
331 #define FLASHCFG_Val 0x0000403A
333 /*----------------------------------------------------------------------------
335 *----------------------------------------------------------------------------*/
336 #define XTAL (14745600UL) /* Oscillator frequency */
337 #define OSC_CLK ( XTAL) /* Main oscillator frequency */
338 #define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
339 #define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
344 #define SYS_TIMER_HZ 1000
347 #define BIT(n) (1 << (n))
350 // Port Bit Definitions & Macros: Description - initial conditions
351 #define P0_0_UNUSED_BIT BIT(0) // P0.0 unused - low output
352 #define P0_1_UNUSED_BIT BIT(1) // P0.1 unused - low output
353 #define TXD0_BIT BIT(2) // used by UART0
354 #define RXD0_BIT BIT(3) // used by UART0
355 #define OVER_LOAD_BIT BIT(6) // OVER_LOAD
356 #define P0_7_UNUSED_BIT BIT(7) // P0.7 unused - low output
357 #define P0_8_UNUSED_BIT BIT(8) // P0.8 unused - low output
358 #define P0_9_UNUSED_BIT BIT(9) // P0.9 unused - low output
359 #define P0_10_UNUSED_BIT BIT(10) // P0.10 unused - low output
360 #define P0_11_UNUSED_BIT BIT(11) // P0.11 unused - low output
361 #define IN2_BIT BIT(15) // P0.15 input 2
362 #define IN1_BIT BIT(16) // P0.16 input 1
363 #define IN3_BIT BIT(17) // P0.17 input 3
364 #define IN4_BIT BIT(18) // P0.18 input 4
365 #define RTS1_BIT BIT(22) // P0.22 uDIR
366 #define EXT_TEMP_SENS_BIT BIT(25) // P0.25
367 #define EXT_TEMP_TYPE_BIT BIT(26) // P0.26
368 #define USBDPLUS_BIT BIT(29) // P0.29 USBD+
369 #define USBDMINUS_BIT BIT(30) // P0.30 USBD-
372 // Port Bit Definitions & Macros: Description - initial conditions
373 #define P1_0_UNUSED_BIT BIT(0) // P1.0 unused - low output
374 #define P1_1_UNUSED_BIT BIT(1) // P1.1 unused - low output
375 #define P1_4_UNUSED_BIT BIT(4) // P1.4 unused - low output
376 #define P1_8_UNUSED_BIT BIT(8) // P1.8 unused - low output
377 #define P1_9_UNUSED_BIT BIT(9) // P1.9 unused - low output
378 #define P1_10_UNUSED_BIT BIT(10) // P1.10 unused - low output
379 #define P1_14_UNUSED_BIT BIT(14) // P1.14 unused - low output
380 #define P1_15_UNUSED_BIT BIT(15) // P1.15 unused - low output
381 #define P1_18_UNUSED_BIT BIT(18) // P1.18 unused - low output
382 #define P1_19_UNUSED_BIT BIT(19) // P1.19 unused - low output
383 #define P1_20_UNUSED_BIT BIT(20) // P1.20 unused - low output
384 #define P1_22_UNUSED_BIT BIT(22) // P1.22 unused - low output
385 #define OUT1_BIT BIT(23) // Output 1
386 #define OUT2_BIT BIT(24) // Output 2
387 #define P1_25_UNUSED_BIT BIT(25) // P1.25 unused - low output
388 #define P1_26_UNUSED_BIT BIT(26) // P1.26 unused - low output
389 #define P1_28_UNUSED_BIT BIT(28) // P1.28 unused - low output
390 #define P1_29_UNUSED_BIT BIT(29) // P1.29 unused - low output
391 #define EXT_TEMP_SW_BIT BIT(30) // P1.30
392 #define P1_31_UNUSED_BIT BIT(31) // P1.31 unused - low output
394 // Port Bit Definitions & Macros: Description - initial conditions
395 #define TXD1_BIT BIT(0) // P2.0 TXD
396 #define RXD1_BIT BIT(1) // P2.1 RXD
397 #define P2_2_UNUSED_BIT BIT(2) // P2.2 unused - low output
398 #define P2_3_UNUSED_BIT BIT(3) // P2.3 unused - low output
399 #define DSR1_BIT BIT(4) // P2.4 DSR
400 #define LED1_BIT BIT(5) // P2.5 LED1
401 #define LED2_BIT BIT(6) // P2.6 LED2
402 #define LED3_BIT BIT(7) // P2.7 LED3
403 #define LED4_BIT BIT(8) // P2.8 LED4
404 #define P2_9_UNUSED_BIT BIT(9) // P2.9 unused - low output
405 #define BOOT_BIT BIT(10) // P2.10 Boot input
407 #define P4_28_UNUSED_BIT BIT(28) // P4.28 unused - low output
408 #define P4_29_UNUSED_BIT BIT(29) // P4.29 unused - low output
410 #define P0IO_INPUT_BITS (uint32_t) ( \
417 EXT_TEMP_SENS_BIT | \
422 #define P1IO_INPUT_BITS (uint32_t) ( \
425 #define P2IO_INPUT_BITS (uint32_t) ( \
431 #define P3IO_INPUT_BITS (uint32_t) ( \
434 #define P4IO_INPUT_BITS (uint32_t) ( \
437 #define P0IO_ZERO_BITS (uint32_t) ( \
448 #define P1IO_ZERO_BITS (uint32_t) ( \
468 #define P2IO_ZERO_BITS (uint32_t) ( \
474 #define P3IO_ZERO_BITS (uint32_t) ( \
477 #define P4IO_ZERO_BITS (uint32_t) ( \
482 #define P0IO_ONE_BITS (uint32_t) ( \
484 EXT_TEMP_TYPE_BIT | \
487 #define P1IO_ONE_BITS (uint32_t) ( \
493 #define P2IO_ONE_BITS (uint32_t) ( \
501 #define P3IO_ONE_BITS (uint32_t) ( \
504 #define P4IO_ONE_BITS (uint32_t) ( \
507 #define P0IO_OUTPUT_BITS (uint32_t) ( \
511 #define P1IO_OUTPUT_BITS (uint32_t) ( \
515 #define P2IO_OUTPUT_BITS (uint32_t) ( \
519 #define P3IO_OUTPUT_BITS (uint32_t) ( \
523 #define P4IO_OUTPUT_BITS (uint32_t) ( \
529 /***************************************************************************/
531 #define LED_GP LED2_BIT /* GENREAL PURPOSE LED */
532 #define LED_ERR LED3_BIT
534 /***************************************************************************/
536 #define IN_PORT GPIO0->FIO
537 #define OUT_PORT GPIO1->FIO
538 #define LED_PORT GPIO2->FIO
540 #define CREATE_PORT_NAME_PIN(port) port##PIN
541 #define CREATE_PORT_NAME_CLR(port) port##CLR
542 #define CREATE_PORT_NAME_SET(port) port##SET
544 #define GET_IN_PIN(port,in) ((CREATE_PORT_NAME_PIN(port) & in)?1:0)
545 #define GET_IN_PORT(port) (CREATE_PORT_NAME_PIN(port))
546 #define SET_OUT_PIN(port,out) (CREATE_PORT_NAME_SET(port)=out)
547 #define CLR_OUT_PIN(port,out) (CREATE_PORT_NAME_CLR(port)=out)
549 /***************************************************************************/
551 #define WATCHDOG_ENABLED
552 #define WATCHDOG_TIMEOUT_MS 1000
554 /***************************************************************************/
555 /* uLan configuration */
561 #ifdef ULD_DEFAULT_BUFFER_SIZE
562 #undef ULD_DEFAULT_BUFFER_SIZE
563 #define ULD_DEFAULT_BUFFER_SIZE 0x0800
566 #define UL_DRV_SYSLESS_PORT UART1_BASE
567 #define UL_DRV_SYSLESS_BAUD 19200
568 #define UL_DRV_SYSLESS_IRQ UART1_IRQn
569 #define UL_DRV_SYSLESS_MY_ADR_DEFAULT 1
571 #define watchdog_feed lpc_watchdog_feed
572 #define kvpb_erase lpcisp_kvpb_erase
573 #define kvpb_copy lpcisp_kvpb_copy
574 #define kvpb_flush lpcisp_kvpb_flush
575 #define KVPB_DEFAULT_FLAGS KVPB_DESC_DOUBLE|KVPB_DESC_CHUNKWO
584 #endif /* _SYSTEM_DEF_H_ */