embedded/board/arm/lpc17xx-common/defines/system_def-lmc1.h

   1 /*******************************************************************
   2   Components for embedded applications builded for
   3   laboratory and medical instruments firmware
   4
   5   system_def.h - common cover for definition of hardware adresses,
   6                  registers, timing and other hardware dependant
   7                  parts of embedded hardware
   8
   9   Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
  10             (C) 2002 by PiKRON Ltd. http://www.pikron.com
  11
  12  *******************************************************************/
  13
  14 #ifndef _SYSTEM_DEF_H_
  15 #define _SYSTEM_DEF_H_
  16
  17 #include <types.h>
  18 #include <system_stub.h>
  19 #include <LPC17xx.h>
  20 #include <bspbase.h>
  21 #include <hal_gpio_def.h>
  22
  23 #ifndef MACH_LPC17XX
  24 #define MACH_LPC17XX
  25 #endif
  26
  27 #ifndef NULL
  28 #define NULL    0
  29 #endif
  30
  31 #define VER_CODE(major,minor,patch) (major*0x10000+minor*0x100+patch)
  32 /* Software version */
  33 #define SW_VER_ID       "LMC1"
  34 #define SW_VER_MAJOR    0
  35 #define SW_VER_MINOR    1
  36 #define SW_VER_PATCH    0
  37 #define SW_VER_CODE     VER_CODE(SW_VER_MAJOR,SW_VER_MINOR,SW_VER_PATCH)
  38 /* Hardware version */
  39 #define HW_VER_ID       "LMC1"
  40 #define HW_VER_MAJOR    1
  41 #define HW_VER_MINOR    0
  42 #define HW_VER_PATCH    0
  43 #define HW_VER_CODE     VER_CODE(HW_VER_MAJOR,HW_VER_MINOR,HW_VER_PATCH)
  44 /* Version of mechanical  */
  45 #define MECH_VER_ID     "LMC1"
  46 #define MECH_VER_MAJOR  0
  47 #define MECH_VER_MINOR  0
  48 #define MECH_VER_PATCH  0
  49 #define MECH_VER_CODE   VER_CODE(MECH_VER_MAJOR,MECH_VER_MINOR,MECH_VER_PATCH)
  50
  51
  52 /*--------------------- Clock Configuration ----------------------------------
  53 //
  54 // <e> Clock Configuration
  55 //   <h> System Controls and Status Register (SCS)
  56 //     <o1.4>    OSCRANGE: Main Oscillator Range Select
  57 //                     <0=>  1 MHz to 20 MHz
  58 //                     <1=> 15 MHz to 24 MHz
  59 //     <e1.5>       OSCEN: Main Oscillator Enable
  60 //     </e>
  61 //   </h>
  62 //
  63 //   <h> Clock Source Select Register (CLKSRCSEL)
  64 //     <o2.0..1>   CLKSRC: PLL Clock Source Selection
  65 //                     <0=> Internal RC oscillator
  66 //                     <1=> Main oscillator
  67 //                     <2=> RTC oscillator
  68 //   </h>
  69 //
  70 //   <e3> PLL0 Configuration (Main PLL)
  71 //     <h> PLL0 Configuration Register (PLL0CFG)
  72 //                     <i> F_cco0 = (2 * M * F_in) / N
  73 //                     <i> F_in must be in the range of 32 kHz to 50 MHz
  74 //                     <i> F_cco0 must be in the range of 275 MHz to 550 MHz
  75 //       <o4.0..14>  MSEL: PLL Multiplier Selection
  76 //                     <6-32768><#-1>
  77 //                     <i> M Value
  78 //       <o4.16..23> NSEL: PLL Divider Selection
  79 //                     <1-256><#-1>
  80 //                     <i> N Value
  81 //     </h>
  82 //   </e>
  83 //
  84 //   <e5> PLL1 Configuration (USB PLL)
  85 //     <h> PLL1 Configuration Register (PLL1CFG)
  86 //                     <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
  87 //                     <i> F_cco1 = F_osc * M * 2 * P
  88 //                     <i> F_cco1 must be in the range of 156 MHz to 320 MHz
  89 //       <o6.0..4>   MSEL: PLL Multiplier Selection
  90 //                     <1-32><#-1>
  91 //                     <i> M Value (for USB maximum value is 4)
  92 //       <o6.5..6>   PSEL: PLL Divider Selection
  93 //                     <0=> 1
  94 //                     <1=> 2
  95 //                     <2=> 4
  96 //                     <3=> 8
  97 //                     <i> P Value
  98 //     </h>
  99 //   </e>
 100 //
 101 //   <h> CPU Clock Configuration Register (CCLKCFG)
 102 //     <o7.0..7>  CCLKSEL: Divide Value for CPU Clock from PLL0
 103 //                     <2-256:2><#-1>
 104 //   </h>
 105 //
 106 //   <h> USB Clock Configuration Register (USBCLKCFG)
 107 //     <o8.0..3>   USBSEL: Divide Value for USB Clock from PLL1
 108 //                     <0-15>
 109 //                     <i> Divide is USBSEL + 1
 110 //   </h>
 111 //
 112 //   <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
 113 //     <o9.0..1>    PCLK_WDT: Peripheral Clock Selection for WDT
 114 //                     <0=> Pclk = Cclk / 4
 115 //                     <1=> Pclk = Cclk
 116 //                     <2=> Pclk = Cclk / 2
 117 //                     <3=> Pclk = Hclk / 8
 118 //     <o9.2..3>    PCLK_TIMER0: Peripheral Clock Selection for TIMER0
 119 //                     <0=> Pclk = Cclk / 4
 120 //                     <1=> Pclk = Cclk
 121 //                     <2=> Pclk = Cclk / 2
 122 //                     <3=> Pclk = Hclk / 8
 123 //     <o9.4..5>    PCLK_TIMER1: Peripheral Clock Selection for TIMER1
 124 //                     <0=> Pclk = Cclk / 4
 125 //                     <1=> Pclk = Cclk
 126 //                     <2=> Pclk = Cclk / 2
 127 //                     <3=> Pclk = Hclk / 8
 128 //     <o9.6..7>    PCLK_UART0: Peripheral Clock Selection for UART0
 129 //                     <0=> Pclk = Cclk / 4
 130 //                     <1=> Pclk = Cclk
 131 //                     <2=> Pclk = Cclk / 2
 132 //                     <3=> Pclk = Hclk / 8
 133 //     <o9.8..9>    PCLK_UART1: Peripheral Clock Selection for UART1
 134 //                     <0=> Pclk = Cclk / 4
 135 //                     <1=> Pclk = Cclk
 136 //                     <2=> Pclk = Cclk / 2
 137 //                     <3=> Pclk = Hclk / 8
 138 //     <o9.12..13>  PCLK_PWM1: Peripheral Clock Selection for PWM1
 139 //                     <0=> Pclk = Cclk / 4
 140 //                     <1=> Pclk = Cclk
 141 //                     <2=> Pclk = Cclk / 2
 142 //                     <3=> Pclk = Hclk / 8
 143 //     <o9.14..15>  PCLK_I2C0: Peripheral Clock Selection for I2C0
 144 //                     <0=> Pclk = Cclk / 4
 145 //                     <1=> Pclk = Cclk
 146 //                     <2=> Pclk = Cclk / 2
 147 //                     <3=> Pclk = Hclk / 8
 148 //     <o9.16..17>  PCLK_SPI: Peripheral Clock Selection for SPI
 149 //                     <0=> Pclk = Cclk / 4
 150 //                     <1=> Pclk = Cclk
 151 //                     <2=> Pclk = Cclk / 2
 152 //                     <3=> Pclk = Hclk / 8
 153 //     <o9.20..21>  PCLK_SSP1: Peripheral Clock Selection for SSP1
 154 //                     <0=> Pclk = Cclk / 4
 155 //                     <1=> Pclk = Cclk
 156 //                     <2=> Pclk = Cclk / 2
 157 //                     <3=> Pclk = Hclk / 8
 158 //     <o9.22..23>  PCLK_DAC: Peripheral Clock Selection for DAC
 159 //                     <0=> Pclk = Cclk / 4
 160 //                     <1=> Pclk = Cclk
 161 //                     <2=> Pclk = Cclk / 2
 162 //                     <3=> Pclk = Hclk / 8
 163 //     <o9.24..25>  PCLK_ADC: Peripheral Clock Selection for ADC
 164 //                     <0=> Pclk = Cclk / 4
 165 //                     <1=> Pclk = Cclk
 166 //                     <2=> Pclk = Cclk / 2
 167 //                     <3=> Pclk = Hclk / 8
 168 //     <o9.26..27>  PCLK_CAN1: Peripheral Clock Selection for CAN1
 169 //                     <0=> Pclk = Cclk / 4
 170 //                     <1=> Pclk = Cclk
 171 //                     <2=> Pclk = Cclk / 2
 172 //                     <3=> Pclk = Hclk / 6
 173 //     <o9.28..29>  PCLK_CAN2: Peripheral Clock Selection for CAN2
 174 //                     <0=> Pclk = Cclk / 4
 175 //                     <1=> Pclk = Cclk
 176 //                     <2=> Pclk = Cclk / 2
 177 //                     <3=> Pclk = Hclk / 6
 178 //     <o9.30..31>  PCLK_ACF: Peripheral Clock Selection for ACF
 179 //                     <0=> Pclk = Cclk / 4
 180 //                     <1=> Pclk = Cclk
 181 //                     <2=> Pclk = Cclk / 2
 182 //                     <3=> Pclk = Hclk / 6
 183 //   </h>
 184 //
 185 //   <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
 186 //     <o10.0..1>   PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
 187 //                     <0=> Pclk = Cclk / 4
 188 //                     <1=> Pclk = Cclk
 189 //                     <2=> Pclk = Cclk / 2
 190 //                     <3=> Pclk = Hclk / 8
 191 //     <o10.2..3>   PCLK_GPIO: Peripheral Clock Selection for GPIOs
 192 //                     <0=> Pclk = Cclk / 4
 193 //                     <1=> Pclk = Cclk
 194 //                     <2=> Pclk = Cclk / 2
 195 //                     <3=> Pclk = Hclk / 8
 196 //     <o10.4..5>   PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
 197 //                     <0=> Pclk = Cclk / 4
 198 //                     <1=> Pclk = Cclk
 199 //                     <2=> Pclk = Cclk / 2
 200 //                     <3=> Pclk = Hclk / 8
 201 //     <o10.6..7>   PCLK_I2C1: Peripheral Clock Selection for I2C1
 202 //                     <0=> Pclk = Cclk / 4
 203 //                     <1=> Pclk = Cclk
 204 //                     <2=> Pclk = Cclk / 2
 205 //                     <3=> Pclk = Hclk / 8
 206 //     <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
 207 //                     <0=> Pclk = Cclk / 4
 208 //                     <1=> Pclk = Cclk
 209 //                     <2=> Pclk = Cclk / 2
 210 //                     <3=> Pclk = Hclk / 8
 211 //     <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
 212 //                     <0=> Pclk = Cclk / 4
 213 //                     <1=> Pclk = Cclk
 214 //                     <2=> Pclk = Cclk / 2
 215 //                     <3=> Pclk = Hclk / 8
 216 //     <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
 217 //                     <0=> Pclk = Cclk / 4
 218 //                     <1=> Pclk = Cclk
 219 //                     <2=> Pclk = Cclk / 2
 220 //                     <3=> Pclk = Hclk / 8
 221 //     <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
 222 //                     <0=> Pclk = Cclk / 4
 223 //                     <1=> Pclk = Cclk
 224 //                     <2=> Pclk = Cclk / 2
 225 //                     <3=> Pclk = Hclk / 8
 226 //     <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
 227 //                     <0=> Pclk = Cclk / 4
 228 //                     <1=> Pclk = Cclk
 229 //                     <2=> Pclk = Cclk / 2
 230 //                     <3=> Pclk = Hclk / 8
 231 //     <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
 232 //                     <0=> Pclk = Cclk / 4
 233 //                     <1=> Pclk = Cclk
 234 //                     <2=> Pclk = Cclk / 2
 235 //                     <3=> Pclk = Hclk / 8
 236 //     <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
 237 //                     <0=> Pclk = Cclk / 4
 238 //                     <1=> Pclk = Cclk
 239 //                     <2=> Pclk = Cclk / 2
 240 //                     <3=> Pclk = Hclk / 8
 241 //     <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
 242 //                     <0=> Pclk = Cclk / 4
 243 //                     <1=> Pclk = Cclk
 244 //                     <2=> Pclk = Cclk / 2
 245 //                     <3=> Pclk = Hclk / 8
 246 //     <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
 247 //                     <0=> Pclk = Cclk / 4
 248 //                     <1=> Pclk = Cclk
 249 //                     <2=> Pclk = Cclk / 2
 250 //                     <3=> Pclk = Hclk / 8
 251 //     <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
 252 //                     <0=> Pclk = Cclk / 4
 253 //                     <1=> Pclk = Cclk
 254 //                     <2=> Pclk = Cclk / 2
 255 //                     <3=> Pclk = Hclk / 8
 256 //   </h>
 257 //
 258 //   <h> Power Control for Peripherals Register (PCONP)
 259 //     <o11.1>      PCTIM0: Timer/Counter 0 power/clock enable
 260 //     <o11.2>      PCTIM1: Timer/Counter 1 power/clock enable
 261 //     <o11.3>      PCUART0: UART 0 power/clock enable
 262 //     <o11.4>      PCUART1: UART 1 power/clock enable
 263 //     <o11.6>      PCPWM1: PWM 1 power/clock enable
 264 //     <o11.7>      PCI2C0: I2C interface 0 power/clock enable
 265 //     <o11.8>      PCSPI: SPI interface power/clock enable
 266 //     <o11.9>      PCRTC: RTC power/clock enable
 267 //     <o11.10>     PCSSP1: SSP interface 1 power/clock enable
 268 //     <o11.12>     PCAD: A/D converter power/clock enable
 269 //     <o11.13>     PCCAN1: CAN controller 1 power/clock enable
 270 //     <o11.14>     PCCAN2: CAN controller 2 power/clock enable
 271 //     <o11.15>     PCGPIO: GPIOs power/clock enable
 272 //     <o11.16>     PCRIT: Repetitive interrupt timer power/clock enable
 273 //     <o11.17>     PCMC: Motor control PWM power/clock enable
 274 //     <o11.18>     PCQEI: Quadrature encoder interface power/clock enable
 275 //     <o11.19>     PCI2C1: I2C interface 1 power/clock enable
 276 //     <o11.21>     PCSSP0: SSP interface 0 power/clock enable
 277 //     <o11.22>     PCTIM2: Timer 2 power/clock enable
 278 //     <o11.23>     PCTIM3: Timer 3 power/clock enable
 279 //     <o11.24>     PCUART2: UART 2 power/clock enable
 280 //     <o11.25>     PCUART3: UART 3 power/clock enable
 281 //     <o11.26>     PCI2C2: I2C interface 2 power/clock enable
 282 //     <o11.27>     PCI2S: I2S interface power/clock enable
 283 //     <o11.29>     PCGPDMA: GP DMA function power/clock enable
 284 //     <o11.30>     PCENET: Ethernet block power/clock enable
 285 //     <o11.31>     PCUSB: USB interface power/clock enable
 286 //   </h>
 287 // </e>
 288 */
 289
 290 #define CLOCK_SETUP           1
 291
 292 #define SCS_Val               0x00000020        /* OSCEN */
 293 #define CLKSRCSEL_Val         0x00000001        /* XTAL */
 294
 295 #define PLL0_SETUP            1
 296 #define PLL0CFG_Val           0x0000000B        /* 288000000Hz - must be in the range 275HMz-550MHz */
 297
 298 #define PLL1_SETUP            0
 299 #define PLL1CFG_Val           0x00000023
 300
 301 #define CCLKCFG_Val           0x00000003        /* ppl0clk/(CCLKCFG_Val+1)=72000000Hz */
 302 #define USBCLKCFG_Val         0x00000005        /* divide ppl0clk by 6 to 48MHz */
 303
 304 //#define PCLKSEL0_Val          0x00000000        /* all peripherial sysclk/4 */
 305 //#define PCLKSEL1_Val          0x00000000
 306 //#define PCONP_Val             0x042887DE
 307
 308 #define PCONP_CLK_DIV(x) ((x)==0?4:((x)==1?1:((x)==2?2:8)))
 309
 310 /*--------------------- Flash Accelerator Configuration ----------------------
 311 //
 312 // <e> Flash Accelerator Configuration
 313 //   <o1.0..1>   FETCHCFG: Fetch Configuration
 314 //               <0=> Instruction fetches from flash are not buffered
 315 //               <1=> One buffer is used for all instruction fetch buffering
 316 //               <2=> All buffers may be used for instruction fetch buffering
 317 //               <3=> Reserved (do not use this setting)
 318 //   <o1.2..3>   DATACFG: Data Configuration
 319 //               <0=> Data accesses from flash are not buffered
 320 //               <1=> One buffer is used for all data access buffering
 321 //               <2=> All buffers may be used for data access buffering
 322 //               <3=> Reserved (do not use this setting)
 323 //   <o1.4>      ACCEL: Acceleration Enable
 324 //   <o1.5>      PREFEN: Prefetch Enable
 325 //   <o1.6>      PREFOVR: Prefetch Override
 326 //   <o1.12..15> FLASHTIM: Flash Access Time
 327 //               <0=> 1 CPU clock (for CPU clock up to 20 MHz)
 328 //               <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
 329 //               <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
 330 //               <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
 331 //               <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
 332 //               <5=> 6 CPU clocks (for any CPU clock)
 333 // </e>
 334 */
 335 #define FLASH_SETUP           1
 336 #define FLASHCFG_Val          0x0000403A
 337
 338 /*----------------------------------------------------------------------------
 339   Define clocks
 340  *----------------------------------------------------------------------------*/
 341 #define XTAL        (12000000UL)        /* Oscillator frequency               */
 342 #define OSC_CLK     (      XTAL)        /* Main oscillator frequency          */
 343 #define RTC_CLK     (   32000UL)        /* RTC oscillator frequency           */
 344 #define IRC_OSC     ( 4000000UL)        /* Internal RC oscillator frequency   */
 345
 346 #define SYS_TIMER_HZ        1000
 347
 348 #ifndef BIT
 349 #define BIT(n)              (1 << (n))
 350 #endif
 351
 352 // Port Bit Definitions & Macros:    Description - initial conditions
 353 #define CAN1_RX_BIT         BIT(0)      // CAN1 RX
 354 #define CAN1_TX_BIT         BIT(1)      // CAN1 TX
 355 #define TXD0_BIT            BIT(2)      // used by UART0
 356 #define RXD0_BIT            BIT(3)      // used by UART0
 357 #define CAN2_RX_BIT         BIT(4)      // CAN2 RX
 358 #define CAN2_TX_BIT         BIT(5)      // CAN2 TX
 359 #define LED2_BIT            BIT(6)      // active low/SSEL1
 360 #define LED2_PIN            PORT_PIN(0,6,PORT_CONF_GPIO_OUT_LO)
 361 #define SSP1_CS0_BIT        BIT(6)      // active low/ LMC_GRAD CS
 362 #define SSP1_CS0_PIN        PORT_PIN(0,6,PORT_CONF_GPIO_OUT_HI)
 363 #define SCK1_BIT            BIT(7)      // clock SSP1 to gradient valves
 364 #define SCK1_PIN            PORT_PIN(0,7,PORT_CONF_FNC_2|PORT_CONF_OUT_LO_NORM)
 365 #define MISO1_BIT           BIT(8)      // master input
 366 #define MISO1_PIN           PORT_PIN(0,8,PORT_CONF_FNC_2|PORT_CONF_IN_PU)
 367 #define MOSI1_BIT           BIT(9)      // master output
 368 #define MOSI1_PIN           PORT_PIN(0,9,PORT_CONF_FNC_2|PORT_CONF_OUT_LO_NORM)
 369 #define P0_10_UNUSED_BIT    BIT(10)     // P0.10 unused (SDA2/TXD2)
 370 #define P0_11_UNUSED_BIT    BIT(11)     // P0.11 unused (SCL2/RXD2)
 371 #define SCK0_BIT            BIT(15)     // clock SSP0 to display panel
 372 #define SCK0_PIN            PORT_PIN(0,15,PORT_CONF_FNC_2|PORT_CONF_OUT_LO_NORM)
 373 #define SSEL0_BIT           BIT(16)     // slave select SSP0
 374 #define SSP0_CS0_BIT        BIT(16)     // slave select SSP0 / display chip select
 375 #define SSP0_CS0_PIN        PORT_PIN(0,16,PORT_CONF_GPIO_OUT_HI)
 376 #define MISO0_BIT           BIT(17)     // master input SSP0
 377 #define MISO0_PIN           PORT_PIN(0,17,PORT_CONF_FNC_2|PORT_CONF_IN_PU)
 378 #define MOSI0_BIT           BIT(18)     // master output SSP0
 379 #define MOSI0_PIN           PORT_PIN(0,18,PORT_CONF_FNC_2|PORT_CONF_OUT_LO_NORM)
 380 #define SDA1_BIT            BIT(19)     // I2C data - memory/connector
 381 #define SCL1_BIT            BIT(20)     // I2C clock
 382 #define SSP0_CS1_BIT        BIT(21)     // chip select 1 SSP0/ A/D for display
 383 #define SSP0_CS1_PIN        PORT_PIN(0,21,PORT_CONF_GPIO_OUT_HI)
 384 #define SSP0_CS2_BIT        BIT(22)     // chip select 2 SSP0 for keyboard and LED
 385 #define SSP0_CS2_PIN        PORT_PIN(0,22,PORT_CONF_GPIO_OUT_HI)
 386 #define ADC0_BIT            BIT(23)     // ADC motor current
 387 #define ADC0_PIN            PORT_PIN(0,23,PORT_CONF_FNC_1|PORT_CONF_DIR_IN)
 388 #define ADC1_BIT            BIT(24)     // ADC motor current
 389 #define ADC1_PIN            PORT_PIN(0,24,PORT_CONF_FNC_1|PORT_CONF_DIR_IN)
 390 #define ADC2_BIT            BIT(25)     // ADC motor current
 391 #define ADC2_PIN            PORT_PIN(0,25,PORT_CONF_FNC_1|PORT_CONF_DIR_IN)
 392 #define ADC3_BIT            BIT(26)     // ADC motor current
 393 #define ADC3_PIN            PORT_PIN(0,26,PORT_CONF_FNC_1|PORT_CONF_DIR_IN)
 394 #define P0_27_UNUSED_BIT    BIT(27)     // P0.27 unused
 395 #define P0_28_UNUSED_BIT    BIT(28)     // P0.28 unused
 396 #define USBDPLUS_BIT        BIT(29)     // P0.29 USBD+
 397 #define USBDMINUS_BIT       BIT(30)     // P0.30 USBD-
 398
 399
 400 // Port Bit Definitions & Macros:    Description - initial conditions
 401
 402 #define P1_ETH_BITS         (BIT(0)|BIT(1)|BIT(4)|BIT(8)|BIT(9)|\
 403                              BIT(10)|BIT(14)|BIT(15)|BIT(16)|BIT(17))
 404
 405 #define P1_0_UNUSED_BIT     BIT(0)      // P1.0 unused - low output
 406 #define P1_1_UNUSED_BIT     BIT(1)      // P1.1 unused - low output
 407 #define P1_4_UNUSED_BIT     BIT(4)      // P1.4 unused - low output
 408 #define P1_8_UNUSED_BIT     BIT(8)      // P1.8 unused - low output
 409 #define P1_9_UNUSED_BIT     BIT(9)      // P1.9 unused - low output
 410 #define P1_10_UNUSED_BIT    BIT(10)     // P1.10 unused - low output
 411 #define P1_14_UNUSED_BIT    BIT(14)     // P1.14 unused - low output
 412 #define P1_15_UNUSED_BIT    BIT(15)     // P1.15 unused - low output
 413 #define PWM1_BIT            BIT(18)     // motor pwm 0 / ADC0
 414 #define PWM1_PIN            PORT_PIN(1,18,PORT_CONF_FNC_2|PORT_CONF_OUT_LO_NORM)
 415 #define BLDC_HAL_A_BIT      BIT(19)     // motor HAL input A
 416 #define BLDC_HAL_A_PIN      PORT_PIN(1,19,PORT_CONF_GPIO_IN_PU)
 417 #define IRC_A_BIT           BIT(20)     // motor IRC channel A (MCI0)
 418 #define IRC_M_BIT           BIT(21)     // motor IRC channel mark (GPIO)
 419 #define IRC_M_PIN           PORT_PIN(1,21,PORT_CONF_FNC_1|PORT_CONF_IN_PU)
 420 #define BLDC_HAL_B_BIT      BIT(22)     // motor HAL input B
 421 #define BLDC_HAL_B_PIN      PORT_PIN(1,22,PORT_CONF_GPIO_IN_PU)
 422 #define IRC_B_BIT           BIT(23)     // motor IRC channel B (MCI1)
 423 #define IRC_I_BIT           BIT(24)     // motor IRC index (MCI2)
 424 #define BLDC_HAL_C_BIT      BIT(25)     // motor HAL input C
 425 #define BLDC_HAL_C_PIN      PORT_PIN(1,25,PORT_CONF_GPIO_IN_PU)
 426 #define PWM1_EN_BIT         BIT(26)     // motor pwm 0 enable
 427 #define PWM1_EN_PIN         PORT_PIN(1,26,PORT_CONF_GPIO_OUT_LO)
 428 #define PWM2_EN_BIT         BIT(27)     // motor pwm 1 enable
 429 #define PWM2_EN_PIN         PORT_PIN(1,27,PORT_CONF_GPIO_OUT_LO)
 430 #define PWM4_EN_BIT         BIT(28)     // motor pwm 2 enable
 431 #define PWM4_EN_PIN         PORT_PIN(1,28,PORT_CONF_GPIO_OUT_LO)
 432 #define PWM6_EN_BIT         BIT(29)     // motor pwm 3 enable
 433 #define PWM6_EN_PIN         PORT_PIN(1,29,PORT_CONF_GPIO_OUT_LO)
 434 #define ADC4_BIT            BIT(30)     // ADC4 tensometer
 435 #define ADC4_PIN            PORT_PIN(1,30,PORT_CONF_FNC_3|PORT_CONF_DIR_IN)
 436 #define ADC5_BIT            BIT(31)     // ADC5 external input
 437 #define ADC5_PIN            PORT_PIN(1,31,PORT_CONF_FNC_3|PORT_CONF_DIR_IN)
 438
 439 // Port Bit Definitions & Macros:    Description - initial conditions
 440 #define TXD1_BIT            BIT(0)      // P2.0 TXD
 441 #define RXD1_BIT            BIT(1)      // P2.1 RXD
 442 #define CTS1_BIT            BIT(2)      // P2.2 CTS connected to RXD1
 443 #define PWM4_BIT            BIT(3)      // P2.3 motor pwm 2 / ADC2
 444 #define PWM4_PIN            PORT_PIN(2,3,PORT_CONF_FNC_1|PORT_CONF_OUT_LO_NORM)
 445 #define DSR1_BIT            BIT(4)      // P2.4 DSR connected to TXD1
 446 #define PWM6_BIT            BIT(5)      // P2.5 motor pwm 3 / ADC3
 447 #define PWM6_PIN            PORT_PIN(2,5,PORT_CONF_FNC_1|PORT_CONF_OUT_LO_NORM)
 448 #define LED1_BIT            BIT(6)      // P2.6 LED1 - error
 449 #define LED1_PIN            PORT_PIN(2,6,PORT_CONF_GPIO_OUT_LO)
 450 #define RTS1_BIT            BIT(7)      // P2.7 RTS1 used as DIR1
 451 #define AUX_OUT2_BIT        BIT(8)      // P2.8 auxual TLL port
 452 #define AUX_OUT2_PIN        PORT_PIN(2,8,PORT_CONF_GPIO_OUT_HI)
 453 #define USB_CONNECT_BIT     BIT(9)      // P2.9 USB output for soft connect
 454 #define BOOT_BIT            BIT(10)     // P2.10 Boot input
 455 #define AUX_IN2_BIT         BIT(11)     // P2.11 auxual TLL port
 456 #define AUX_IN2_PIN         PORT_PIN(2,11,PORT_CONF_GPIO_IN_PU)
 457 #define AUX_OUT4_BIT        BIT(12)     // P2.12 auxual TLL port
 458 #define AUX_OUT4_PIN        PORT_PIN(2,12,PORT_CONF_GPIO_OUT_HI)
 459 #define ETH_PD_IRQ_BIT      BIT(13)     // P2.13 power down/int
 460
 461 // Port Bit Definitions & Macros:    Description - initial conditions
 462 #define PWM2_BIT            BIT(25)     // P3.25 motor pwm 1 / ADC1
 463 #define PWM2_PIN            PORT_PIN(3,25,PORT_CONF_FNC_3|PORT_CONF_OUT_LO_NORM)
 464 #define AUX_OUT1_BIT        BIT(26)     // P3.26 auxual TLL port
 465 #define AUX_OUT1_PIN        PORT_PIN(3,26,PORT_CONF_GPIO_OUT_HI)
 466
 467 // Port Bit Definitions & Macros:    Description - initial conditions
 468 #define AUX_OUT3_BIT        BIT(28)     // P4.28 auxual TLL port / TXD3
 469 #define AUX_OUT3_PIN        PORT_PIN(4,28,PORT_CONF_GPIO_OUT_HI)
 470 #define AUX_IN1_BIT         BIT(29)     // P4.29 auxual TLL port / RXD3
 471 #define AUX_IN1_PIN         PORT_PIN(4,29,PORT_CONF_GPIO_IN_PU)
 472
 473 #define P0IO_INPUT_BITS      (uint32_t) ( \
 474                                          CAN1_RX_BIT | \
 475                                          RXD0_BIT | \
 476                                          CAN2_RX_BIT | \
 477                                          MISO1_BIT | \
 478                                          P0_10_UNUSED_BIT | \
 479                                          P0_11_UNUSED_BIT | \
 480                                          MISO0_BIT | \
 481                                          SDA1_BIT | \
 482                                          SCL1_BIT | \
 483                                          ADC0_BIT | \
 484                                          ADC1_BIT | \
 485                                          ADC2_BIT | \
 486                                          ADC3_BIT | \
 487                                          USBDPLUS_BIT | \
 488                                          USBDMINUS_BIT | \
 489                                          0 )
 490
 491 #define P1IO_INPUT_BITS      (uint32_t) ( \
 492                                          P1_ETH_BITS | \
 493                                          BLDC_HAL_A_BIT | \
 494                                          IRC_A_BIT | \
 495                                          IRC_M_BIT | \
 496                                          BLDC_HAL_B_BIT | \
 497                                          IRC_B_BIT | \
 498                                          IRC_I_BIT | \
 499                                          BLDC_HAL_C_BIT | \
 500                                          ADC4_BIT | \
 501                                          ADC5_BIT | \
 502                                          0 )
 503
 504 #define P2IO_INPUT_BITS      (uint32_t) ( \
 505                                          RXD1_BIT | \
 506                                          CTS1_BIT | \
 507                                          DSR1_BIT | \
 508                                          BOOT_BIT | \
 509                                          AUX_IN2_BIT | \
 510                                          ETH_PD_IRQ_BIT | \
 511                                          0 )
 512
 513 #define P3IO_INPUT_BITS      (uint32_t) ( \
 514                                          0 )
 515
 516 #define P4IO_INPUT_BITS      (uint32_t) ( \
 517                                          AUX_IN1_BIT | \
 518                                          0 )
 519
 520 #define P0IO_ZERO_BITS       (uint32_t) ( \
 521                                          P0_27_UNUSED_BIT | \
 522                                          P0_28_UNUSED_BIT | \
 523                                          0 )
 524
 525 #define P1IO_ZERO_BITS       (uint32_t) ( \
 526                                          PWM1_BIT | \
 527                                          PWM1_EN_BIT | \
 528                                          PWM2_EN_BIT | \
 529                                          PWM4_EN_BIT | \
 530                                          PWM6_EN_BIT | \
 531                                          0 )
 532
 533 #define P2IO_ZERO_BITS       (uint32_t) ( \
 534                                          PWM4_BIT | \
 535                                          PWM6_BIT | \
 536                                          0 )
 537
 538 #define P3IO_ZERO_BITS       (uint32_t) ( \
 539                                          PWM2_BIT | \
 540                                          0 )
 541
 542 #define P4IO_ZERO_BITS       (uint32_t) ( \
 543                                          0 )
 544
 545 #define P0IO_ONE_BITS        (uint32_t) ( \
 546                                          CAN1_TX_BIT | \
 547                                          TXD0_BIT | \
 548                                          CAN2_TX_BIT | \
 549                                          LED2_BIT | \
 550                                          SCK1_BIT | \
 551                                          MOSI1_BIT | \
 552                                          SCK0_BIT | \
 553                                          SSEL0_BIT | \
 554                                          MOSI0_BIT | \
 555                                          SSP0_CS0_BIT | \
 556                                          SSP0_CS1_BIT | \
 557                                          0 )
 558
 559 #define P1IO_ONE_BITS        (uint32_t) ( \
 560                                          0 )
 561
 562 #define P2IO_ONE_BITS        (uint32_t) ( \
 563                                          TXD1_BIT | \
 564                                          LED1_BIT | \
 565                                          RTS1_BIT | \
 566                                          AUX_OUT2_BIT | \
 567                                          USB_CONNECT_BIT | \
 568                                          AUX_OUT4_BIT | \
 569                                          0 )
 570
 571 #define P3IO_ONE_BITS        (uint32_t) ( \
 572                                          AUX_OUT1_BIT | \
 573                                          0 )
 574
 575 #define P4IO_ONE_BITS        (uint32_t) ( \
 576                                          AUX_OUT3_BIT | \
 577                                          0 )
 578
 579 #define P0IO_OUTPUT_BITS     (uint32_t) ( \
 580                                          P0IO_ZERO_BITS | \
 581                                          P0IO_ONE_BITS )
 582
 583 #define P1IO_OUTPUT_BITS     (uint32_t) ( \
 584                                          P1IO_ZERO_BITS | \
 585                                          P1IO_ONE_BITS )
 586
 587 #define P2IO_OUTPUT_BITS     (uint32_t) ( \
 588                                          P2IO_ZERO_BITS | \
 589                                          P2IO_ONE_BITS )
 590
 591 #define P3IO_OUTPUT_BITS     (uint32_t) ( \
 592                                          P3IO_ZERO_BITS | \
 593                                          P3IO_ONE_BITS )
 594
 595 #define P4IO_OUTPUT_BITS     (uint32_t) ( \
 596                                          P4IO_ZERO_BITS | \
 597                                          P4IO_ONE_BITS )
 598
 599
 600
 601 /***************************************************************************/
 602 /* io functions */
 603 #define LED_GP                  LED2_BIT  /* GENREAL PURPOSE LED */
 604 #define LED_ERR                 LED1_BIT
 605
 606 /***************************************************************************/
 607 /* io functions */
 608 #define IN_PORT                 GPIO0->FIO
 609 #define OUT_PORT                GPIO1->FIO
 610 #define LED_PORT                GPIO2->FIO
 611
 612 #define CREATE_PORT_NAME_PIN(port) port##PIN
 613 #define CREATE_PORT_NAME_CLR(port) port##CLR
 614 #define CREATE_PORT_NAME_SET(port) port##SET
 615
 616 #define GET_IN_PIN(port,in)     ((CREATE_PORT_NAME_PIN(port) & in)?1:0)
 617 #define GET_IN_PORT(port)       (CREATE_PORT_NAME_PIN(port))
 618 #define SET_OUT_PIN(port,out)   (CREATE_PORT_NAME_SET(port)=out)
 619 #define CLR_OUT_PIN(port,out)   (CREATE_PORT_NAME_CLR(port)=out)
 620
 621 /***************************************************************************/
 622 /* watchdog */
 623 #define WATCHDOG_ENABLED
 624 #define WATCHDOG_TIMEOUT_MS     1000
 625
 626 /***************************************************************************/
 627 /* uLan configuration */
 628
 629 #ifdef UL_LOG_ENABLE
 630   #undef UL_LOG_ENABLE
 631 #endif
 632
 633 #ifdef ULD_DEFAULT_BUFFER_SIZE
 634   #undef ULD_DEFAULT_BUFFER_SIZE
 635   #define ULD_DEFAULT_BUFFER_SIZE 0x2000
 636 #endif
 637
 638 #define UL_DRV_SYSLESS_PORT UART1_BASE
 639 #define UL_DRV_SYSLESS_BAUD 19200
 640 #define UL_DRV_SYSLESS_IRQ UART1_IRQn
 641 #define UL_DRV_SYSLESS_MY_ADR_DEFAULT 1
 642
 643 #define watchdog_feed lpc_watchdog_feed
 644 #define kvpb_erase lpcisp_kvpb_erase
 645 #define kvpb_copy lpcisp_kvpb_copy
 646 #define kvpb_flush lpcisp_kvpb_flush
 647 #define KVPB_DEFAULT_FLAGS KVPB_DESC_DOUBLE|KVPB_DESC_CHUNKWO
 648
 649 /***************************************************************************/
 650 /* USB configuration */
 651 #define USB_WITH_UDEV_FNC
 652 #define USB_EP_NUM          32
 653 #define USB_MAX_PACKET0     64
 654 #define USB_MAX_PACKET      8
 655 #define USB_DMA_EP          0x00000000
 656
 657 #define USB_VBUS_PIN_USED   0
 658
 659 /***************************************************************************/
 660 /* I2C1 configuration */
 661 #define I2C_DRV_SYSLESS_IRQ I2C1_IRQn
 662 #define I2C_DRV_SYSLESS_PORT I2C1_BASE
 663 #define I2C_DRV_SYSLESS_BITRATE 10000
 664 #define I2C_DRV_SYSLESS_SLADR 0
 665
 666 #endif /* _SYSTEM_DEF_H_ */