1 /**************************************************************************/
2 /* File: sja1000p.c - Philips/NXP SJA1000 chip PeliCanCAN mode support */
4 /* LinCAN - (Not only) Linux CAN bus driver */
5 /* Copyright (C) 2002-2009 DCE FEE CTU Prague <http://dce.felk.cvut.cz> */
6 /* Copyright (C) 2002-2009 Pavel Pisa <pisa@cmp.felk.cvut.cz> */
7 /* Copyright (C) 2004-2005 Tomasz Motylewski (BFAD GmbH) */
8 /* Funded by OCERA and FRESCOR IST projects */
9 /* Based on CAN driver code by Arnaud Westenberg <arnaud@wanadoo.nl> */
11 /* LinCAN is free software; you can redistribute it and/or modify it */
12 /* under terms of the GNU General Public License as published by the */
13 /* Free Software Foundation; either version 2, or (at your option) any */
14 /* later version. LinCAN is distributed in the hope that it will be */
15 /* useful, but WITHOUT ANY WARRANTY; without even the implied warranty */
16 /* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */
17 /* General Public License for more details. You should have received a */
18 /* copy of the GNU General Public License along with LinCAN; see file */
19 /* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, */
20 /* Cambridge, MA 02139, USA. */
22 /* To allow use of LinCAN in the compact embedded systems firmware */
23 /* and RT-executives (RTEMS for example), main authors agree with next */
24 /* special exception: */
26 /* Including LinCAN header files in a file, instantiating LinCAN generics */
27 /* or templates, or linking other files with LinCAN objects to produce */
28 /* an application image/executable, does not by itself cause the */
29 /* resulting application image/executable to be covered by */
30 /* the GNU General Public License. */
31 /* This exception does not however invalidate any other reasons */
32 /* why the executable file might be covered by the GNU Public License. */
33 /* Publication of enhanced or derived LinCAN files is required although. */
34 /**************************************************************************/
36 #include "../include/can.h"
37 #include "../include/can_sysdep.h"
38 #include "../include/main.h"
39 #include "../include/sja1000p.h"
41 #ifdef CONFIG_OC_LINCAN_DETAILED_ERRORS
43 static const char *sja1000_ecc_errc_str[]={
50 static const char *sja1000_ecc_seg_str[]={
70 "tolerate dominant bits",
78 "acknowledge delimiter",
85 #endif /*CONFIG_OC_LINCAN_DETAILED_ERRORS*/
87 static int sja1000_report_error_limit_counter;
89 static void sja1000_report_error(struct canchip_t *chip,
90 unsigned sr, unsigned ir, unsigned ecc)
92 if(sja1000_report_error_limit_counter>=100)
95 CANMSG("Error: status register: 0x%x irq_register: 0x%02x error: 0x%02x\n",
98 sja1000_report_error_limit_counter+=10;
100 if(sja1000_report_error_limit_counter>=100){
101 sja1000_report_error_limit_counter+=10;
102 CANMSG("Error: too many errors, reporting disabled\n");
106 #ifdef CONFIG_OC_LINCAN_DETAILED_ERRORS
107 CANMSG("SR: BS=%c ES=%c TS=%c RS=%c TCS=%c TBS=%c DOS=%c RBS=%c\n",
108 sr&sjaSR_BS?'1':'0',sr&sjaSR_ES?'1':'0',
109 sr&sjaSR_TS?'1':'0',sr&sjaSR_RS?'1':'0',
110 sr&sjaSR_TCS?'1':'0',sr&sjaSR_TBS?'1':'0',
111 sr&sjaSR_DOS?'1':'0',sr&sjaSR_RBS?'1':'0');
112 CANMSG("IR: BEI=%c ALI=%c EPI=%c WUI=%c DOI=%c EI=%c TI=%c RI=%c\n",
113 sr&sjaIR_BEI?'1':'0',sr&sjaIR_ALI?'1':'0',
114 sr&sjaIR_EPI?'1':'0',sr&sjaIR_WUI?'1':'0',
115 sr&sjaIR_DOI?'1':'0',sr&sjaIR_EI?'1':'0',
116 sr&sjaIR_TI?'1':'0',sr&sjaIR_RI?'1':'0');
117 if((sr&sjaIR_EI) || 1){
118 CANMSG("EI: %s %s %s\n",
119 sja1000_ecc_errc_str[(ecc&(sjaECC_ERCC1|sjaECC_ERCC0))/sjaECC_ERCC0],
120 ecc&sjaECC_DIR?"RX":"TX",
121 sja1000_ecc_seg_str[ecc&sjaECC_SEG_M]
124 #endif /*CONFIG_OC_LINCAN_DETAILED_ERRORS*/
129 * sja1000p_enable_configuration - enable chip configuration mode
130 * @chip: pointer to chip state structure
132 int sja1000p_enable_configuration(struct canchip_t *chip)
135 enum sja1000_PeliCAN_MOD flags;
137 can_disable_irq(chip->chip_irq);
139 flags=can_read_reg(chip,SJAMOD);
141 while ((!(flags & sjaMOD_RM)) && (i<=10)) {
142 can_write_reg(chip, sjaMOD_RM, SJAMOD);
143 // TODO: configurable sjaMOD_AFM (32/16 bit acceptance filter)
144 // config sjaMOD_LOM (listen only)
147 flags=can_read_reg(chip, SJAMOD);
150 CANMSG("Reset error\n");
151 can_enable_irq(chip->chip_irq);
159 * sja1000p_disable_configuration - disable chip configuration mode
160 * @chip: pointer to chip state structure
162 int sja1000p_disable_configuration(struct canchip_t *chip)
165 enum sja1000_PeliCAN_MOD flags;
167 flags=can_read_reg(chip,SJAMOD);
169 while ( (flags & sjaMOD_RM) && (i<=50) ) {
170 // could be as long as 11*128 bit times after buss-off
171 can_write_reg(chip, 0, SJAMOD);
172 // TODO: configurable sjaMOD_AFM (32/16 bit acceptance filter)
173 // config sjaMOD_LOM (listen only)
176 flags=can_read_reg(chip, SJAMOD);
179 CANMSG("Error leaving reset status\n");
183 can_enable_irq(chip->chip_irq);
189 * sja1000p_chip_config: - can chip configuration
190 * @chip: pointer to chip state structure
192 * This function configures chip and prepares it for message
193 * transmission and reception. The function resets chip,
194 * resets mask for acceptance of all messages by call to
195 * sja1000p_extended_mask() function and then
196 * computes and sets baudrate with use of function sja1000p_baud_rate().
197 * Return Value: negative value reports error.
198 * File: src/sja1000p.c
200 int sja1000p_chip_config(struct canchip_t *chip)
205 if (sja1000p_enable_configuration(chip))
208 /* Set mode, clock out, comparator */
209 can_write_reg(chip,sjaCDR_PELICAN|chip->sja_cdr_reg,SJACDR);
211 /* Ensure, that interrupts are disabled even on the chip level now */
212 can_write_reg(chip, sjaDISABLE_INTERRUPTS, SJAIER);
214 /* Set driver output configuration */
215 can_write_reg(chip,chip->sja_ocr_reg,SJAOCR);
217 /* Simple check for chip presence */
218 for (i=0, n=0x5a; i<8; i++, n+=0xf) {
219 can_write_reg(chip,n,SJAACR0+i);
221 for (i=0, n=0x5a; i<8; i++, n+=0xf) {
222 r = n^can_read_reg(chip,SJAACR0+i);
224 CANMSG("sja1000p_chip_config: chip connection broken,"
225 " readback differ 0x%02x\n", r);
231 if (sja1000p_extended_mask(chip,0x00000000, 0xffffffff))
235 chip->baudrate=1000000;
236 if (sja1000p_baud_rate(chip,chip->baudrate,chip->clock,0,75,0))
239 /* Enable hardware interrupts */
240 can_write_reg(chip, sjaENABLE_INTERRUPTS, SJAIER);
242 sja1000p_disable_configuration(chip);
248 * sja1000p_extended_mask: - setup of extended mask for message filtering
249 * @chip: pointer to chip state structure
250 * @code: can message acceptance code
251 * @mask: can message acceptance mask
253 * Return Value: negative value reports error.
254 * File: src/sja1000p.c
256 int sja1000p_extended_mask(struct canchip_t *chip, unsigned long code, unsigned long mask)
260 if (sja1000p_enable_configuration(chip))
263 // LSB to +3, MSB to +0
264 for(i=SJA_PeliCAN_AC_LEN; --i>=0;) {
265 can_write_reg(chip,code&0xff,SJAACR0+i);
266 can_write_reg(chip,mask&0xff,SJAAMR0+i);
271 DEBUGMSG("Setting acceptance code to 0x%lx\n",(unsigned long)code);
272 DEBUGMSG("Setting acceptance mask to 0x%lx\n",(unsigned long)mask);
274 sja1000p_disable_configuration(chip);
280 * sja1000p_baud_rate: - set communication parameters.
281 * @chip: pointer to chip state structure
282 * @rate: baud rate in Hz
283 * @clock: frequency of sja1000 clock in Hz (ISA osc is 14318000)
284 * @sjw: synchronization jump width (0-3) prescaled clock cycles
285 * @sampl_pt: sample point in % (0-100) sets (TSEG1+1)/(TSEG1+TSEG2+2) ratio
286 * @flags: fields %BTR1_SAM, %OCMODE, %OCPOL, %OCTP, %OCTN, %CLK_OFF, %CBP
288 * Return Value: negative value reports error.
289 * File: src/sja1000p.c
291 int sja1000p_baud_rate(struct canchip_t *chip, int rate, int clock, int sjw,
292 int sampl_pt, int flags)
294 int best_error = 1000000000, error;
295 int best_tseg=0, best_brp=0, best_rate=0, brp=0;
296 int tseg=0, tseg1=0, tseg2=0;
298 if (sja1000p_enable_configuration(chip))
303 /* tseg even = round down, odd = round up */
304 for (tseg=(0+0+2)*2; tseg<=(sjaMAX_TSEG2+sjaMAX_TSEG1+2)*2+1; tseg++) {
305 brp = clock/((1+tseg/2)*rate)+tseg%2;
306 if (brp == 0 || brp > 64)
308 error = rate - clock/(brp*(1+tseg/2));
311 if (error <= best_error) {
315 best_rate = clock/(brp*(1+tseg/2));
318 if (best_error && (rate/best_error < 10)) {
319 CANMSG("baud rate %d is not possible with %d Hz clock\n",
321 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
322 best_rate, best_brp, best_tseg, tseg1, tseg2);
325 tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
328 if (tseg2 > sjaMAX_TSEG2)
329 tseg2 = sjaMAX_TSEG2;
330 tseg1 = best_tseg-tseg2-2;
331 if (tseg1>sjaMAX_TSEG1) {
332 tseg1 = sjaMAX_TSEG1;
333 tseg2 = best_tseg-tseg1-2;
336 DEBUGMSG("Setting %d bps.\n", best_rate);
337 DEBUGMSG("brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
338 best_brp, best_tseg, tseg1, tseg2,
339 (100*(best_tseg-tseg2)/(best_tseg+1)));
342 can_write_reg(chip, sjw<<6 | best_brp, SJABTR0);
343 can_write_reg(chip, ((flags & BTR1_SAM) != 0)<<7 | (tseg2<<4)
346 sja1000p_disable_configuration(chip);
352 * sja1000p_read: - reads and distributes one or more received messages
353 * @chip: pointer to chip state structure
354 * @obj: pinter to CAN message queue information
356 * File: src/sja1000p.c
358 void sja1000p_read(struct canchip_t *chip, struct msgobj_t *obj) {
359 int i, flags, len, datastart;
361 flags = can_read_reg(chip,SJAFRM);
362 if(flags&sjaFRM_FF) {
364 (can_read_reg(chip,SJAID0)<<21) +
365 (can_read_reg(chip,SJAID1)<<13) +
366 (can_read_reg(chip,SJAID2)<<5) +
367 (can_read_reg(chip,SJAID3)>>3);
371 (can_read_reg(chip,SJAID0)<<3) +
372 (can_read_reg(chip,SJAID1)>>5);
376 ((flags & sjaFRM_RTR) ? MSG_RTR : 0) |
377 ((flags & sjaFRM_FF) ? MSG_EXT : 0);
378 len = flags & sjaFRM_DLC_M;
379 obj->rx_msg.length = len;
380 if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
381 for(i=0; i< len; i++) {
382 obj->rx_msg.data[i]=can_read_reg(chip,datastart+i);
385 /* fill CAN message timestamp */
386 can_filltimestamp(&obj->rx_msg.timestamp);
388 canque_filter_msg2edges(obj->qends, &obj->rx_msg);
390 can_write_reg(chip, sjaCMR_RRB, SJACMR);
392 } while (can_read_reg(chip, SJASR) & sjaSR_RBS);
396 * sja1000p_pre_read_config: - prepares message object for message reception
397 * @chip: pointer to chip state structure
398 * @obj: pointer to message object state structure
400 * Return Value: negative value reports error.
401 * Positive value indicates immediate reception of message.
402 * File: src/sja1000p.c
404 int sja1000p_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj)
407 status=can_read_reg(chip,SJASR);
409 if(status & sjaSR_BS) {
410 /* Try to recover from error condition */
411 DEBUGMSG("sja1000p_pre_read_config bus-off recover 0x%x\n",status);
412 sja1000p_enable_configuration(chip);
413 can_write_reg(chip, 0, SJARXERR);
414 can_write_reg(chip, 0, SJATXERR1);
415 can_read_reg(chip, SJAECC);
416 sja1000p_disable_configuration(chip);
419 if (!(status&sjaSR_RBS)) {
423 can_write_reg(chip, sjaDISABLE_INTERRUPTS, SJAIER); //disable interrupts for a moment
424 sja1000p_read(chip, obj);
425 can_write_reg(chip, sjaENABLE_INTERRUPTS, SJAIER); //enable interrupts
429 #define MAX_TRANSMIT_WAIT_LOOPS 10
431 * sja1000p_pre_write_config: - prepares message object for message transmission
432 * @chip: pointer to chip state structure
433 * @obj: pointer to message object state structure
434 * @msg: pointer to CAN message
436 * This function prepares selected message object for future initiation
437 * of message transmission by sja1000p_send_msg() function.
438 * The CAN message data and message ID are transfered from @msg slot
439 * into chip buffer in this function.
440 * Return Value: negative value reports error.
441 * File: src/sja1000p.c
443 int sja1000p_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
444 struct canmsg_t *msg)
451 /* Wait until Transmit Buffer Status is released */
452 while ( !((status=can_read_reg(chip, SJASR)) & sjaSR_TBS) &&
453 i++<MAX_TRANSMIT_WAIT_LOOPS) {
457 if(status & sjaSR_BS) {
458 /* Try to recover from error condition */
459 DEBUGMSG("sja1000p_pre_write_config bus-off recover 0x%x\n",status);
460 sja1000p_enable_configuration(chip);
461 can_write_reg(chip, 0, SJARXERR);
462 can_write_reg(chip, 0, SJATXERR1);
463 can_read_reg(chip, SJAECC);
464 sja1000p_disable_configuration(chip);
466 if (!(can_read_reg(chip, SJASR) & sjaSR_TBS)) {
467 CANMSG("Transmit timed out, cancelling\n");
468 // here we should check if there is no write/select waiting for this
469 // transmit. If so, set error ret and wake up.
470 // CHECKME: if we do not disable sjaIER_TIE (TX IRQ) here we get interrupt
472 can_write_reg(chip, sjaCMR_AT, SJACMR);
474 while ( !(can_read_reg(chip, SJASR) & sjaSR_TBS) &&
475 i++<MAX_TRANSMIT_WAIT_LOOPS) {
478 if (!(can_read_reg(chip, SJASR) & sjaSR_TBS)) {
479 CANMSG("Could not cancel, please reset\n");
484 if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
485 /* len &= sjaFRM_DLC_M; ensured by above condition already */
486 can_write_reg(chip, ((msg->flags&MSG_EXT)?sjaFRM_FF:0) |
487 ((msg->flags & MSG_RTR) ? sjaFRM_RTR : 0) | len, SJAFRM);
488 if(msg->flags&MSG_EXT) {
490 can_write_reg(chip, id & 0xff, SJAID3);
492 can_write_reg(chip, id & 0xff, SJAID2);
494 can_write_reg(chip, id & 0xff, SJAID1);
496 can_write_reg(chip, id, SJAID0);
497 for(i=0; i < len; i++) {
498 can_write_reg(chip, msg->data[i], SJADATE+i);
502 can_write_reg(chip, (id >> 8) & 0xff, SJAID0);
503 can_write_reg(chip, id & 0xff, SJAID1);
504 for(i=0; i < len; i++) {
505 can_write_reg(chip, msg->data[i], SJADATS+i);
512 * sja1000p_send_msg: - initiate message transmission
513 * @chip: pointer to chip state structure
514 * @obj: pointer to message object state structure
515 * @msg: pointer to CAN message
517 * This function is called after sja1000p_pre_write_config() function,
518 * which prepares data in chip buffer.
519 * Return Value: negative value reports error.
520 * File: src/sja1000p.c
522 int sja1000p_send_msg(struct canchip_t *chip, struct msgobj_t *obj,
523 struct canmsg_t *msg)
525 can_write_reg(chip, sjaCMR_TR, SJACMR);
531 * sja1000p_check_tx_stat: - checks state of transmission engine
532 * @chip: pointer to chip state structure
534 * Return Value: negative value reports error.
535 * Positive return value indicates transmission under way status.
536 * Zero value indicates finishing of all issued transmission requests.
537 * File: src/sja1000p.c
539 int sja1000p_check_tx_stat(struct canchip_t *chip)
541 if (can_read_reg(chip,SJASR) & sjaSR_TCS)
548 * sja1000p_set_btregs: - configures bitrate registers
549 * @chip: pointer to chip state structure
550 * @btr0: bitrate register 0
551 * @btr1: bitrate register 1
553 * Return Value: negative value reports error.
554 * File: src/sja1000p.c
556 int sja1000p_set_btregs(struct canchip_t *chip, unsigned short btr0,
559 if (sja1000p_enable_configuration(chip))
562 can_write_reg(chip, btr0, SJABTR0);
563 can_write_reg(chip, btr1, SJABTR1);
565 sja1000p_disable_configuration(chip);
571 * sja1000p_start_chip: - starts chip message processing
572 * @chip: pointer to chip state structure
574 * Return Value: negative value reports error.
575 * File: src/sja1000p.c
577 int sja1000p_start_chip(struct canchip_t *chip)
579 enum sja1000_PeliCAN_MOD flags;
581 flags = can_read_reg(chip, SJAMOD) & (sjaMOD_LOM|sjaMOD_STM|sjaMOD_AFM|sjaMOD_SM);
582 can_write_reg(chip, flags, SJAMOD);
584 sja1000_report_error_limit_counter=0;
590 * sja1000p_stop_chip: - stops chip message processing
591 * @chip: pointer to chip state structure
593 * Return Value: negative value reports error.
594 * File: src/sja1000p.c
596 int sja1000p_stop_chip(struct canchip_t *chip)
598 enum sja1000_PeliCAN_MOD flags;
600 flags = can_read_reg(chip, SJAMOD) & (sjaMOD_LOM|sjaMOD_STM|sjaMOD_AFM|sjaMOD_SM);
601 can_write_reg(chip, flags|sjaMOD_RM, SJAMOD);
607 * sja1000p_attach_to_chip: - attaches to the chip, setups registers and state
608 * @chip: pointer to chip state structure
610 * Return Value: negative value reports error.
611 * File: src/sja1000p.c
613 int sja1000p_attach_to_chip(struct canchip_t *chip)
619 * sja1000p_release_chip: - called before chip structure removal if %CHIP_ATTACHED is set
620 * @chip: pointer to chip state structure
622 * Return Value: negative value reports error.
623 * File: src/sja1000p.c
625 int sja1000p_release_chip(struct canchip_t *chip)
627 sja1000p_stop_chip(chip);
628 can_write_reg(chip, sjaDISABLE_INTERRUPTS, SJAIER);
634 * sja1000p_remote_request: - configures message object and asks for RTR message
635 * @chip: pointer to chip state structure
636 * @obj: pointer to message object structure
638 * Return Value: negative value reports error.
639 * File: src/sja1000p.c
641 int sja1000p_remote_request(struct canchip_t *chip, struct msgobj_t *obj)
643 CANMSG("sja1000p_remote_request not implemented\n");
648 * sja1000p_standard_mask: - setup of mask for message filtering
649 * @chip: pointer to chip state structure
650 * @code: can message acceptance code
651 * @mask: can message acceptance mask
653 * Return Value: negative value reports error.
654 * File: src/sja1000p.c
656 int sja1000p_standard_mask(struct canchip_t *chip, unsigned short code,
659 CANMSG("sja1000p_standard_mask not implemented\n");
664 * sja1000p_clear_objects: - clears state of all message object residing in chip
665 * @chip: pointer to chip state structure
667 * Return Value: negative value reports error.
668 * File: src/sja1000p.c
670 int sja1000p_clear_objects(struct canchip_t *chip)
672 CANMSG("sja1000p_clear_objects not implemented\n");
677 * sja1000p_config_irqs: - tunes chip hardware interrupt delivery
678 * @chip: pointer to chip state structure
679 * @irqs: requested chip IRQ configuration
681 * Return Value: negative value reports error.
682 * File: src/sja1000p.c
684 int sja1000p_config_irqs(struct canchip_t *chip, short irqs)
686 CANMSG("sja1000p_config_irqs not implemented\n");
691 * sja1000p_irq_write_handler: - part of ISR code responsible for transmit events
692 * @chip: pointer to chip state structure
693 * @obj: pointer to attached queue description
695 * The main purpose of this function is to read message from attached queues
696 * and transfer message contents into CAN controller chip.
697 * This subroutine is called by
698 * sja1000p_irq_write_handler() for transmit events.
699 * File: src/sja1000p.c
701 void sja1000p_irq_write_handler(struct canchip_t *chip, struct msgobj_t *obj)
706 /* Do local transmitted message distribution if enabled */
708 /* fill CAN message timestamp */
709 can_filltimestamp(&obj->tx_slot->msg.timestamp);
711 obj->tx_slot->msg.flags |= MSG_LOCAL;
712 canque_filter_msg2edges(obj->qends, &obj->tx_slot->msg);
714 /* Free transmitted slot */
715 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
719 can_msgobj_clear_fl(obj,TX_PENDING);
720 cmd=canque_test_outslot(obj->qends, &obj->tx_qedge, &obj->tx_slot);
723 can_msgobj_set_fl(obj,TX_PENDING);
725 if (chip->chipspecops->pre_write_config(chip, obj, &obj->tx_slot->msg)) {
727 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_PREP);
728 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
732 if (chip->chipspecops->send_msg(chip, obj, &obj->tx_slot->msg)) {
734 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_SEND);
735 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
745 * sja1000p_irq_handler: - interrupt service routine
746 * @irq: interrupt vector number, this value is system specific
747 * @chip: pointer to chip state structure
749 * Interrupt handler is activated when state of CAN controller chip changes,
750 * there is message to be read or there is more space for new messages or
751 * error occurs. The receive events results in reading of the message from
752 * CAN controller chip and distribution of message through attached
754 * File: src/sja1000p.c
756 int sja1000p_irq_handler(int irq, struct canchip_t *chip)
758 int irq_register, status, error_code;
759 struct msgobj_t *obj=chip->msgobj[0];
760 int loop_cnt=CHIP_MAX_IRQLOOP;
762 irq_register=can_read_reg(chip,SJAIR);
763 // DEBUGMSG("sja1000_irq_handler: SJAIR:%02x\n",irq_register);
764 // DEBUGMSG("sja1000_irq_handler: SJASR:%02x\n",
765 // can_read_reg(chip,SJASR));
767 if ((irq_register & (sjaIR_BEI|sjaIR_EPI|sjaIR_DOI|sjaIR_EI|sjaIR_TI|sjaIR_RI)) == 0)
768 return CANCHIP_IRQ_NONE;
770 if(!(chip->flags&CHIP_CONFIGURED)) {
771 CANMSG("sja1000p_irq_handler: called for non-configured device, irq_register 0x%02x\n", irq_register);
772 return CANCHIP_IRQ_NONE;
775 status=can_read_reg(chip,SJASR);
780 CANMSG("sja1000p_irq_handler IRQ %d stuck\n",irq);
781 return CANCHIP_IRQ_STUCK;
784 /* (irq_register & sjaIR_RI) */
785 /* old variant using SJAIR, collides with intended use with irq_accept */
786 if (status & sjaSR_RBS) {
787 DEBUGMSG("sja1000_irq_handler: RI or RBS\n");
788 sja1000p_read(chip,obj);
792 /* (irq_register & sjaIR_TI) */
793 /* old variant using SJAIR, collides with intended use with irq_accept */
794 if (((status & sjaSR_TBS) && can_msgobj_test_fl(obj,TX_PENDING))||
795 (can_msgobj_test_fl(obj,TX_REQUEST))) {
796 DEBUGMSG("sja1000_irq_handler: TI or TX_PENDING and TBS\n");
798 can_msgobj_set_fl(obj,TX_REQUEST);
799 while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
800 can_msgobj_clear_fl(obj,TX_REQUEST);
802 if (can_read_reg(chip, SJASR) & sjaSR_TBS)
803 sja1000p_irq_write_handler(chip, obj);
805 can_msgobj_clear_fl(obj,TX_LOCK);
806 if(!can_msgobj_test_fl(obj,TX_REQUEST)) break;
807 DEBUGMSG("TX looping in sja1000_irq_handler\n");
810 if ((irq_register & (sjaIR_EI|sjaIR_BEI|sjaIR_EPI|sjaIR_DOI)) != 0) {
811 // Some error happened
812 error_code=can_read_reg(chip,SJAECC);
813 sja1000_report_error(chip, status, irq_register, error_code);
814 // FIXME: chip should be brought to usable state. Transmission cancelled if in progress.
815 // Reset flag set to 0 if chip is already off the bus. Full state report
818 if(error_code == 0xd9) {
820 /* no such device or address - no ACK received */
822 if(obj->tx_retry_cnt++>MAX_RETR) {
823 can_write_reg(chip, sjaCMR_AT, SJACMR); // cancel any transmition
824 obj->tx_retry_cnt = 0;
826 if(status&sjaSR_BS) {
827 CANMSG("bus-off, resetting sja1000p\n");
828 can_write_reg(chip, 0, SJAMOD);
832 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_BUS);
833 /*canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
838 if(sja1000_report_error_limit_counter)
839 sja1000_report_error_limit_counter--;
843 irq_register=can_read_reg(chip,SJAIR);
845 status=can_read_reg(chip,SJASR);
847 if(((status & sjaSR_TBS) && can_msgobj_test_fl(obj,TX_PENDING)) ||
848 (irq_register & sjaIR_TI))
849 can_msgobj_set_fl(obj,TX_REQUEST);
851 } while((irq_register & (sjaIR_BEI|sjaIR_EPI|sjaIR_DOI|sjaIR_EI|sjaIR_RI)) ||
852 (can_msgobj_test_fl(obj,TX_REQUEST) && !can_msgobj_test_fl(obj,TX_LOCK)) ||
853 (status & sjaSR_RBS));
855 return CANCHIP_IRQ_HANDLED;
859 * sja1000p_wakeup_tx: - wakeups TX processing
860 * @chip: pointer to chip state structure
861 * @obj: pointer to message object structure
863 * Function is responsible for initiating message transmition.
864 * It is responsible for clearing of object TX_REQUEST flag
866 * Return Value: negative value reports error.
867 * File: src/sja1000p.c
869 int sja1000p_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj)
872 can_preempt_disable();
874 can_msgobj_set_fl(obj,TX_PENDING);
875 can_msgobj_set_fl(obj,TX_REQUEST);
876 while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
877 can_msgobj_clear_fl(obj,TX_REQUEST);
879 if (can_read_reg(chip, SJASR) & sjaSR_TBS){
881 sja1000p_irq_write_handler(chip, obj);
884 can_msgobj_clear_fl(obj,TX_LOCK);
885 if(!can_msgobj_test_fl(obj,TX_REQUEST)) break;
886 DEBUGMSG("TX looping in sja1000p_wakeup_tx\n");
889 can_preempt_enable();
893 int sja1000p_register(struct chipspecops_t *chipspecops)
895 CANMSG("initializing sja1000p chip operations\n");
896 chipspecops->chip_config=sja1000p_chip_config;
897 chipspecops->baud_rate=sja1000p_baud_rate;
898 chipspecops->standard_mask=sja1000p_standard_mask;
899 chipspecops->extended_mask=sja1000p_extended_mask;
900 chipspecops->message15_mask=sja1000p_extended_mask;
901 chipspecops->clear_objects=sja1000p_clear_objects;
902 chipspecops->config_irqs=sja1000p_config_irqs;
903 chipspecops->pre_read_config=sja1000p_pre_read_config;
904 chipspecops->pre_write_config=sja1000p_pre_write_config;
905 chipspecops->send_msg=sja1000p_send_msg;
906 chipspecops->check_tx_stat=sja1000p_check_tx_stat;
907 chipspecops->wakeup_tx=sja1000p_wakeup_tx;
908 chipspecops->remote_request=sja1000p_remote_request;
909 chipspecops->enable_configuration=sja1000p_enable_configuration;
910 chipspecops->disable_configuration=sja1000p_disable_configuration;
911 chipspecops->attach_to_chip=sja1000p_attach_to_chip;
912 chipspecops->release_chip=sja1000p_release_chip;
913 chipspecops->set_btregs=sja1000p_set_btregs;
914 chipspecops->start_chip=sja1000p_start_chip;
915 chipspecops->stop_chip=sja1000p_stop_chip;
916 chipspecops->irq_handler=sja1000p_irq_handler;
917 chipspecops->irq_accept=NULL;
922 * sja1000p_fill_chipspecops - fills chip specific operations
923 * @chip: pointer to chip representation structure
925 * The function fills chip specific operations for sja1000 (PeliCAN) chip.
927 * Return Value: returns negative number in the case of fail
929 int sja1000p_fill_chipspecops(struct canchip_t *chip)
931 chip->chip_type="sja1000p";
933 sja1000p_register(chip->chipspecops);