1 /**************************************************************************/
2 /* File: sja1000p.h - Philips/NXP SJA1000 chip PeliCanCAN mode support */
4 /* LinCAN - (Not only) Linux CAN bus driver */
5 /* Copyright (C) 2002-2009 DCE FEE CTU Prague <http://dce.felk.cvut.cz> */
6 /* Copyright (C) 2002-2009 Pavel Pisa <pisa@cmp.felk.cvut.cz> */
7 /* Copyright (C) 2004-2005 Tomasz Motylewski (BFAD GmbH) */
8 /* Funded by OCERA and FRESCOR IST projects */
9 /* Based on CAN driver code by Arnaud Westenberg <arnaud@wanadoo.nl> */
11 /* LinCAN is free software; you can redistribute it and/or modify it */
12 /* under terms of the GNU General Public License as published by the */
13 /* Free Software Foundation; either version 2, or (at your option) any */
14 /* later version. LinCAN is distributed in the hope that it will be */
15 /* useful, but WITHOUT ANY WARRANTY; without even the implied warranty */
16 /* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */
17 /* General Public License for more details. You should have received a */
18 /* copy of the GNU General Public License along with LinCAN; see file */
19 /* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, */
20 /* Cambridge, MA 02139, USA. */
22 /* To allow use of LinCAN in the compact embedded systems firmware */
23 /* and RT-executives (RTEMS for example), main authors agree with next */
24 /* special exception: */
26 /* Including LinCAN header files in a file, instantiating LinCAN generics */
27 /* or templates, or linking other files with LinCAN objects to produce */
28 /* an application image/executable, does not by itself cause the */
29 /* resulting application image/executable to be covered by */
30 /* the GNU General Public License. */
31 /* This exception does not however invalidate any other reasons */
32 /* why the executable file might be covered by the GNU Public License. */
33 /* Publication of enhanced or derived LinCAN files is required although. */
34 /**************************************************************************/
36 int sja1000p_chip_config(struct canchip_t *chip);
37 int sja1000p_extended_mask(struct canchip_t *chip, unsigned long code, unsigned long mask);
38 int sja1000p_baud_rate(struct canchip_t *chip, int rate, int clock, int sjw,
39 int sampl_pt, int flags);
40 int sja1000p_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj);
41 int sja1000p_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
42 struct canmsg_t *msg);
43 int sja1000p_send_msg(struct canchip_t *chip, struct msgobj_t *obj,
44 struct canmsg_t *msg);
45 int sja1000p_fill_chipspecops(struct canchip_t *chip);
46 int sja1000p_irq_handler(int irq, struct canchip_t *chip);
50 enum SJA1000_PeliCAN_regs {
56 /// Interrupt register
60 /// Bus Timing register 0
62 /// Bus Timing register 1
64 /// Output Control register
66 /// Arbitration Lost Capture
68 /// Error Code Capture
70 /// Error Warning Limit
77 /// Rx Message Counter (number of msgs. in RX FIFO
79 /// Rx Buffer Start Addr. (address of current MSG)
81 /// Transmit Buffer (write) Receive Buffer (read) Frame Information
83 /// ID bytes (11 bits in 0 and 1 or 16 bits in 0,1 and 13 bits in 2,3 (extended))
84 SJAID0 = 0x11, SJAID1 = 0x12,
85 /// ID cont. for extended frames
86 SJAID2 = 0x13, SJAID3 = 0x14,
87 /// Data start standard frame
89 /// Data start extended frame
91 /// Acceptance Code (4 bytes) in RESET mode
93 /// Acceptance Mask (4 bytes) in RESET mode
96 SJA_PeliCAN_AC_LEN = 4,
101 /** Mode Register 0x00 */
102 enum sja1000_PeliCAN_MOD {
103 sjaMOD_SM = 1<<4, // Sleep Mode (writable only in OPERATING mode)
104 sjaMOD_AFM= 1<<3, // Acceptance Filter Mode (writable only in RESET)
105 sjaMOD_STM= 1<<2, // Self Test Mode (writable only in RESET)
106 sjaMOD_LOM= 1<<1, // Listen Only Mode (writable only in RESET)
107 sjaMOD_RM = 1 // Reset Mode
110 /** Command Register 0x01 */
111 enum sja1000_PeliCAN_CMR {
112 sjaCMR_SRR= 1<<4, // Self Reception Request (GoToSleep in BASIC mode)
113 sjaCMR_CDO= 1<<3, // Clear Data Overrun
114 sjaCMR_RRB= 1<<2, // Release Receive Buffer
115 sjaCMR_AT = 1<<1, // Abort Transmission
116 sjaCMR_TR = 1 }; // Transmission Request
118 /** Status Register 0x02 */
120 sjaSR_BS = 1<<7, // Bus Status
121 sjaSR_ES = 1<<6, // Error Status
122 sjaSR_TS = 1<<5, // Transmit Status
123 sjaSR_RS = 1<<4, // Receive Status
124 sjaSR_TCS = 1<<3, // Transmission Complete Status
125 sjaSR_TBS = 1<<2, // Transmit Buffer Status
126 sjaSR_DOS = 1<<1, // Data Overrun Status
127 sjaSR_RBS = 1 }; // Receive Buffer Status
129 /** Interrupt Enable Register 0x04 */
130 enum sja1000_PeliCAN_IER {
131 sjaIER_BEIE= 1<<7, // Bus Error Interrupt Enable
132 sjaIER_ALIE= 1<<6, // Arbitration Lost Interrupt Enable
133 sjaIER_EPIE= 1<<5, // Error Passive Interrupt Enable
134 sjaIER_WUIE= 1<<4, // Wake-Up Interrupt Enable
135 sjaIER_DOIE= 1<<3, // Data Overrun Interrupt Enable
136 sjaIER_EIE = 1<<2, // Error Warning Interrupt Enable
137 sjaIER_TIE = 1<<1, // Transmit Interrupt Enable
138 sjaIER_RIE = 1, // Receive Interrupt Enable
139 sjaENABLE_INTERRUPTS = sjaIER_BEIE|sjaIER_EPIE|sjaIER_DOIE|sjaIER_EIE|sjaIER_TIE|sjaIER_RIE,
140 sjaDISABLE_INTERRUPTS = 0
141 // WARNING: the chip automatically enters RESET (bus off) mode when
142 // error counter > 255
145 /** Arbitration Lost Capture Register 0x0b.
146 * Counting starts from 0 (bit1 of ID). Bits 5-7 reserved*/
147 enum sja1000_PeliCAN_ALC {
148 sjaALC_SRTR = 0x0b,// Arbitration lost in bit SRTR
149 sjaALC_IDE = 0x1c, // Arbitration lost in bit IDE
150 sjaALC_RTR = 0x1f, // Arbitration lost in RTR
153 /** Error Code Capture Register 0x0c*/
154 enum sja1000_PeliCAN_ECC {
158 sjaECC_FORM = sjaECC_ERCC0,
159 sjaECC_STUFF = sjaECC_ERCC1,
160 sjaECC_OTHER = sjaECC_ERCC0 | sjaECC_ERCC1,
161 sjaECC_DIR = 1<<5, // 1 == RX, 0 == TX
162 sjaECC_SEG_M = (1<<5) -1 // Segment mask, see page 37 of SJA1000 Data Sheet
165 /** Frame format information 0x10 */
166 enum sja1000_PeliCAN_FRM {
167 sjaFRM_FF = 1<<7, // Frame Format 1 == extended, 0 == standard
168 sjaFRM_RTR = 1<<6, // Remote request
169 sjaFRM_DLC_M = (1<<4)-1 // Length Mask
173 /** Interrupt (status) Register 0x03 */
174 enum sja1000_PeliCAN_IR {
175 sjaIR_BEI = 1<<7, // Bus Error Interrupt
176 sjaIR_ALI = 1<<6, // Arbitration Lost Interrupt
177 sjaIR_EPI = 1<<5, // Error Passive Interrupt (entered error passive state or error active state)
178 sjaIR_WUI = 1<<4, // Wake-Up Interrupt
179 sjaIR_DOI = 1<<3, // Data Overrun Interrupt
180 sjaIR_EI = 1<<2, // Error Interrupt
181 sjaIR_TI = 1<<1, // Transmit Interrupt
182 sjaIR_RI = 1 // Receive Interrupt
185 /** Bus Timing 1 Register 0x07 */
191 /** Output Control Register 0x08 */
193 sjaOCR_MODE_BIPHASE = 0,
194 sjaOCR_MODE_TEST = 1,
195 sjaOCR_MODE_NORMAL = 2,
196 sjaOCR_MODE_CLOCK = 3,
197 /// TX0 push-pull not inverted
198 sjaOCR_TX0_LH = 0x18,
199 /// TX1 floating (off)
203 /** Clock Divider register 0x1f */
205 sjaCDR_PELICAN = 1<<7,
206 /// bypass input comparator
208 /// switch TX1 to generate RX INT
209 sjaCDR_RXINPEN = 1<<5,
210 sjaCDR_CLK_OFF = 1<<3,
211 /// f_out = f_osc/(2*(CDR[2:0]+1)) or f_osc if CDR[2:0]==7
212 sjaCDR_CLKOUT_DIV1 = 7,
213 sjaCDR_CLKOUT_DIV2 = 0,
214 sjaCDR_CLKOUT_DIV4 = 1,
215 sjaCDR_CLKOUT_DIV6 = 2,
216 sjaCDR_CLKOUT_DIV8 = 3,
217 sjaCDR_CLKOUT_DIV10 = 4,
218 sjaCDR_CLKOUT_DIV12 = 5,
219 sjaCDR_CLKOUT_DIV14 = 6,
220 sjaCDR_CLKOUT_MASK = 7
223 /** flags for sja1000_baud_rate */
224 #define BTR1_SAM (1<<1)