2 * Linux CAN-bus device driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
5 * email:pisa@cmp.felk.cvut.cz
6 * This software is released under the GPL-License.
7 * Version lincan-0.3 17 Jun 2004
10 #include "../include/can.h"
11 #include "../include/can_sysdep.h"
12 #include "../include/main.h"
13 #include "../include/sja1000p.h"
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/imx-regs.h>
17 #define EIM_CS1U __REG(IMX_EIM_BASE + 0x08)
18 #define EIM_CS1L __REG(IMX_EIM_BASE + 0x0C)
21 * IO_RANGE is the io-memory range that gets reserved, please adjust according
22 * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
23 * #define IO_RANGE 0x20 for sja1000 chips in basic CAN mode.
25 #define PIMX1_CAN_IO_ADDRESS 0x12000000
26 #define PIMX1_CAN_IO_RANGE 0x100
27 #define PIMX1_CAN_IRQ IRQ_GPIOB(17)
28 #define PIMX1_CAN_RESET_ADDR 0x0
32 static can_spinlock_t pimx1_setup_hardware_lock=SPIN_LOCK_UNLOCKED;
34 int pimx1_setup_hardware(struct candevice_t *candev)
36 can_spin_irqflags_t flags;
38 can_spin_lock_irqsave(&pimx1_setup_hardware_lock,flags);
39 /* CNC=0; WSC=10-1; WWS=0; EDC=2; OEA=6; OEN=2; WEA=8; WEN=2 */
40 EIM_CS1U = 0x00000902;
41 EIM_CS1L = 0x82820903;
42 imx_gpio_mode(PA21_PF_A0);
43 /* Setup IRQ port as input */
44 imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | GPIO_GPIO | 17);
45 /* Setup SJA1000 reset as ourput */
46 imx_gpio_mode(GPIO_PORTB | GPIO_OUT | GPIO_GPIO | 15);
48 can_spin_unlock_irqrestore(&pimx1_setup_hardware_lock,flags);
50 set_irq_type(PIMX1_CAN_IRQ, IRQT_LOW);
57 * pimx1_request_io: - reserve io or memory range for can board
58 * @candev: pointer to candevice/board which asks for io. Field @io_addr
59 * of @candev is used in most cases to define start of the range
61 * The function pimx1_request_io() is used to reserve the io-memory. If your
62 * hardware uses a dedicated memory range as hardware control registers you
63 * will have to add the code to reserve this memory as well.
64 * %IO_RANGE is the io-memory range that gets reserved, please adjust according
65 * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
66 * #define IO_RANGE 0x20 for sja1000 chips in basic CAN mode.
67 * Return Value: The function returns zero on success or %-ENODEV on failure
68 * File: src/pikronisa.c
70 int pimx1_request_io(struct candevice_t *candev)
74 if(pimx1_setup_hardware(candev)<0){
75 CANMSG("PiMX1 board hardware setup failure\n");
79 if (!can_request_mem_region(candev->io_addr,PIMX1_CAN_IO_RANGE,DEVICE_NAME " - pimx1")) {
80 CANMSG("Unable to request IO-memory: 0x%lx\n",candev->io_addr);
83 if ( !( remap_addr = (long) ioremap( candev->io_addr, PIMX1_CAN_IO_RANGE ) ) ) {
84 CANMSG("Unable to access I/O memory at: 0x%lx\n", candev->io_addr);
85 can_release_mem_region(candev->io_addr,PIMX1_CAN_IO_RANGE);
88 can_base_addr_fixup(candev, remap_addr);
89 CANMSG("Registered IO-memory: 0x%lx - 0x%lx\n", candev->io_addr, candev->io_addr + PIMX1_CAN_IO_RANGE - 1);
94 * pimx1_elease_io - free reserved io memory range
95 * @candev: pointer to candevice/board which releases io
97 * The function pimx1_release_io() is used to free reserved io-memory.
98 * In case you have reserved more io memory, don't forget to free it here.
99 * IO_RANGE is the io-memory range that gets released, please adjust according
100 * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
101 * #define IO_RANGE 0x20 for sja1000 chips in basic CAN mode.
102 * Return Value: The function always returns zero
103 * File: src/pikronisa.c
105 int pimx1_release_io(struct candevice_t *candev)
107 /* release I/O memory mapping */
108 iounmap((void*)candev->dev_base_addr);
109 can_release_mem_region(candev->io_addr,PIMX1_CAN_IO_RANGE);
115 * pimx1_write_register - Low level write register routine
116 * @data: data to be written
117 * @address: memory address to write to
119 * The function pimx1_write_register() is used to write to hardware registers
120 * on the CAN chip. You should only have to edit this function if your hardware
121 * uses some specific write process.
122 * Return Value: The function does not return a value
123 * File: src/pikronisa.c
125 void pimx1_write_register(unsigned data, unsigned long address)
127 /*DEBUGMSG("pimx1_write_register: addr=0x%lx data=0x%x",
129 writeb(data,address);
133 * pimx1_read_register - Low level read register routine
134 * @address: memory address to read from
136 * The function pimx1_read_register() is used to read from hardware registers
137 * on the CAN chip. You should only have to edit this function if your hardware
138 * uses some specific read process.
139 * Return Value: The function returns the value stored in @address
140 * File: src/pikronisa.c
142 unsigned pimx1_read_register(unsigned long address)
144 return readb(address);
148 * pimx1_reset - hardware reset routine
149 * @candev: Pointer to candevice/board structure
151 * The function pimx1_reset() is used to give a hardware reset. This is
152 * rather hardware specific so I haven't included example code. Don't forget to
153 * check the reset status of the chip before returning.
154 * Return Value: The function returns zero on success or %-ENODEV on failure
155 * File: src/pikronisa.c
157 int pimx1_reset(struct candevice_t *candev)
160 struct canchip_t *chip=candev->chip[0];
163 pimx1_write_register(sjaMOD_RM, chip->chip_base_addr+SJAMOD);
166 cdr=pimx1_read_register(chip->chip_base_addr+SJACDR);
167 pimx1_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
169 pimx1_write_register(0, chip->chip_base_addr+SJAIER);
172 pimx1_write_register(0, chip->chip_base_addr+SJAMOD);
173 while (pimx1_read_register(chip->chip_base_addr+SJAMOD)&sjaMOD_RM){
174 if(!i--) return -ENODEV;
176 pimx1_write_register(0, chip->chip_base_addr+SJAMOD);
179 cdr=pimx1_read_register(chip->chip_base_addr+SJACDR);
180 pimx1_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
182 pimx1_write_register(0, chip->chip_base_addr+SJAIER);
188 * pimx1_init_hw_data - Initialize hardware cards
189 * @candev: Pointer to candevice/board structure
191 * The function pimx1_init_hw_data() is used to initialize the hardware
192 * structure containing information about the installed CAN-board.
193 * %RESET_ADDR represents the io-address of the hardware reset register.
194 * %NR_82527 represents the number of intel 82527 chips on the board.
195 * %NR_SJA1000 represents the number of philips sja1000 chips on the board.
196 * The flags entry can currently only be %CANDEV_PROGRAMMABLE_IRQ to indicate that
197 * the hardware uses programmable interrupts.
198 * Return Value: The function always returns zero
199 * File: src/pikronisa.c
201 int pimx1_init_hw_data(struct candevice_t *candev)
203 candev->res_addr=PIMX1_CAN_RESET_ADDR;
204 candev->io_addr=PIMX1_CAN_IO_ADDRESS;
205 candev->dev_base_addr=PIMX1_CAN_IO_ADDRESS;
206 candev->nr_82527_chips=0;
207 candev->nr_sja1000_chips=1;
208 candev->nr_all_chips=1;
209 candev->flags |= CANDEV_PROGRAMMABLE_IRQ*0;
215 * pimx1_init_chip_data - Initialize chips
216 * @candev: Pointer to candevice/board structure
217 * @chipnr: Number of the CAN chip on the hardware card
219 * The function pimx1_init_chip_data() is used to initialize the hardware
220 * structure containing information about the CAN chips.
221 * %CHIP_TYPE represents the type of CAN chip. %CHIP_TYPE can be "i82527" or
223 * The @chip_base_addr entry represents the start of the 'official' memory map
224 * of the installed chip. It's likely that this is the same as the @io_addr
225 * argument supplied at module loading time.
226 * The @clock entry holds the chip clock value in Hz.
227 * The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
228 * register. Options defined in the %sja1000.h file:
229 * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
230 * The entry @sja_ocr_reg holds hardware specific options for the Output Control
231 * register. Options defined in the %sja1000.h file:
232 * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
233 * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
234 * The entry @int_clk_reg holds hardware specific options for the Clock Out
235 * register. Options defined in the %i82527.h file:
236 * %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
237 * The entry @int_bus_reg holds hardware specific options for the Bus
238 * Configuration register. Options defined in the %i82527.h file:
239 * %iBUS_DR0, %iBUS_DR1, %iBUS_DT1, %iBUS_POL, %iBUS_CBY.
240 * The entry @int_cpu_reg holds hardware specific options for the cpu interface
241 * register. Options defined in the %i82527.h file:
242 * %iCPU_CEN, %iCPU_MUX, %iCPU_SLP, %iCPU_PWD, %iCPU_DMC, %iCPU_DSC, %iCPU_RST.
243 * Return Value: The function always returns zero
244 * File: src/pikronisa.c
246 int pimx1_init_chip_data(struct candevice_t *candev, int chipnr)
248 /*sja1000_fill_chipspecops(candev->chip[chipnr]);*/
249 sja1000p_fill_chipspecops(candev->chip[chipnr]);
251 candev->chip[chipnr]->chip_base_addr=candev->io_addr;
252 candev->chip[chipnr]->chip_irq=PIMX1_CAN_IRQ;
253 candev->chip[chipnr]->clock = 24000000;
254 candev->chip[chipnr]->int_clk_reg = 0x0;
255 candev->chip[chipnr]->int_bus_reg = 0x0;
256 candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | sjaCDR_CLK_OFF;
257 candev->chip[chipnr]->sja_ocr_reg = sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH;
263 * pimx1_init_obj_data - Initialize message buffers
264 * @chip: Pointer to chip specific structure
265 * @objnr: Number of the message buffer
267 * The function pimx1_init_obj_data() is used to initialize the hardware
268 * structure containing information about the different message objects on the
269 * CAN chip. In case of the sja1000 there's only one message object but on the
270 * i82527 chip there are 15.
271 * The code below is for a i82527 chip and initializes the object base addresses
272 * The entry @obj_base_addr represents the first memory address of the message
273 * object. In case of the sja1000 @obj_base_addr is taken the same as the chips
275 * Unless the hardware uses a segmented memory map, flags can be set zero.
276 * Return Value: The function always returns zero
277 * File: src/pikronisa.c
279 int pimx1_init_obj_data(struct canchip_t *chip, int objnr)
281 chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr;
286 * pimx1_program_irq - program interrupts
287 * @candev: Pointer to candevice/board structure
289 * The function pimx1_program_irq() is used for hardware that uses
290 * programmable interrupts. If your hardware doesn't use programmable interrupts
291 * you should not set the @candevices_t->flags entry to %CANDEV_PROGRAMMABLE_IRQ and
292 * leave this function unedited. Again this function is hardware specific so
293 * there's no example code.
294 * Return value: The function returns zero on success or %-ENODEV on failure
295 * File: src/pikronisa.c
297 int pimx1_program_irq(struct candevice_t *candev)
302 /* !!! Don't change this function !!! */
303 int pimx1_register(struct hwspecops_t *hwspecops)
305 hwspecops->request_io = pimx1_request_io;
306 hwspecops->release_io = pimx1_release_io;
307 hwspecops->reset = pimx1_reset;
308 hwspecops->init_hw_data = pimx1_init_hw_data;
309 hwspecops->init_chip_data = pimx1_init_chip_data;
310 hwspecops->init_obj_data = pimx1_init_obj_data;
311 hwspecops->write_register = pimx1_write_register;
312 hwspecops->read_register = pimx1_read_register;
313 hwspecops->program_irq = pimx1_program_irq;