2 * Header file for the Linux CAN-bus driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
5 * email:pisa@cmp.felk.cvut.cz
6 * This software is released under the GPL-License.
7 * Version lincan-0.2 9 Jul 2003
11 #include "./constants.h"
12 #include "./can_sysdep.h"
13 #include "./can_queue.h"
16 #define DEBUGMSG(fmt,args...) can_printk(KERN_ERR "can.o (debug): " fmt,\
19 #define DEBUGMSG(fmt,args...)
22 #define CANMSG(fmt,args...) can_printk(KERN_ERR "can.o: " fmt,##args)
25 extern can_spinlock_t canuser_manipulation_lock;
28 * struct canhardware_t - structure representing pointers to all CAN boards
29 * @nr_boards: number of present boards
30 * @rtr_queue: RTR - remote transmission request queue (expect some changes there)
31 * @rtr_lock: locking for RTR queue
32 * @candevice: array of pointers to CAN devices/boards
34 struct canhardware_t {
36 struct rtr_id *rtr_queue;
37 can_spinlock_t rtr_lock;
38 struct candevice_t *candevice[MAX_HW_CARDS];
42 * struct candevice_t - CAN device/board structure
43 * @hwname: text string with board type
44 * @candev_idx: board index in canhardware_t.candevice[]
45 * @io_addr: IO/physical MEM address
46 * @res_addr: optional reset register port
47 * @dev_base_addr: CPU translated IO/virtual MEM address
48 * @flags: board flags: %PROGRAMMABLE_IRQ .. interrupt number
49 * can be programmed into board
50 * @nr_all_chips: number of chips present on the board
51 * @nr_82527_chips: number of Intel 8257 chips
52 * @nr_sja1000_chips: number of Philips SJA100 chips
53 * @chip: array of pointers to the chip structures
54 * @hwspecops: pointer to board specific operations
55 * @hosthardware_p: pointer to the root hardware structure
56 * @sysdevptr: union reserved for pointer to bus specific
57 * device structure (case @pcidev is used for PCI devices)
59 * The structure represent configuration and state of associated board.
60 * The driver infrastructure prepares this structure and calls
61 * board type specific board_register() function. The board support provided
62 * register function fills right function pointers in @hwspecops structure.
63 * Then driver setup calls functions init_hw_data(), init_chip_data(),
64 * init_chip_data(), init_obj_data() and program_irq(). Function init_hw_data()
65 * and init_chip_data() have to specify number and types of connected chips
66 * or objects respectively.
67 * The use of @nr_all_chips is preferred over use of fields @nr_82527_chips
68 * and @nr_sja1000_chips in the board non-specific functions.
69 * The @io_addr and @dev_base_addr is filled from module parameters
70 * to the same value. The request_io function can fix-up @dev_base_addr
71 * field if virtual address is different than bus address.
74 char *hwname; /* text board type */
75 int candev_idx; /* board index in canhardware_t.candevice[] */
76 unsigned long io_addr; /* IO/physical MEM address */
77 unsigned long res_addr; /* optional seset register port */
78 unsigned long dev_base_addr; /* CPU translated IO/virtual MEM address */
83 struct chip_t *chip[MAX_HW_CHIPS];
85 struct hwspecops_t *hwspecops;
87 struct canhardware_t *hosthardware_p;
91 #ifdef CAN_ENABLE_PCI_SUPPORT
92 struct pci_dev *pcidev;
93 #endif /*CAN_ENABLE_PCI_SUPPORT*/
99 * struct chip_t - CAN chip state and type information
100 * @chip_type: text string describing chip type
101 * @chip_idx: index of the chip in candevice_t.chip[] array
102 * @chip_irq: chip interrupt number if any
103 * @chip_base_addr: chip base address in the CPU IO or virtual memory space
104 * @flags: chip flags: %CHIP_CONFIGURED .. chip is configured,
105 * %CHIP_SEGMENTED .. access to the chip is segmented (mainly for i82527 chips)
106 * @clock: chip base clock frequency in Hz
107 * @baudrate: selected chip baudrate in Hz
108 * @write_register: write chip register function copy
109 * @read_register: read chip register function copy
110 * @chip_data: pointer for optional chip specific data extension
111 * @sja_cdr_reg: SJA specific register -
112 * holds hardware specific options for the Clock Divider
113 * register. Options defined in the sja1000.h file:
114 * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
115 * @sja_ocr_reg: SJA specific register -
116 * hold hardware specific options for the Output Control
117 * register. Options defined in the sja1000.h file:
118 * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
119 * %OCR_TX0_LH, %OCR_TX1_ZZ.
120 * @int_cpu_reg: Intel specific register -
121 * holds hardware specific options for the CPU Interface
122 * register. Options defined in the i82527.h file:
123 * %iCPU_CEN, %iCPU_MUX, %iCPU_SLP, %iCPU_PWD, %iCPU_DMC, %iCPU_DSC, %iCPU_RST.
124 * @int_clk_reg: Intel specific register -
125 * holds hardware specific options for the Clock Out
126 * register. Options defined in the i82527.h file:
127 * %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
128 * @int_bus_reg: Intel specific register -
129 * holds hardware specific options for the Bus Configuration
130 * register. Options defined in the i82527.h file:
131 * %iBUS_DR0, %iBUS_DR1, %iBUS_DT1, %iBUS_POL, %iBUS_CBY.
132 * @msgobj: array of pointers to individual communication objects
133 * @chipspecops: pointer to the set of chip specific object filled by init_chip_data() function
134 * @hostdevice: pointer to chip hosting board
135 * @max_objects: maximal number of communication objects connected to this chip
136 * @chip_lock: reserved for synchronization of the chip supporting routines
137 * (not used in the current driver version)
138 * @worker_thread: chip worker thread ID (RT-Linux specific field)
139 * @pend_flags: holds information about pending interrupt and tx_wake() operations
140 * (RT-Linux specific field). Masks values:
141 * %MSGOBJ_TX_REQUEST .. some of the message objects requires tx_wake() call,
142 * %MSGOBJ_IRQ_REQUEST .. chip interrupt processing required
143 * %MSGOBJ_WORKER_WAKE .. marks, that worker thread should be waked
144 * for some of above reasons
146 * The fields @write_register and @read_register are copied from
147 * corresponding fields from @hwspecops structure
148 * (chip->hostdevice->hwspecops->write_register and
149 * chip->hostdevice->hwspecops->read_register)
150 * to speedup can_write_reg() and can_read_reg() functions.
154 int chip_idx; /* chip index in candevice_t.chip[] */
156 unsigned long chip_base_addr;
158 long clock; /* Chip clock in Hz */
161 void (*write_register)(unsigned data,unsigned long address);
162 unsigned (*read_register)(unsigned long address);
166 unsigned short sja_cdr_reg; /* sja1000 only! */
167 unsigned short sja_ocr_reg; /* sja1000 only! */
168 unsigned short int_cpu_reg; /* intel 82527 only! */
169 unsigned short int_clk_reg; /* intel 82527 only! */
170 unsigned short int_bus_reg; /* intel 82527 only! */
172 struct msgobj_t *msgobj[MAX_MSGOBJS];
174 struct chipspecops_t *chipspecops;
176 struct candevice_t *hostdevice;
178 int max_objects; /* 1 for sja1000, 15 for i82527 */
180 can_spinlock_t chip_lock;
183 pthread_t worker_thread;
184 unsigned long pend_flags;
185 #endif /*CAN_WITH_RTL*/
189 * struct msgobj_t - structure holding communication object state
191 * @minor: associated device minor number
192 * @object: object number in chip_t structure +1
193 * @flags: message object flags
194 * @ret: field holding status of the last Tx operation
195 * @qends: pointer to message object corresponding ends structure
196 * @tx_qedge: edge corresponding to transmitted message
197 * @tx_slot: slot holding transmitted message, slot is taken from
198 * canque_test_outslot() call and is freed by canque_free_outslot()
199 * or rescheduled canque_again_outslot()
200 * @tx_retry_cnt: transmission attempt counter
201 * @tx_timeout: can be used by chip driver to check for the transmission timeout
202 * @rx_msg: temporary storage to hold received messages before
203 * calling to canque_filter_msg2edges()
204 * @hostchip: pointer to the &chip_t structure this object belongs to
205 * @obj_used: counter of users (associated file structures for Linux
206 * userspace clients) of this object
207 * @obj_users: list of user structures of type &canuser_t.
208 * @obj_flags: message object specific flags. Masks values:
209 * %MSGOBJ_TX_REQUEST .. the message object requests TX activation
210 * %MSGOBJ_TX_LOCK .. some IRQ routine or callback on some CPU
211 * is running inside TX activation processing code
212 * @rx_preconfig_id: place to store RX message identifier for some chip types
213 * that reuse same object for TX
216 unsigned long obj_base_addr;
217 unsigned int minor; /* associated device minor number */
218 unsigned int object; /* object number in chip_t +1 for debug printk */
219 unsigned long obj_flags;
222 struct canque_ends_t *qends;
224 struct canque_edge_t *tx_qedge;
225 struct canque_slot_t *tx_slot;
227 struct timer_list tx_timeout;
229 struct canmsg_t rx_msg;
231 struct chip_t *hostchip;
233 unsigned long rx_preconfig_id;
236 struct list_head obj_users;
239 #define CAN_USER_MAGIC 0x05402033
242 * struct canuser_t - structure holding CAN user/client state
243 * @flags: used to distinguish Linux/RT-Linux type
244 * @peers: for connection into list of object users
245 * @qends: pointer to the ends structure corresponding for this user
246 * @msgobj: communication object the user is connected to
247 * @rx_edge0: default receive queue for filter IOCTL
248 * @userinfo: stores user context specific information.
249 * The field @fileinfo.file holds pointer to open device file state structure
250 * for the Linux user-space client applications
251 * @magic: magic number to check consistency when pointer is retrieved
252 * from file private field
256 struct list_head peers;
257 struct canque_ends_t *qends;
258 struct msgobj_t *msgobj;
259 struct canque_edge_t *rx_edge0; /* simplifies IOCTL */
262 struct file *file; /* back ptr to file */
266 struct rtl_file *file;
268 #endif /*CAN_WITH_RTL*/
274 * struct hwspecops_t - hardware/board specific operations
275 * @request_io: reserve io or memory range for can board
276 * @release_io: free reserved io memory range
277 * @reset: hardware reset routine
278 * @init_hw_data: called to initialize &candevice_t structure, mainly
279 * @res_add, @nr_all_chips, @nr_82527_chips, @nr_sja1000_chips
281 * @init_chip_data: called initialize each &chip_t structure, mainly
282 * @chip_type, @chip_base_addr, @clock and chip specific registers.
283 * It is responsible to setup &chip_t->@chipspecops functions
284 * for non-standard chip types (type other than "i82527", "sja1000" or "sja1000p")
285 * @init_obj_data: called initialize each &msgobj_t structure,
286 * mainly @obj_base_addr field.
287 * @program_irq: program interrupt generation hardware of the board
288 * if flag %PROGRAMMABLE_IRQ is present for specified device/board
289 * @write_register: low level write register routine
290 * @read_register: low level read register routine
293 int (*request_io)(struct candevice_t *candev);
294 int (*release_io)(struct candevice_t *candev);
295 int (*reset)(struct candevice_t *candev);
296 int (*init_hw_data)(struct candevice_t *candev);
297 int (*init_chip_data)(struct candevice_t *candev, int chipnr);
298 int (*init_obj_data)(struct chip_t *chip, int objnr);
299 int (*program_irq)(struct candevice_t *candev);
300 void (*write_register)(unsigned data,unsigned long address);
301 unsigned (*read_register)(unsigned long address);
305 * struct chipspecops_t - can controller chip specific operations
306 * @chip_config: CAN chip configuration
307 * @baud_rate: set communication parameters
308 * @standard_mask: setup of mask for message filtering
309 * @extended_mask: setup of extended mask for message filtering
310 * @message15_mask: set mask of i82527 message object 15
311 * @clear_objects: clears state of all message object residing in chip
312 * @config_irqs: tunes chip hardware interrupt delivery
313 * @pre_read_config: prepares message object for message reception
314 * @pre_write_config: prepares message object for message transmission
315 * @send_msg: initiate message transmission
316 * @remote_request: configures message object and asks for RTR message
317 * @check_tx_stat: checks state of transmission engine
318 * @wakeup_tx: wakeup TX processing
319 * @filtch_rq: optional routine for propagation of outgoing edges filters to HW
320 * @enable_configuration: enable chip configuration mode
321 * @disable_configuration: disable chip configuration mode
322 * @set_btregs: configures bitrate registers
323 * @start_chip: starts chip message processing
324 * @stop_chip: stops chip message processing
325 * @irq_handler: interrupt service routine
327 struct chipspecops_t {
328 int (*chip_config)(struct chip_t *chip);
329 int (*baud_rate)(struct chip_t *chip, int rate, int clock, int sjw,
330 int sampl_pt, int flags);
331 int (*standard_mask)(struct chip_t *chip, unsigned short code,
332 unsigned short mask);
333 int (*extended_mask)(struct chip_t *chip, unsigned long code,
335 int (*message15_mask)(struct chip_t *chip, unsigned long code,
337 int (*clear_objects)(struct chip_t *chip);
338 int (*config_irqs)(struct chip_t *chip, short irqs);
339 int (*pre_read_config)(struct chip_t *chip, struct msgobj_t *obj);
340 int (*pre_write_config)(struct chip_t *chip, struct msgobj_t *obj,
341 struct canmsg_t *msg);
342 int (*send_msg)(struct chip_t *chip, struct msgobj_t *obj,
343 struct canmsg_t *msg);
344 int (*remote_request)(struct chip_t *chip, struct msgobj_t *obj);
345 int (*check_tx_stat)(struct chip_t *chip);
346 int (*wakeup_tx)(struct chip_t *chip, struct msgobj_t *obj);
347 int (*filtch_rq)(struct chip_t *chip, struct msgobj_t *obj);
348 int (*enable_configuration)(struct chip_t *chip);
349 int (*disable_configuration)(struct chip_t *chip);
350 int (*set_btregs)(struct chip_t *chip, unsigned short btr0,
351 unsigned short btr1);
352 int (*start_chip)(struct chip_t *chip);
353 int (*stop_chip)(struct chip_t *chip);
354 can_irqreturn_t (*irq_handler)(int irq, void *dev_id, struct pt_regs *regs);
359 struct mem_addr *next;
363 /* Structure for the RTR queue */
366 struct canmsg_t *rtr_message;
367 wait_queue_head_t rtr_wq;
372 extern int minor[MAX_TOT_CHIPS];
374 extern int baudrate[MAX_TOT_CHIPS];
375 extern char *hw[MAX_HW_CARDS];
376 extern int irq[MAX_IRQ];
377 extern unsigned long io[MAX_HW_CARDS];
378 extern int processlocal;
380 extern struct canhardware_t *hardware_p;
381 extern struct chip_t *chips_p[MAX_TOT_CHIPS];
382 extern struct msgobj_t *objects_p[MAX_TOT_MSGOBJS];
384 extern struct mem_addr *mem_head;
387 #if defined(CONFIG_OC_LINCAN_PORTIO_ONLY)
388 extern inline void can_write_reg(const struct chip_t *chip, unsigned char data, unsigned address)
390 outb(data, chip->chip_base_addr+address);
392 extern inline unsigned can_read_reg(const struct chip_t *chip, unsigned address)
394 return inb(chip->chip_base_addr+address);
396 extern inline void canobj_write_reg(const struct chip_t *chip, const struct msgobj_t *obj,
397 unsigned char data, unsigned address)
399 outb(data, obj->obj_base_addr+address);
401 extern inline unsigned canobj_read_reg(const struct chip_t *chip, const struct msgobj_t *obj,
404 return inb(obj->obj_base_addr+address);
407 #elif defined(CONFIG_OC_LINCAN_MEMIO_ONLY)
408 extern inline void can_write_reg(const struct chip_t *chip, unsigned char data, unsigned address)
410 writeb(data, chip->chip_base_addr+address);
412 extern inline unsigned can_read_reg(const struct chip_t *chip, unsigned address)
414 return readb(chip->chip_base_addr+address);
416 extern inline void canobj_write_reg(const struct chip_t *chip, const struct msgobj_t *obj,
417 unsigned char data, unsigned address)
419 writeb(data, obj->obj_base_addr+address);
421 extern inline unsigned canobj_read_reg(const struct chip_t *chip, const struct msgobj_t *obj,
424 return readb(obj->obj_base_addr+address);
427 #else /*CONFIG_OC_LINCAN_DYNAMICIO*/
428 #ifndef CONFIG_OC_LINCAN_DYNAMICIO
429 #define CONFIG_OC_LINCAN_DYNAMICIO
432 /* Inline function to write to the hardware registers. The argument address is
433 * relative to the memory map of the chip and not the absolute memory address.
435 extern inline void can_write_reg(const struct chip_t *chip, unsigned char data, unsigned address)
437 unsigned long address_to_write;
438 address_to_write = chip->chip_base_addr+address;
439 chip->write_register(data, address_to_write);
442 extern inline unsigned can_read_reg(const struct chip_t *chip, unsigned address)
444 unsigned long address_to_read;
445 address_to_read = chip->chip_base_addr+address;
446 return chip->read_register(address_to_read);
449 extern inline void canobj_write_reg(const struct chip_t *chip, const struct msgobj_t *obj,
450 unsigned char data, unsigned address)
452 unsigned long address_to_write;
453 address_to_write = obj->obj_base_addr+address;
454 chip->write_register(data, address_to_write);
457 extern inline unsigned canobj_read_reg(const struct chip_t *chip, const struct msgobj_t *obj,
460 unsigned long address_to_read;
461 address_to_read = obj->obj_base_addr+address;
462 return chip->read_register(address_to_read);
465 #endif /*CONFIG_OC_LINCAN_DYNAMICIO*/
467 int can_base_addr_fixup(struct candevice_t *candev, unsigned long new_base);
468 int can_request_io_region(unsigned long start, unsigned long n, const char *name);
469 void can_release_io_region(unsigned long start, unsigned long n);
470 int can_request_mem_region(unsigned long start, unsigned long n, const char *name);
471 void can_release_mem_region(unsigned long start, unsigned long n);
474 const char *boardtype;
475 int (*board_register)(struct hwspecops_t *hwspecops);
479 const struct boardtype_t* boardtype_find(const char *str);
481 int can_check_dev_taken(void *anydev);
484 extern int can_rtl_priority;
485 #endif /*CAN_WITH_RTL*/