2 * Linux CAN-bus device driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
5 * email:pisa@cmp.felk.cvut.cz
6 * Adapted for actual PIP5 Version and PIP7 and PIP8 by
7 * Stefan Peter, MPL AG, Switzerland
9 * This software is released under the GPL-License.
10 * Version lincan-0.3 17 Jun 2004
12 /* This is the CAN driver for the PIP5,PIP6,PIP7 and PIP8
13 * Packaged Industrial PCs of MPL AG, Switzerland.
17 #include "../include/can.h"
18 #include "../include/can_sysdep.h"
19 #include "../include/main.h"
20 #include "../include/pip.h"
21 #include "../include/i82527.h"
22 /* PIP Specific Extension registers */
23 #define PIP_CANRES_REG 0x804 /* CAN Resources */
24 #define PIP_CANCTRL_REG (PIP_CANRES_REG+1) /* CAN Control */
25 /* Interrupt maps for the various PIP variants, see user manual */
26 #define PIP5_IRQ_MAP 0x4F6D
27 #define PIP6_IRQ_MAP 0xDEF8
28 #define PIP7_IRQ_MAP 0x3768
29 #define PIP8_IRQ_MAP 0x3768
31 int pip_request_io(struct candevice_t *candev)
33 if ((candev->io_addr != 0x1000) && (candev->io_addr != 0x8000)
34 && (candev->io_addr != 0xe000)) {
35 CANMSG("Invalid base io address\n");
37 ("Valid values for the PIP are: 0x1000, 0x8000 or 0xe000\n");
38 CANMSG("Please consult your user manual.\n");
41 if (!can_request_io_region(candev->io_addr, 0x100, DEVICE_NAME)) {
42 CANMSG("Unable to open port: 0x%lx\n", candev->io_addr);
45 if (!can_request_io_region(PIP_CANRES_REG, 0x02, DEVICE_NAME))
47 can_release_io_region(candev->io_addr, 0x100);
48 CANMSG("Unable to open port: 0x%x\n", PIP_CANRES_REG);
51 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n",
52 candev->io_addr, candev->io_addr + 0x100 - 1);
53 DEBUGMSG("Registered IO-memory : 0x%x - 0x%x\n",
54 PIP_CANRES_REG, PIP_CANCTRL_REG);
59 int pip_release_io(struct candevice_t *candev)
61 can_release_io_region(candev->io_addr, 0x100);
62 can_release_io_region(PIP_CANRES_REG, 0x02);
67 int pip_reset(struct candevice_t *candev)
71 DEBUGMSG("Resetting %s hardware ...\n", candev->hwname);
74 outb(0x01, candev->res_addr);
76 outb(0x0, candev->res_addr);
78 /* Check hardware reset status */
80 while ((inb(candev->io_addr + iCPU) & iCPU_RST) && (i <= 15)) {
85 CANMSG("Reset status timeout!\n");
86 CANMSG("Please check your hardware.\n");
89 DEBUGMSG("Chip0 reset status ok.\n");
95 int pip_init_hw_data(struct candevice_t *candev)
97 candev->res_addr = PIP_CANCTRL_REG;
98 candev->nr_82527_chips = 1;
99 candev->nr_sja1000_chips = 0;
100 candev->nr_all_chips = 1;
101 candev->flags |= CANDEV_PROGRAMMABLE_IRQ;
106 int pip_init_chip_data(struct candevice_t *candev, int chipnr)
108 i82527_fill_chipspecops(candev->chip[chipnr]);
109 candev->chip[chipnr]->chip_base_addr = candev->io_addr;
110 candev->chip[chipnr]->clock = 8000000;
111 candev->chip[chipnr]->int_cpu_reg = 0;
112 candev->chip[chipnr]->int_clk_reg = iCLK_SL1;
113 candev->chip[chipnr]->int_bus_reg = iBUS_CBY;
114 candev->chip[chipnr]->sja_cdr_reg = 0;
115 candev->chip[chipnr]->sja_ocr_reg = 0;
120 int pip_init_obj_data(struct canchip_t *chip, int objnr)
122 chip->msgobj[objnr]->obj_base_addr =
123 chip->chip_base_addr + (objnr + 1) * 0x10;
128 int pip_program_irq(struct candevice_t *candev)
130 unsigned int irq_mask;
131 unsigned char can_addr = 0, can_reg = 0;
132 DEBUGMSG("pip_program_irq\n");
133 /* Reset can controller */
134 outb(0x01, candev->res_addr);
135 if (strcmp(candev->hwname, "pip5") == 0) {
136 irq_mask = PIP5_IRQ_MAP;
137 } else if (strcmp(candev->hwname, "pip6") == 0) {
138 irq_mask = PIP6_IRQ_MAP;
139 } else if (strcmp(candev->hwname, "pip7") == 0) {
140 irq_mask = PIP7_IRQ_MAP;
141 } else if (strcmp(candev->hwname, "pip8") == 0) {
142 irq_mask = PIP8_IRQ_MAP;
144 CANMSG("Unsupported PIP specified.\n");
147 if ((candev->chip[0]->chip_irq < 1)
148 || (candev->chip[0]->chip_irq > 15)) {
149 CANMSG("Interrupt specified does not exist.\n");
152 if (((0x01 << (candev->chip[0]->chip_irq - 1)) & irq_mask) == 0) {
153 CANMSG("Invalid Interrupt specified %d\n",
154 candev->chip[0]->chip_irq);
158 /* set the IRQ routing of the board accordingly */
159 switch (candev->io_addr) {
174 ("Supplied io address is not valid, please check your manual\n");
178 can_reg = inb(PIP_CANRES_REG);
179 DEBUGMSG("PIP_CANRES was 0x%x\n", can_reg);
180 can_reg = (candev->chip[0]->chip_irq << 4) | can_addr;
181 DEBUGMSG("Setting PIP_CANRES_REG to 0x%x\n", can_reg);
182 outb((candev->chip[0]->chip_irq << 4) | can_addr, PIP_CANRES_REG);
183 /* re-enable the chip */
184 outb(0x00, candev->res_addr);
190 void pip_write_register(unsigned data, unsigned long address)
195 unsigned pip_read_register(unsigned long address)
200 /* !!! Don't change these functions !!! */
201 int pip_register(struct hwspecops_t *hwspecops)
203 hwspecops->request_io = pip_request_io;
204 hwspecops->release_io = pip_release_io;
205 hwspecops->reset = pip_reset;
206 hwspecops->init_hw_data = pip_init_hw_data;
207 hwspecops->init_chip_data = pip_init_chip_data;
208 hwspecops->init_obj_data = pip_init_obj_data;
209 hwspecops->write_register = pip_write_register;
210 hwspecops->read_register = pip_read_register;
211 hwspecops->program_irq = pip_program_irq;