2 * Linux CAN-bus device driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * This software is released under the GPL-License.
5 * Version 0.6 18 Sept 2000
6 * Changed for PeliCan mode SJA1000 by Tomasz Motylewski (BFAD GmbH)
10 #include <linux/autoconf.h>
11 #if defined (CONFIG_MODVERSIONS) && !defined (MODVERSIONS)
15 #if defined (MODVERSIONS)
16 #include <linux/modversions.h>
19 #include <linux/sched.h>
20 #include <linux/delay.h>
23 #include "../include/main.h"
24 #include "../include/sja1000p.h"
26 int sja1000p_enable_configuration(struct chip_t *chip)
29 enum sja1000_PeliCAN_MOD flags;
31 disable_irq(chip->chip_irq);
33 flags=can_read_reg(chip,SJAMOD);
35 while ((!(flags & MOD_RM)) && (i<=10)) {
36 can_write_reg(chip, MOD_RM, SJAMOD);
37 // TODO: configurable MOD_AFM (32/16 bit acceptance filter)
38 // config MOD_LOM (listen only)
41 flags=can_read_reg(chip, SJAMOD);
44 CANMSG("Reset error\n");
45 enable_irq(chip->chip_irq);
52 int sja1000p_disable_configuration(struct chip_t *chip)
55 enum sja1000_PeliCAN_MOD flags;
57 flags=can_read_reg(chip,SJAMOD);
59 while ( (flags & MOD_RM) && (i<=50) ) {
60 // could be as long as 11*128 bit times after buss-off
61 can_write_reg(chip, 0, SJAMOD);
62 // TODO: configurable MOD_AFM (32/16 bit acceptance filter)
63 // config MOD_LOM (listen only)
66 flags=can_read_reg(chip, SJAMOD);
69 CANMSG("Error leaving reset status\n");
73 enable_irq(chip->chip_irq);
78 int sja1000p_chip_config(struct chip_t *chip)
80 if (sja1000p_enable_configuration(chip))
83 /* Set mode, clock out, comparator */
84 can_write_reg(chip,CDR_PELICAN|chip->sja_cdr_reg,SJACDR);
85 /* Set driver output configuration */
86 can_write_reg(chip,chip->sja_ocr_reg,SJAOCR);
88 if (sja1000p_extended_mask(chip,0x00000000, 0xffffffff))
93 if (sja1000p_baud_rate(chip,1000*baudrate,chip->clock,0,75,0))
96 /* Enable hardware interrupts */
97 can_write_reg(chip, ENABLE_INTERRUPTS, SJAIER);
99 sja1000p_disable_configuration(chip);
104 int sja1000p_extended_mask(struct chip_t *chip, unsigned long code, unsigned long mask)
108 if (sja1000p_enable_configuration(chip))
111 // LSB to +3, MSB to +0
112 for(i=SJA_PeliCAN_AC_LEN; --i>=0;) {
113 can_write_reg(chip,code&0xff,SJAACR0+i);
114 can_write_reg(chip,mask&0xff,SJAAMR0+i);
119 DEBUGMSG("Setting acceptance code to 0x%lx\n",(unsigned long)code);
120 DEBUGMSG("Setting acceptance mask to 0x%lx\n",(unsigned long)mask);
122 sja1000p_disable_configuration(chip);
127 /* Set communication parameters.
128 * param rate baud rate in Hz
129 * param clock frequency of sja1000 clock in Hz (ISA osc is 14318000)
130 * param sjw synchronization jump width (0-3) prescaled clock cycles
131 * param sampl_pt sample point in % (0-100) sets (TSEG1+1)/(TSEG1+TSEG2+2) ratio
132 * param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP
134 int sja1000p_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,
135 int sampl_pt, int flags)
137 int best_error = 1000000000, error;
138 int best_tseg=0, best_brp=0, best_rate=0, brp=0;
139 int tseg=0, tseg1=0, tseg2=0;
141 if (sja1000p_enable_configuration(chip))
146 /* tseg even = round down, odd = round up */
147 for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++) {
148 brp = clock/((1+tseg/2)*rate)+tseg%2;
149 if (brp == 0 || brp > 64)
151 error = rate - clock/(brp*(1+tseg/2));
154 if (error <= best_error) {
158 best_rate = clock/(brp*(1+tseg/2));
161 if (best_error && (rate/best_error < 10)) {
162 CANMSG("baud rate %d is not possible with %d Hz clock\n",
164 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
165 best_rate, best_brp, best_tseg, tseg1, tseg2);
168 tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
171 if (tseg2 > MAX_TSEG2)
173 tseg1 = best_tseg-tseg2-2;
174 if (tseg1>MAX_TSEG1) {
176 tseg2 = best_tseg-tseg1-2;
179 DEBUGMSG("Setting %d bps.\n", best_rate);
180 DEBUGMSG("brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
181 best_brp, best_tseg, tseg1, tseg2,
182 (100*(best_tseg-tseg2)/(best_tseg+1)));
185 can_write_reg(chip, sjw<<6 | best_brp, SJABTR0);
186 can_write_reg(chip, ((flags & BTR1_SAM) != 0)<<7 | (tseg2<<4)
189 sja1000p_disable_configuration(chip);
194 void sja1000p_read(struct chip_t *chip, struct canfifo_t *fifo) {
195 int i, flags, len, datastart;
197 flags = can_read_reg(chip,SJAFRM);
199 fifo->rx_writep->id =
200 (can_read_reg(chip,SJAID0)<<21) +
201 (can_read_reg(chip,SJAID1)<<13) +
202 (can_read_reg(chip,SJAID2)<<5) +
203 (can_read_reg(chip,SJAID3)>>3);
206 fifo->rx_writep->id =
207 (can_read_reg(chip,SJAID0)<<3) +
208 (can_read_reg(chip,SJAID1)>>5);
211 fifo->rx_writep->flags =
212 ((flags & FRM_RTR) ? MSG_RTR : 0) |
213 ((flags & FRM_FF) ? MSG_EXT : 0);
214 len = flags & FRM_DLC_M;
215 for(i=0; i< len; i++) {
216 fifo->rx_writep->data[i]=can_read_reg(chip,datastart+i);
218 fifo->rx_writep->length = len;
221 if (fifo->rx_writep >= fifo->buf_rx_entry + MAX_BUF_LENGTH)
222 fifo->rx_writep = fifo->buf_rx_entry;
224 // FIXME: what if fifo->rx_writep == fifo->rx_readp again ?
226 can_write_reg(chip, CMR_RRB, SJACMR);
227 } while (can_read_reg(chip, SJASR) & SR_RBS);
230 int sja1000p_pre_read_config(struct chip_t *chip, struct msgobj_t *obj)
233 status=can_read_reg(chip,SJASR);
236 /* Try to recover from error condition */
237 DEBUGMSG("sja1000p_pre_read_config bus-off recover 0x%x\n",status);
238 sja1000p_enable_configuration(chip);
239 can_write_reg(chip, 0, SJARXERR);
240 can_write_reg(chip, 0, SJATXERR1);
241 can_read_reg(chip, SJAECC);
242 sja1000p_disable_configuration(chip);
245 if (!(status&SR_RBS)) {
249 can_write_reg(chip, DISABLE_INTERRUPTS, SJAIER); //disable interrupts for a moment
250 sja1000p_read(chip, obj->fifo);
251 can_write_reg(chip, ENABLE_INTERRUPTS, SJAIER); //enable interrupts
255 #define MAX_TRANSMIT_WAIT_LOOPS 200
256 int sja1000p_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
257 struct canmsg_t *msg)
263 /* Wait until Transmit Buffer Status is released */
264 while ( !((status=can_read_reg(chip, SJASR)) & SR_TBS) &&
265 i++<MAX_TRANSMIT_WAIT_LOOPS) {
270 /* Try to recover from error condition */
271 DEBUGMSG("sja1000p_pre_write_config bus-off recover 0x%x\n",status);
272 sja1000p_enable_configuration(chip);
273 can_write_reg(chip, 0, SJARXERR);
274 can_write_reg(chip, 0, SJATXERR1);
275 can_read_reg(chip, SJAECC);
276 sja1000p_disable_configuration(chip);
278 if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
279 CANMSG("Transmit timed out, cancelling\n");
280 // here we should check if there is no write/select waiting for this
281 // transmit. If so, set error ret and wake up.
282 // CHECKME: if we do not disable IER_TIE (TX IRQ) here we get interrupt
284 can_write_reg(chip, CMR_AT, SJACMR);
286 while ( !(can_read_reg(chip, SJASR) & SR_TBS) &&
287 i++<MAX_TRANSMIT_WAIT_LOOPS) {
290 if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
291 CANMSG("Could not cancel, please reset\n");
295 msg->length &= FRM_DLC_M;
296 can_write_reg(chip, ((msg->flags&MSG_EXT)?FRM_FF:0) |
297 ((msg->flags & MSG_RTR) ? FRM_RTR : 0) |
298 msg->length, SJAFRM);
299 if(msg->flags&MSG_EXT) {
301 can_write_reg(chip, id & 0xff, SJAID3);
303 can_write_reg(chip, id & 0xff, SJAID2);
305 can_write_reg(chip, id & 0xff, SJAID1);
307 can_write_reg(chip, id, SJAID0);
308 for(i=0; i < msg->length; i++) {
309 can_write_reg(chip, msg->data[i], SJADATE+i);
313 can_write_reg(chip, (id >> 8) & 0xff, SJAID0);
314 can_write_reg(chip, id & 0xff, SJAID1);
315 for(i=0; i < msg->length; i++) {
316 can_write_reg(chip, msg->data[i], SJADATS+i);
322 int sja1000p_send_msg(struct chip_t *chip, struct msgobj_t *obj,
323 struct canmsg_t *msg)
325 can_write_reg(chip, CMR_TR, SJACMR);
330 int sja1000p_check_tx_stat(struct chip_t *chip)
332 if (can_read_reg(chip,SJASR) & SR_TCS)
338 int sja1000p_set_btregs(struct chip_t *chip, unsigned short btr0,
341 if (sja1000p_enable_configuration(chip))
344 can_write_reg(chip, btr0, SJABTR0);
345 can_write_reg(chip, btr1, SJABTR1);
347 sja1000p_disable_configuration(chip);
352 int sja1000p_start_chip(struct chip_t *chip)
354 enum sja1000_PeliCAN_MOD flags;
356 flags = can_read_reg(chip, SJAMOD) & (MOD_LOM|MOD_STM|MOD_AFM|MOD_SM);
357 can_write_reg(chip, flags, SJAMOD);
362 int sja1000p_stop_chip(struct chip_t *chip)
364 enum sja1000_PeliCAN_MOD flags;
366 flags = can_read_reg(chip, SJAMOD) & (MOD_LOM|MOD_STM|MOD_AFM|MOD_SM);
367 can_write_reg(chip, flags|MOD_RM, SJAMOD);
373 int sja1000p_remote_request(struct chip_t *chip, struct msgobj_t *obj)
375 CANMSG("sja1000p_remote_request not implemented\n");
379 int sja1000p_standard_mask(struct chip_t *chip, unsigned short code,
382 CANMSG("sja1000p_standard_mask not implemented\n");
386 int sja1000p_clear_objects(struct chip_t *chip)
388 CANMSG("sja1000p_clear_objects not implemented\n");
392 int sja1000p_config_irqs(struct chip_t *chip, short irqs)
394 CANMSG("sja1000p_config_irqs not implemented\n");
398 void sja1000p_irq_write_handler(struct chip_t *chip, struct canfifo_t *fifo)
401 if (fifo->tx_readp >= fifo->buf_tx_entry + MAX_BUF_LENGTH)
402 fifo->tx_readp = fifo->buf_tx_entry;
403 if (fifo->tx_readp == fifo->tx_writep) { // Output buffer is empty
404 fifo->tx_in_progress = 0;
405 if (waitqueue_active(&fifo->writeq)) {
406 chip->msgobj[0]->ret = 0; //CHECKME or 26?
407 wake_up_interruptible(&fifo->writeq);
411 if (chip->chipspecops->pre_write_config(chip, chip->msgobj[0],
413 if (waitqueue_active(&fifo->writeq)) {
414 chip->msgobj[0]->ret = -1;
415 wake_up_interruptible(&fifo->writeq);
419 if (chip->chipspecops->send_msg(chip, chip->msgobj[0],
421 if (waitqueue_active(&fifo->writeq)) {
422 chip->msgobj[0]->ret = -1;
423 wake_up_interruptible(&fifo->writeq);
432 void sja1000p_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
434 int irq_register, status, error_code;
435 int static retransmitted=0; /* FIXME - should go into chip struct */
436 struct chip_t *chip=(struct chip_t *)dev_id;
437 struct canfifo_t *fifo;
439 irq_register=can_read_reg(chip,SJAIR);
440 // DEBUGMSG("sja1000_irq_handler: SJAIR:%02x\n",irq_register);
441 // DEBUGMSG("sja1000_irq_handler: SJASR:%02x\n",
442 // can_read_reg(chip,SJASR));
444 if ((irq_register & (IR_BEI|IR_EPI|IR_DOI|IR_EI|IR_TI|IR_RI)) == 0)
447 if(!chip->msgobj[0]->flags & BUFFERS_ALLOCATED) {
448 CANMSG("sja1000p_irq_handler: called with device closed, irq_register 0x%02x\n", irq_register);
451 fifo=chip->msgobj[0]->fifo;
453 if ((irq_register & IR_RI) != 0) {
454 sja1000p_read(chip,fifo);
455 chip->msgobj[0]->ret = 0;
456 if (waitqueue_active(&fifo->readq))
457 wake_up_interruptible(&fifo->readq);
459 if ((irq_register & IR_TI) != 0) {
460 chip->msgobj[0]->ret = 0;
461 sja1000p_irq_write_handler(chip,fifo);
463 if ((irq_register & (IR_EI|IR_BEI|IR_EPI|IR_DOI)) != 0) {
464 // Some error happened
465 status=can_read_reg(chip,SJASR);
466 error_code=can_read_reg(chip,SJAECC);
467 CANMSG("Error: status register: 0x%x irq_register: 0x%02x error: 0x%02x\n",
468 status, irq_register, error_code);
469 // FIXME: chip should be brought to usable state. Transmission cancelled if in progress.
470 // Reset flag set to 0 if chip is already off the bus. Full state report
471 chip->msgobj[0]->ret=-1;
473 if(error_code == 0xd9) {
474 chip->msgobj[0]->ret= -ENXIO;
475 /* no such device or address - no ACK received */
477 if(retransmitted++>MAX_RETR) {
478 can_write_reg(chip, CMR_AT, SJACMR); // cancel any transmition
482 CANMSG("bus-off, resetting sja1000p\n");
483 can_write_reg(chip, 0, SJAMOD);
486 if (waitqueue_active(&fifo->writeq))
487 wake_up_interruptible(&fifo->writeq);
488 if (waitqueue_active(&fifo->readq))
489 wake_up_interruptible(&fifo->readq);
497 int sja1000p_register(struct chipspecops_t *chipspecops)
499 CANMSG("initializing sja1000p chip operations\n");
500 chipspecops->chip_config=sja1000p_chip_config;
501 chipspecops->baud_rate=sja1000p_baud_rate;
502 chipspecops->standard_mask=sja1000p_standard_mask;
503 chipspecops->extended_mask=sja1000p_extended_mask;
504 chipspecops->message15_mask=sja1000p_extended_mask;
505 chipspecops->clear_objects=sja1000p_clear_objects;
506 chipspecops->config_irqs=sja1000p_config_irqs;
507 chipspecops->pre_read_config=sja1000p_pre_read_config;
508 chipspecops->pre_write_config=sja1000p_pre_write_config;
509 chipspecops->send_msg=sja1000p_send_msg;
510 chipspecops->check_tx_stat=sja1000p_check_tx_stat;
511 chipspecops->remote_request=sja1000p_remote_request;
512 chipspecops->enable_configuration=sja1000p_enable_configuration;
513 chipspecops->disable_configuration=sja1000p_disable_configuration;
514 chipspecops->set_btregs=sja1000p_set_btregs;
515 chipspecops->start_chip=sja1000p_start_chip;
516 chipspecops->stop_chip=sja1000p_stop_chip;
517 chipspecops->irq_handler=sja1000p_irq_handler;