More updates in the C_CAN support, but locking not reworked still.
[lincan.git] / lincan / src / i82527.c
1 /* i82527.c
2  * Linux CAN-bus device driver.
3  * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4  * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
5  * email:pisa@cmp.felk.cvut.cz
6  * This software is released under the GPL-License.
7  * Version lincan-0.3  17 Jun 2004
8  */
9
10 #include "../include/can.h"
11 #include "../include/can_sysdep.h"
12 #include "../include/main.h"
13 #include "../include/i82527.h"
14
15 void i82527_irq_rtr_handler(struct canchip_t *chip, struct msgobj_t *obj, 
16                             struct rtr_id *rtr_search, unsigned long message_id);
17
18
19 extern int stdmask;
20 extern int extmask;
21 extern int mo15mask;
22
23 /* helper functions for segmented cards read and write configuration and status registers
24    above 0xf offset */
25
26 void i82527_seg_write_reg(const struct canchip_t *chip, unsigned char data, unsigned address)
27 {
28         if((address > 0xf) && (chip->flags & CHIP_SEGMENTED))
29                 canobj_write_reg(chip, chip->msgobj[(address>>4)-1],data, address & 0xf);
30         else
31                 can_write_reg(chip, data, address);
32 }
33
34 unsigned i82527_seg_read_reg(const struct canchip_t *chip, unsigned address)
35 {
36         if((address > 0xf) && (chip->flags & CHIP_SEGMENTED))
37                 return canobj_read_reg(chip, chip->msgobj[(address>>4)-1], address & 0xf);
38         else
39                 return can_read_reg(chip, address);
40 }
41
42 int i82527_enable_configuration(struct canchip_t *chip)
43 {
44         unsigned short flags=0;
45
46         flags = can_read_reg(chip, iCTL) & (iCTL_IE|iCTL_SIE|iCTL_EIE);
47         can_write_reg(chip, flags|iCTL_CCE, iCTL);
48         
49         return 0;
50 }
51
52 int i82527_disable_configuration(struct canchip_t *chip)
53 {
54         unsigned short flags=0;
55
56         flags = can_read_reg(chip, iCTL) & (iCTL_IE|iCTL_SIE|iCTL_EIE);
57         can_write_reg(chip, flags, iCTL);
58
59         return 0;
60 }
61
62 int i82527_chip_config(struct canchip_t *chip)
63 {
64         can_write_reg(chip,chip->int_cpu_reg,iCPU); // Configure cpu interface
65         can_write_reg(chip,(iCTL_CCE|iCTL_INI),iCTL); // Enable configuration
66         i82527_seg_write_reg(chip,chip->int_clk_reg,iCLK); // Set clock out slew rates 
67         i82527_seg_write_reg(chip,chip->int_bus_reg,iBUS); /* Bus configuration */
68         can_write_reg(chip,0x00,iSTAT); /* Clear error status register */
69
70         /* Check if we can at least read back some arbitrary data from the 
71          * card. If we can not, the card is not properly configured!
72          */
73         canobj_write_reg(chip,chip->msgobj[1],0x25,iMSGDAT1);
74         canobj_write_reg(chip,chip->msgobj[2],0x52,iMSGDAT3);
75         canobj_write_reg(chip,chip->msgobj[10],0xc3,iMSGDAT6);
76         if ( (canobj_read_reg(chip,chip->msgobj[1],iMSGDAT1) != 0x25) ||
77               (canobj_read_reg(chip,chip->msgobj[2],iMSGDAT3) != 0x52) ||
78               (canobj_read_reg(chip,chip->msgobj[10],iMSGDAT6) != 0xc3) ) {
79                 CANMSG("Could not read back from the hardware.\n");
80                 CANMSG("This probably means that your hardware is not correctly configured!\n");
81                 return -1;
82         }
83         else
84                 DEBUGMSG("Could read back, hardware is probably configured correctly\n");
85
86         if (chip->baudrate == 0)
87                 chip->baudrate=1000000;
88
89         if (i82527_baud_rate(chip,chip->baudrate,chip->clock,0,75,0)) {
90                 CANMSG("Error configuring baud rate\n");
91                 return -ENODEV;
92         }
93         if (i82527_standard_mask(chip,0x0000,stdmask)) {
94                 CANMSG("Error configuring standard mask\n");
95                 return -ENODEV;
96         }
97         if (i82527_extended_mask(chip,0x00000000,extmask)) {
98                 CANMSG("Error configuring extended mask\n");
99                 return -ENODEV;
100         }
101         if (i82527_message15_mask(chip,0x00000000,mo15mask)) {
102                 CANMSG("Error configuring message 15 mask\n");
103                 return -ENODEV;
104         }
105         if (i82527_clear_objects(chip)) {
106                 CANMSG("Error clearing message objects\n");
107                 return -ENODEV;
108         }
109         if (i82527_config_irqs(chip,iCTL_IE|iCTL_EIE)) { /* has been 0x0a */
110                 CANMSG("Error configuring interrupts\n");
111                 return -ENODEV;
112         }
113
114         return 0;
115 }
116
117 /* Set communication parameters.
118  * param rate baud rate in Hz
119  * param clock frequency of i82527 clock in Hz (ISA osc is 14318000)
120  * param sjw synchronization jump width (0-3) prescaled clock cycles
121  * param sampl_pt sample point in % (0-100) sets (TSEG1+2)/(TSEG1+TSEG2+3) ratio
122  * param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP
123  */
124 int i82527_baud_rate(struct canchip_t *chip, int rate, int clock, int sjw,
125                                                         int sampl_pt, int flags)
126 {
127         int best_error = 1000000000, error;
128         int best_tseg=0, best_brp=0, best_rate=0, brp=0;
129         int tseg=0, tseg1=0, tseg2=0;
130         
131         if (i82527_enable_configuration(chip))
132                 return -ENODEV;
133
134         if(chip->int_cpu_reg & iCPU_DSC)
135                 clock /=2;
136
137         /* tseg even = round down, odd = round up */
138         for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++) {
139                 brp = clock/((1+tseg/2)*rate)+tseg%2;
140                 if (brp == 0 || brp > 64)
141                         continue;
142                 error = rate - clock/(brp*(1+tseg/2));
143                 if (error < 0)
144                         error = -error;
145                 if (error <= best_error) {
146                         best_error = error;
147                         best_tseg = tseg/2;
148                         best_brp = brp-1;
149                         best_rate = clock/(brp*(1+tseg/2));
150                 }
151         }
152         if (best_error && (rate/best_error < 10)) {
153                 CANMSG("baud rate %d is not possible with %d Hz clock\n",
154                                                                 rate, 2*clock);
155                 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
156                                 best_rate, best_brp, best_tseg, tseg1, tseg2);
157                 return -EINVAL;
158         }
159         tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
160         if (tseg2 < 0)
161                 tseg2 = 0;
162         if (tseg2 > MAX_TSEG2)
163                 tseg2 = MAX_TSEG2;
164         
165         tseg1 = best_tseg-tseg2-2;
166         if (tseg1>MAX_TSEG1) {
167                 tseg1 = MAX_TSEG1;
168                 tseg2 = best_tseg-tseg1-2;
169         }
170
171         DEBUGMSG("Setting %d bps.\n", best_rate);
172         DEBUGMSG("brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
173                                         best_brp, best_tseg, tseg1, tseg2,
174                                         (100*(best_tseg-tseg2)/(best_tseg+1)));
175                                         
176                                 
177         i82527_seg_write_reg(chip, sjw<<6 | best_brp, iBT0);
178         can_write_reg(chip, ((flags & BTR1_SAM) != 0)<<7 | tseg2<<4 | tseg1,
179                                                                 iBT1);
180         DEBUGMSG("Writing 0x%x to iBT0\n",(sjw<<6 | best_brp));
181         DEBUGMSG("Writing 0x%x to iBT1\n",((flags & BTR1_SAM) != 0)<<7 | 
182                                                         tseg2<<4 | tseg1);
183
184         i82527_disable_configuration(chip);
185
186         return 0;
187 }
188
189 int i82527_standard_mask(struct canchip_t *chip, unsigned short code, unsigned short mask)
190 {
191         unsigned char mask0, mask1;
192
193         mask0 = (unsigned char) (mask >> 3);
194         mask1 = (unsigned char) (mask << 5);
195         
196         can_write_reg(chip,mask0,iSGM0);
197         can_write_reg(chip,mask1,iSGM1);
198
199         DEBUGMSG("Setting standard mask to 0x%lx\n",(unsigned long)mask);
200
201         return 0;
202 }
203
204 int i82527_extended_mask(struct canchip_t *chip, unsigned long code, unsigned long mask)
205 {
206         unsigned char mask0, mask1, mask2, mask3;
207
208         mask0 = (unsigned char) (mask >> 21);
209         mask1 = (unsigned char) (mask >> 13);
210         mask2 = (unsigned char) (mask >> 5);
211         mask3 = (unsigned char) (mask << 3);
212
213         can_write_reg(chip,mask0,iEGM0);
214         can_write_reg(chip,mask1,iEGM1);
215         can_write_reg(chip,mask2,iEGM2);
216         can_write_reg(chip,mask3,iEGM3);
217
218         DEBUGMSG("Setting extended mask to 0x%lx\n",(unsigned long)mask);
219
220         return 0;
221 }
222
223 int i82527_message15_mask(struct canchip_t *chip, unsigned long code, unsigned long mask)
224 {
225         unsigned char mask0, mask1, mask2, mask3;
226
227         mask0 = (unsigned char) (mask >> 21);
228         mask1 = (unsigned char) (mask >> 13);
229         mask2 = (unsigned char) (mask >> 5);
230         mask3 = (unsigned char) (mask << 3);
231
232         can_write_reg(chip,mask0,i15M0);
233         can_write_reg(chip,mask1,i15M1);
234         can_write_reg(chip,mask2,i15M2);
235         can_write_reg(chip,mask3,i15M3);
236
237         DEBUGMSG("Setting message 15 mask to 0x%lx\n",mask);
238
239         return 0;
240
241
242 }
243
244 int i82527_clear_objects(struct canchip_t *chip)
245 {
246         int i=0,id=0,data=0;
247         struct msgobj_t *obj;
248
249         DEBUGMSG("Cleared all message objects on chip\n");
250
251         for (i=1; i<=15; i++) {
252                 obj=chip->msgobj[i];
253                 canobj_write_reg(chip,obj,(INTPD_RES|RXIE_RES|TXIE_RES|MVAL_RES),iMSGCTL0);
254                 canobj_write_reg(chip,obj,(NEWD_RES|MLST_RES|TXRQ_RES|RMPD_RES), iMSGCTL1);
255                 for (data=0x07; data<0x0f; data++)
256                         canobj_write_reg(chip,obj,0x00,data);
257                 for (id=2; id<6; id++) {
258                         canobj_write_reg(chip,obj,0x00,id);
259                 }
260                 if (extended==0) {
261                         canobj_write_reg(chip,obj,0x00,iMSGCFG);
262                 }
263                 else {
264                         canobj_write_reg(chip,obj,MCFG_XTD,iMSGCFG);
265                 }
266         }
267         if (extended==0)
268                 DEBUGMSG("All message ID's set to standard\n");
269         else
270                 DEBUGMSG("All message ID's set to extended\n");
271         
272         return 0;
273 }
274
275 int i82527_config_irqs(struct canchip_t *chip, short irqs)
276 {
277         can_write_reg(chip,irqs,iCTL);
278         DEBUGMSG("Configured hardware interrupt delivery\n");
279         return 0;
280 }
281
282 int i82527_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj)
283 {
284         unsigned long id=obj->rx_preconfig_id;
285
286         can_msgobj_set_fl(obj,RX_MODE);
287
288         if (extended || can_msgobj_test_fl(obj,RX_MODE_EXT)) {
289                 id<<=3;
290                 canobj_write_reg(chip,obj,id,iMSGID3);
291                 canobj_write_reg(chip,obj,id>>8,iMSGID2);
292                 canobj_write_reg(chip,obj,id>>16,iMSGID1);
293                 canobj_write_reg(chip,obj,id>>24,iMSGID0);
294                 canobj_write_reg(chip,obj,MCFG_XTD,iMSGCFG);
295         } else {
296                 id<<=5;
297                 canobj_write_reg(chip,obj,id,iMSGID1);
298                 canobj_write_reg(chip,obj,id>>8,iMSGID0);
299                 canobj_write_reg(chip,obj,0x00,iMSGCFG);
300         }
301
302         canobj_write_reg(chip,obj,(NEWD_RES|MLST_RES|TXRQ_RES|RMPD_RES), iMSGCTL1);
303         canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
304
305         DEBUGMSG("i82527_pre_read_config: configured obj at 0x%08lx\n",obj->obj_base_addr);
306
307         return 0;
308 }
309
310 int i82527_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
311                                                         struct canmsg_t *msg)
312 {
313         int i=0,id0=0,id1=0,id2=0,id3=0;
314         int len;
315         
316         len = msg->length;
317         if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
318
319         can_msgobj_clear_fl(obj,RX_MODE);
320
321         canobj_write_reg(chip,obj,(MVAL_SET|TXIE_SET|RXIE_RES|INTPD_RES),iMSGCTL0);
322         canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|CPUU_SET|NEWD_RES),iMSGCTL1);
323
324         if (extended || (msg->flags&MSG_EXT)) {
325                 canobj_write_reg(chip,obj,(len<<4)|(MCFG_DIR|MCFG_XTD),iMSGCFG);
326                 id0 = (unsigned char) (msg->id<<3);
327                 id1 = (unsigned char) (msg->id>>5);
328                 id2 = (unsigned char) (msg->id>>13);
329                 id3 = (unsigned char) (msg->id>>21);
330                 canobj_write_reg(chip,obj,id0,iMSGID3);
331                 canobj_write_reg(chip,obj,id1,iMSGID2);
332                 canobj_write_reg(chip,obj,id2,iMSGID1);
333                 canobj_write_reg(chip,obj,id3,iMSGID0);
334         }
335         else {
336                 canobj_write_reg(chip,obj,(len<<4)|MCFG_DIR,iMSGCFG);
337                 id1 = (unsigned char) (msg->id<<5);
338                 id0 = (unsigned char) (msg->id>>3);
339                 canobj_write_reg(chip,obj,id1,iMSGID1);
340                 canobj_write_reg(chip,obj,id0,iMSGID0);
341         }
342         canobj_write_reg(chip,obj,RMPD_UNC|TXRQ_UNC|CPUU_SET|NEWD_SET,iMSGCTL1);
343         for (i=0; i<len; i++) {
344                 canobj_write_reg(chip,obj,msg->data[i],iMSGDAT0+i);
345         }
346
347         return 0;
348 }
349
350 int i82527_send_msg(struct canchip_t *chip, struct msgobj_t *obj,
351                                                         struct canmsg_t *msg)
352 {
353         canobj_write_reg(chip,obj,(MVAL_SET|TXIE_SET|RXIE_RES|INTPD_RES),iMSGCTL0);
354
355         if (msg->flags & MSG_RTR) {
356                 canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|CPUU_RES|NEWD_SET),iMSGCTL1);
357         }
358         else {
359                 canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_SET|CPUU_RES|NEWD_SET),iMSGCTL1);
360         }
361
362         return 0;
363 }
364
365 int i82527_check_tx_stat(struct canchip_t *chip)
366 {
367         if (can_read_reg(chip,iSTAT) & iSTAT_TXOK) {
368                 can_write_reg(chip,0x0,iSTAT);
369                 return 0;
370         }
371         else {
372                 can_write_reg(chip,0x0,iSTAT);
373                 return 1;
374         }
375 }
376
377 int i82527_remote_request(struct canchip_t *chip, struct msgobj_t *obj)
378 {
379         canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
380         canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_SET|MLST_RES|NEWD_RES),iMSGCTL1);
381         
382         return 0;
383 }
384
385 int i82527_set_btregs(struct canchip_t *chip, unsigned short btr0,
386                                                         unsigned short btr1)
387 {
388         if (i82527_enable_configuration(chip))
389                 return -ENODEV;
390
391         i82527_seg_write_reg(chip, btr0, iBT0);
392         i82527_seg_write_reg(chip, btr1, iBT1);
393
394         i82527_disable_configuration(chip);
395
396         return 0;
397 }
398
399 int i82527_start_chip(struct canchip_t *chip)
400 {
401         unsigned short flags = 0;
402
403         flags = can_read_reg(chip, iCTL) & (iCTL_IE|iCTL_SIE|iCTL_EIE);
404         can_write_reg(chip, flags, iCTL);
405         
406         return 0;
407 }
408
409 int i82527_stop_chip(struct canchip_t *chip)
410 {
411         unsigned short flags = 0;
412
413         flags = can_read_reg(chip, iCTL) & (iCTL_IE|iCTL_SIE|iCTL_EIE);
414         can_write_reg(chip, flags|(iCTL_CCE|iCTL_INI), iCTL);
415
416         return 0;
417 }
418
419 int i82527_attach_to_chip(struct canchip_t *chip)
420 {
421         return 0;
422 }
423
424 int i82527_release_chip(struct canchip_t *chip)
425 {
426         i82527_stop_chip(chip);
427         can_write_reg(chip, (iCTL_CCE|iCTL_INI), iCTL);
428
429         return 0;
430 }
431
432 static inline 
433 void i82527_irq_write_handler(struct canchip_t *chip, struct msgobj_t *obj)
434 {
435         int cmd;
436
437         canobj_write_reg(chip,obj,(MVAL_RES|TXIE_RES|RXIE_RES|INTPD_RES),iMSGCTL0);
438
439         if(obj->tx_slot){
440                 /* Do local transmitted message distribution if enabled */
441                 if (processlocal){
442                         /* fill CAN message timestamp */
443                         can_filltimestamp(&obj->tx_slot->msg.timestamp);
444
445                         obj->tx_slot->msg.flags |= MSG_LOCAL;
446                         canque_filter_msg2edges(obj->qends, &obj->tx_slot->msg);
447                 }
448                 /* Free transmitted slot */
449                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
450                 obj->tx_slot=NULL;
451         }
452
453         cmd=canque_test_outslot(obj->qends, &obj->tx_qedge, &obj->tx_slot);
454         if(cmd<0)
455                 return;
456
457         if (chip->chipspecops->pre_write_config(chip, obj, &obj->tx_slot->msg)) {
458                 obj->ret = -1;
459                 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_PREP);
460                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
461                 obj->tx_slot=NULL;
462                 return;
463         }
464         if (chip->chipspecops->send_msg(chip, obj, &obj->tx_slot->msg)) {
465                 obj->ret = -1;
466                 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_SEND);
467                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
468                 obj->tx_slot=NULL;
469                 return;
470         }
471         return;
472 }
473
474 static inline
475 void i82527_irq_read_handler(struct canchip_t *chip, struct msgobj_t *obj, int objnum)
476 {
477         int i;
478         unsigned long message_id;
479         int msgcfg, msgctl1;
480         
481         msgctl1=canobj_read_reg(chip,obj,iMSGCTL1);
482         if(msgctl1 & NEWD_RES)
483                 return;
484         
485         do {
486                 if(objnum != 14) {
487                         canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|MLST_UNC|NEWD_RES),iMSGCTL1);
488                         canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
489                 }
490
491                 msgcfg = canobj_read_reg(chip,obj,iMSGCFG);
492
493                 if (msgcfg&MCFG_XTD) {
494                         message_id =canobj_read_reg(chip,obj,iMSGID3);
495                         message_id|=canobj_read_reg(chip,obj,iMSGID2)<<8;
496                         message_id|=canobj_read_reg(chip,obj,iMSGID1)<<16;
497                         message_id|=canobj_read_reg(chip,obj,iMSGID0)<<24;
498                         message_id>>=3;
499                         obj->rx_msg.flags = MSG_EXT;
500
501                 }
502                 else {
503                         message_id =canobj_read_reg(chip,obj,iMSGID1);
504                         message_id|=canobj_read_reg(chip,obj,iMSGID0)<<8;
505                         message_id>>=5;
506                         obj->rx_msg.flags = 0;
507                 }
508
509                 obj->rx_msg.length = (msgcfg >> 4) & 0xf;
510                 if(obj->rx_msg.length > CAN_MSG_LENGTH) obj->rx_msg.length = CAN_MSG_LENGTH;
511
512                 obj->rx_msg.id = message_id;
513
514                 for (i=0; i < obj->rx_msg.length; i++)
515                         obj->rx_msg.data[i] = canobj_read_reg(chip,obj,iMSGDAT0+i);
516
517                 
518                 if(objnum != 14) {
519                         /* if NEWD is set after data read, then read data are likely inconsistent */
520                         msgctl1=canobj_read_reg(chip,obj,iMSGCTL1);
521                         if(msgctl1 & NEWD_SET) {
522                                 CANMSG("i82527_irq_read_handler: object %d data overwritten\n",objnum);
523                                 continue;
524                         }
525                 }
526                 else {
527                         /* this object is special and data are queued in the shadow register */
528                         canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
529                         canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|MLST_UNC|NEWD_RES),iMSGCTL1);
530                         msgctl1=canobj_read_reg(chip,obj,iMSGCTL1);
531                 }
532                 
533
534                 /* fill CAN message timestamp */
535                 can_filltimestamp(&obj->rx_msg.timestamp);
536
537                 canque_filter_msg2edges(obj->qends, &obj->rx_msg);
538                 
539                 if (msgctl1 & NEWD_SET)
540                         continue;
541                 
542                 if (msgctl1 & MLST_SET) {
543                         canobj_write_reg(chip,obj,(RMPD_UNC|TXRQ_UNC|MLST_RES|NEWD_UNC),iMSGCTL1);
544                         CANMSG("i82527_irq_read_handler: object %d message lost\n",objnum);
545                 }
546                 
547                 return;
548
549         } while(1);
550 }
551
552 /*
553                         if (msgcfg&MCFG_XTD) {
554                                 message_id =canobj_read_reg(chip,obj,iMSGID3);
555                                 message_id|=canobj_read_reg(chip,obj,iMSGID2)<<8;
556                                 message_id|=canobj_read_reg(chip,obj,iMSGID1)<<16;
557                                 message_id|=canobj_read_reg(chip,obj,iMSGID0)<<24;
558                                 message_id>>=3;
559                         }
560                         else {
561                                 message_id =canobj_read_reg(chip,obj,iMSGID1);
562                                 message_id|=canobj_read_reg(chip,obj,iMSGID0)<<8;
563                                 message_id>>=5;
564                         }
565
566                         can_spin_lock(&hardware_p->rtr_lock);
567                         rtr_search=hardware_p->rtr_queue;
568                         while (rtr_search != NULL) {
569                                 if (rtr_search->id == message_id)
570                                         break;
571                                 rtr_search=rtr_search->next;
572                         }
573                         can_spin_unlock(&hardware_p->rtr_lock);
574                         if ((rtr_search!=NULL) && (rtr_search->id==message_id))
575                                 i82527_irq_rtr_handler(chip, obj, rtr_search, message_id);
576                         else
577                                 i82527_irq_read_handler(chip, obj, message_id); 
578 */
579
580
581 static inline 
582 void i82527_irq_update_filter(struct canchip_t *chip, struct msgobj_t *obj)
583 {
584         struct canfilt_t filt;
585
586         if(canqueue_ends_filt_conjuction(obj->qends, &filt)) {
587                 obj->rx_preconfig_id=filt.id;
588                 canobj_write_reg(chip,obj,(MVAL_RES|TXIE_RES|RXIE_RES|INTPD_RES),iMSGCTL0);
589                 if(obj->object == 15) {
590                         i82527_message15_mask(chip,filt.id,filt.mask);
591                 }
592                 if (filt.flags&MSG_EXT)
593                         can_msgobj_set_fl(obj,RX_MODE_EXT);
594                 else
595                         can_msgobj_clear_fl(obj,RX_MODE_EXT);
596
597                 i82527_pre_read_config(chip, obj);
598
599                 CANMSG("i82527_irq_update_filter: obj at 0x%08lx\n",obj->obj_base_addr);
600         }
601 }
602
603
604 void i82527_irq_sync_activities(struct canchip_t *chip, struct msgobj_t *obj)
605 {
606         while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)) {
607
608                 if(can_msgobj_test_and_clear_fl(obj,TX_REQUEST)) {
609                         if(canobj_read_reg(chip,obj,iMSGCTL1)&TXRQ_RES)
610                                 i82527_irq_write_handler(chip, obj);
611                 }
612
613                 if(!obj->tx_slot) {
614                         if(can_msgobj_test_and_clear_fl(obj,FILTCH_REQUEST)) {
615                                 i82527_irq_update_filter(chip, obj);
616                         }
617                 }
618
619                 mb();
620
621                 can_msgobj_clear_fl(obj,TX_LOCK);
622                 if(can_msgobj_test_fl(obj,TX_REQUEST))
623                         continue;
624                 if(can_msgobj_test_fl(obj,FILTCH_REQUEST) && !obj->tx_slot)
625                         continue;
626                 break;
627         }
628 }
629
630 int i82527_irq_handler(int irq, struct canchip_t *chip)
631 {
632         unsigned char msgcfg;
633
634         unsigned irq_register;
635         unsigned object;
636         struct msgobj_t *obj;
637         int loop_cnt=CHIP_MAX_IRQLOOP;
638
639         /*put_reg=device->hwspecops->write_register;*/
640         /*get_reg=device->hwspecops->read_register;*/
641
642         irq_register = i82527_seg_read_reg(chip, iIRQ);
643
644         if(!irq_register) {
645                 DEBUGMSG("i82527: spurious IRQ\n");
646                 return CANCHIP_IRQ_NONE;
647         }
648
649
650         do {
651
652                 if(!loop_cnt--) {
653                         CANMSG("i82527_irq_handler IRQ %d stuck\n",irq);
654                         CANMSG("i82527_irq_register 0x%x\n",irq_register);
655                         return CANCHIP_IRQ_STUCK;
656                 }
657                 
658                 DEBUGMSG("i82527: iIRQ 0x%02x\n",irq_register);
659                 
660                 if (irq_register == 0x01) {
661                         DEBUGMSG("Status register: 0x%x\n",can_read_reg(chip, iSTAT));
662                         continue;
663                         /*return CANCHIP_IRQ_NONE;*/
664                 }
665                 
666                 if (irq_register == 0x02)
667                         object = 14;
668                 else if(irq_register < 14)
669                         object = irq_register-3;
670                 else
671                         return CANCHIP_IRQ_NONE;
672
673                 obj=chip->msgobj[object];
674                 
675                 msgcfg = canobj_read_reg(chip,obj,iMSGCFG);
676                 if (msgcfg & MCFG_DIR) {
677                         can_msgobj_set_fl(obj,TX_REQUEST);
678                         
679                         /* calls i82527_irq_write_handler synchronized with other invocations */
680                         i82527_irq_sync_activities(chip, obj);
681                 }
682                 else { 
683
684                         i82527_irq_read_handler(chip, obj, object); 
685                 }
686                 
687         } while((irq_register=i82527_seg_read_reg(chip, iIRQ)) != 0);
688
689         return CANCHIP_IRQ_HANDLED;
690 }
691
692 void i82527_irq_rtr_handler(struct canchip_t *chip, struct msgobj_t *obj,
693                             struct rtr_id *rtr_search, unsigned long message_id)
694 {
695         short int i=0;
696
697         canobj_write_reg(chip,obj,(MVAL_RES|TXIE_RES|RXIE_RES|INTPD_RES),iMSGCTL0);
698         canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|MLST_RES|NEWD_RES),iMSGCTL1);
699         
700         can_spin_lock(&hardware_p->rtr_lock);
701
702         rtr_search->rtr_message->id=message_id;
703         rtr_search->rtr_message->length=(canobj_read_reg(chip,obj,iMSGCFG) & 0xf0)>>4;
704         for (i=0; i<rtr_search->rtr_message->length; i++)
705                 rtr_search->rtr_message->data[i]=canobj_read_reg(chip,obj,iMSGDAT0+i);
706         
707         can_spin_unlock(&hardware_p->rtr_lock);
708
709         if (waitqueue_active(&rtr_search->rtr_wq))
710                 wake_up(&rtr_search->rtr_wq);
711 }
712
713 /**
714  * i82527_wakeup_tx: - wakeups TX processing
715  * @chip: pointer to chip state structure
716  * @obj: pointer to message object structure
717  *
718  * Function is responsible for initiating message transmition.
719  * It is responsible for clearing of object TX_REQUEST flag
720  *
721  * Return Value: negative value reports error.
722  * File: src/i82527.c
723  */
724 int i82527_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj)
725 {
726         can_preempt_disable();
727         
728         can_msgobj_set_fl(obj,TX_REQUEST);
729
730         /* calls i82527_irq_write_handler synchronized with other invocations
731           from kernel and IRQ context */
732         i82527_irq_sync_activities(chip, obj);
733
734         can_preempt_enable();
735         return 0;
736 }
737
738 int i82527_filtch_rq(struct canchip_t *chip, struct msgobj_t *obj)
739 {
740         can_preempt_disable();
741         
742         can_msgobj_set_fl(obj,FILTCH_REQUEST);
743
744         /* setups filter synchronized with other invocations from kernel and IRQ context */
745         i82527_irq_sync_activities(chip, obj);
746
747         can_preempt_enable();
748         return 0;
749 }
750
751 int i82527_register(struct chipspecops_t *chipspecops)
752 {
753         chipspecops->chip_config = i82527_chip_config;
754         chipspecops->baud_rate = i82527_baud_rate;
755         chipspecops->standard_mask = i82527_standard_mask;
756         chipspecops->extended_mask = i82527_extended_mask;
757         chipspecops->message15_mask = i82527_message15_mask;
758         chipspecops->clear_objects = i82527_clear_objects;
759         chipspecops->config_irqs = i82527_config_irqs;
760         chipspecops->pre_read_config = i82527_pre_read_config;
761         chipspecops->pre_write_config = i82527_pre_write_config;
762         chipspecops->send_msg = i82527_send_msg;
763         chipspecops->check_tx_stat = i82527_check_tx_stat;
764         chipspecops->wakeup_tx = i82527_wakeup_tx;
765         chipspecops->filtch_rq = i82527_filtch_rq;
766         chipspecops->remote_request = i82527_remote_request;
767         chipspecops->enable_configuration = i82527_enable_configuration;
768         chipspecops->disable_configuration = i82527_disable_configuration;
769         chipspecops->set_btregs = i82527_set_btregs;
770         chipspecops->attach_to_chip = i82527_attach_to_chip;
771         chipspecops->release_chip = i82527_release_chip;
772         chipspecops->start_chip = i82527_start_chip;
773         chipspecops->stop_chip = i82527_stop_chip;
774         chipspecops->irq_handler = i82527_irq_handler;
775         chipspecops->irq_accept = NULL;
776         return 0;
777 }
778
779 int i82527_fill_chipspecops(struct canchip_t *chip)
780 {
781         chip->chip_type="i82527";
782         chip->max_objects=15;
783         i82527_register(chip->chipspecops);
784         return 0;
785 }