embedded/app/usbcan/lpc17xx_can.c

   1 #include "can/lpc17xx_can.h"
   2
   3 static void CAN_configPin();
   4
   5
   6 // board can-lmc1 specific functions:
   7
   8 int can_lmc1_register(struct hwspecops_t *hwspecops){
   9
  10         hwspecops->request_io = can_lmc1_request_io;
  11         hwspecops->reset = can_lmc1_reset;
  12         hwspecops->init_hw_data = can_lmc1_init_hw_data;
  13         hwspecops->init_chip_data = can_lmc1_init_chip_data;
  14         hwspecops->init_obj_data = can_lmc1_init_obj_data;
  15         hwspecops->write_register = can_lmc1_write_register;
  16         hwspecops->read_register = can_lmc1_read_register;
  17         hwspecops->program_irq = can_lmc1_program_irq;
  18
  19         return 0;
  20 }
  21
  22 int can_lmc1_init_hw_data(struct candevice_t *candev){
  23
  24         candev->res_addr=0;
  25         candev->nr_82527_chips=0;
  26         candev->nr_sja1000_chips=0;
  27         candev->nr_all_chips=1;
  28         candev->flags = 0;
  29
  30         return 0;
  31 }
  32
  33 int can_lmc1_init_chip_data(struct candevice_t *candev, int chipnr){
  34
  35         struct can_bittiming_const *btc;
  36         struct can_lmc1_chip_data *chip_data;
  37
  38         // used CAN1 peripherial -> CAN1 registers base
  39         candev->chip[chipnr]->chip_base_addr = CAN1_REGS_BASE;
  40         // clock for CAN
  41         candev->chip[chipnr]->clock = system_frequency / 4;
  42
  43         lpc17xx_fill_chipspecops(candev->chip[chipnr]);
  44
  45         candev->chip[chipnr]->chip_data=(void *)malloc(sizeof(struct can_lmc1_chip_data));
  46         if (candev->chip[chipnr]->chip_data==NULL)
  47                 return -ENOMEM;
  48
  49
  50         chip_data = (struct can_lmc1_chip_data*) candev->chip[chipnr]->chip_data;
  51
  52         btc = &chip_data->btc;
  53
  54         // set bittiming constants
  55         btc->tseg1_min = 1;
  56         btc->tseg1_max = 16;
  57         btc->tseg2_min = 1;
  58         btc->tseg2_max = 8;
  59         btc->sjw_max = 4;
  60         btc->brp_min = 1;
  61         btc->brp_max = 1024;
  62         btc->brp_inc = 1;
  63
  64         return 0;
  65 }
  66
  67 int can_lmc1_init_obj_data(struct canchip_t *chip, int objnr){
  68
  69         return 0;
  70 }
  71
  72 void can_lmc1_write_register(unsigned data, unsigned long address){
  73         (*(volatile uint32_t*)(address)) = data;
  74 }
  75
  76 unsigned can_lmc1_read_register(unsigned long address){
  77         return (*(volatile uint32_t*)(address));
  78 }
  79
  80 int can_lmc1_request_io(struct candevice_t *candev)
  81 {
  82         return 0;
  83 }
  84
  85 int can_lmc1_reset(struct candevice_t *candev)
  86 {
  87         return 0;
  88 }
  89
  90 int can_lmc1_program_irq(struct candevice_t *candev)
  91 {
  92         return 0;
  93 }
  94
  95 //---------------------------------------------------------------------------------
  96 //---------------------------------------------------------------------------------
  97
  98
  99 // lpc17xx can chip specific functions:
 100
 101 /*
 102  * lpc17xx_baud_rate: - set communication parameters.
 103  * @chip: pointer to chip state structure
 104  * @rate: baud rate in Hz
 105  * @clock: frequency of CAN clock in Hz
 106  * @sjw: synchronization jump width (0-3) prescaled clock cycles
 107  * @sampl_pt: sample point in % (0-100) sets (TSEG1+1)/(TSEG1+TSEG2+2) ratio
 108  */
 109 int lpc17xx_baud_rate(struct canchip_t *chip, int rate, int clock, int sjw,
 110                                                         int sampl_pt, int flags)
 111 {
 112         int best_error = 1000000000, error;
 113         int best_tseg=0, best_brp=0, best_rate=0, brp=0;
 114         int tseg=0, tseg1=0, tseg2=0;
 115
 116         struct can_lmc1_chip_data *chip_data = (struct can_lmc1_chip_data*) chip->chip_data;
 117
 118         struct can_bittiming_const *btc = &chip_data->btc;
 119
 120         /* tseg even = round down, odd = round up */
 121         for (tseg=(0+0+2)*2; tseg<=(btc->tseg2_max+btc->tseg1_max+2)*2+1; tseg++) {
 122                 brp = clock/((1+tseg/2)*rate)+tseg%2;
 123                 if (brp == 0 || brp > 64)
 124                         continue;
 125                 error = rate - clock/(brp*(1+tseg/2));
 126                 if (error < 0)
 127                         error = -error;
 128                 if (error <= best_error) {
 129                         best_error = error;
 130                         best_tseg = tseg/2;
 131                         best_brp = brp-1;
 132                         best_rate = clock/(brp*(1+tseg/2));
 133                 }
 134         }
 135         if (best_error && (rate/best_error < 10)) {
 136                 CANMSG("baud rate %d is not possible with %d Hz clock\n",
 137                                                                 rate, clock);
 138                 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
 139                                 best_rate, best_brp, best_tseg, tseg1, tseg2);
 140                 return -EINVAL;
 141         }
 142         tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
 143         if (tseg2 < 0)
 144                 tseg2 = 0;
 145         if (tseg2 > btc->tseg2_max)
 146                 tseg2 = btc->tseg2_max;
 147         tseg1 = best_tseg-tseg2-2;
 148         if (tseg1>btc->tseg1_max) {
 149                 tseg1 = btc->tseg1_max;
 150                 tseg2 = best_tseg-tseg1-2;
 151         }
 152
 153         DEBUGMSG("Setting %d bps.\n", best_rate);
 154         DEBUGMSG("brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
 155                                         best_brp, best_tseg, tseg1, tseg2,
 156                                         (100*(best_tseg-tseg2)/(best_tseg+1)));
 157
 158
 159         if(chip->chipspecops->set_bittiming(chip, ++best_brp, ++sjw, ++tseg1, ++tseg2) < 0)
 160                 return -EINVAL;
 161
 162         return 0;
 163 }
 164
 165
 166
 167 int lpc17xx_chip_config(struct canchip_t *chip){
 168
 169         CAN_init(chip);
 170
 171         if (!chip->baudrate)
 172                 chip->baudrate=1000000;
 173
 174         if (lpc17xx_baud_rate(chip,chip->baudrate,chip->clock,0,75,0))
 175                 return -ENODEV;
 176
 177         return 0;
 178 }
 179
 180 int lpc17xx_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
 181                                                         struct canmsg_t *msg)
 182 {
 183
 184         CAN_send(chip, msg);
 185
 186         return 0;
 187 }
 188
 189 int lpc17xx_send_msg(struct canchip_t *chip, struct msgobj_t *obj,
 190                                                         struct canmsg_t *msg)
 191 {
 192         uint32_t i=0;
 193
 194         // write transmission request
 195         can_write_reg(chip, (CAN_CMR_TR | CAN_CMR_STB1), CAN_CMR_o);
 196
 197         // check transmission complete status
 198         while (!(can_read_reg(chip, CAN_SR_o) & CAN_SR_TCS1)){
 199                 if(i++<MAX_TRANSMIT_WAIT_LOOPS)
 200                         continue;
 201
 202                 // request command to abort transmission request
 203                 can_write_reg(chip, CAN_CMR_AT, CAN_CMR_o);
 204                 break;
 205         }
 206
 207         return 0;
 208 }
 209
 210 int lpc17xx_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj)
 211 {
 212
 213         can_preempt_disable();
 214
 215         can_msgobj_set_fl(obj,TX_PENDING);
 216         can_msgobj_set_fl(obj,TX_REQUEST);
 217
 218         while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
 219                 can_msgobj_clear_fl(obj,TX_REQUEST);
 220
 221                 if (can_read_reg(chip, CAN_SR_o) & CAN_SR_TBS1){
 222                         obj->tx_retry_cnt=0;
 223                         lpc17xx_irq_write_handler(chip, obj);
 224                 }
 225
 226                 can_msgobj_clear_fl(obj,TX_LOCK);
 227                 if(!can_msgobj_test_fl(obj,TX_REQUEST)) break;
 228
 229         }
 230
 231         can_preempt_enable();
 232
 233         return 0;
 234 }
 235
 236 int lpc17xx_irq_handler(int irq, struct canchip_t *chip)
 237 {
 238
 239         uint32_t i;
 240         struct msgobj_t *obj;
 241         obj = chip->msgobj[0];
 242
 243
 244         i = can_read_reg(chip, CAN_ICR_o);
 245
 246         if(i & (CAN_ICR_TI1 | CAN_ICR_RI)){
 247
 248                 if(can_read_reg(chip, CAN_SR_o) & CAN_SR_RBS) {
 249                                 lpc17xx_read(chip,obj);
 250                                 obj->ret = 0;
 251                 }
 252
 253
 254                 if ((can_msgobj_test_fl(obj,TX_PENDING)) || (can_msgobj_test_fl(obj,TX_REQUEST))) {
 255
 256                         can_msgobj_set_fl(obj,TX_REQUEST);
 257
 258                         while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
 259
 260                                 obj->ret=0;
 261                                 can_msgobj_clear_fl(obj,TX_REQUEST);
 262
 263                                 if (can_read_reg(chip, CAN_SR_o) & CAN_SR_TBS1){
 264                                         obj->tx_retry_cnt=0;
 265                                         lpc17xx_irq_write_handler(chip, obj);
 266                                 }
 267
 268                                 can_msgobj_clear_fl(obj,TX_LOCK);
 269                                 if(!can_msgobj_test_fl(obj,TX_REQUEST)) break;
 270
 271                         }
 272                 }
 273
 274         }
 275         if(i & CAN_ICR_DOI)
 276                 can_write_reg(chip, CAN_CMR_CDO, CAN_CMR_o);    // clear data overrun
 277
 278
 279         return CANCHIP_IRQ_HANDLED;
 280
 281 }
 282
 283 void lpc17xx_irq_write_handler(struct canchip_t *chip, struct msgobj_t *obj)
 284 {
 285         int cmd;
 286
 287
 288         if(obj->tx_slot){
 289                 /* Do local transmitted message distribution if enabled */
 290                 if (processlocal){
 291                         /* fill CAN message timestamp */
 292                         can_filltimestamp(&obj->tx_slot->msg.timestamp);
 293
 294                         obj->tx_slot->msg.flags |= MSG_LOCAL;
 295                         canque_filter_msg2edges(obj->qends, &obj->tx_slot->msg);
 296                 }
 297                 /* Free transmitted slot */
 298                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 299                 obj->tx_slot=NULL;
 300         }
 301
 302         can_msgobj_clear_fl(obj,TX_PENDING);
 303         cmd=canque_test_outslot(obj->qends, &obj->tx_qedge, &obj->tx_slot);
 304         if(cmd<0)
 305                 return;
 306         can_msgobj_set_fl(obj,TX_PENDING);
 307
 308         if (chip->chipspecops->pre_write_config(chip, obj, &obj->tx_slot->msg)) {
 309                 obj->ret = -1;
 310                 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_PREP);
 311                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 312                 obj->tx_slot=NULL;
 313                 return;
 314         }
 315         if (chip->chipspecops->send_msg(chip, obj, &obj->tx_slot->msg)) {
 316                 obj->ret = -1;
 317                 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_SEND);
 318                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 319                 obj->tx_slot=NULL;
 320                 return;
 321         }
 322
 323 }
 324
 325 void lpc17xx_read(struct canchip_t *chip, struct msgobj_t *obj) {
 326
 327
 328                 CAN_recv(chip, &obj->rx_msg);
 329
 330                 // fill CAN message timestamp
 331                 can_filltimestamp(&obj->rx_msg.timestamp);
 332
 333                 canque_filter_msg2edges(obj->qends, &obj->rx_msg);
 334
 335                 // release Receive buffer
 336                 can_write_reg(chip, CAN_CMR_RRB, CAN_CMR_o);
 337
 338 }
 339
 340 int lpc17xx_set_bittiming(struct canchip_t *chip, int brp, int sjw, int tseg1, int tseg2){
 341
 342         uint8_t SAM = 0; // 0 = the bus is sampled once
 343
 344         if((--brp)<0)
 345                 return -EINVAL;
 346
 347         if((--sjw)<0)
 348                 return -EINVAL;
 349
 350         if((--tseg1)<0)
 351                 return -EINVAL;
 352
 353         if((--tseg2)<0)
 354                 return -EINVAL;
 355
 356
 357         //debug print
 358         printf("BRP: %d, SJW: %d, TSEG1: %d, TSEG2: %d \n", brp+1, sjw+1, tseg1+1, tseg2+1);
 359
 360         can_disable_irq(chip->chip_irq);
 361
 362         // enter reset mode
 363         can_write_reg(chip, 1, CAN_MOD_o);
 364
 365         // set bittiming register
 366         can_write_reg(chip, ((SAM<<23)|(tseg2<<20)|(tseg1<<16)|(sjw<<14)|(brp<<0)), CAN_BTR_o);
 367
 368         // return to normal operating
 369         can_write_reg(chip, 0, CAN_MOD_o);
 370
 371         can_enable_irq(chip->chip_irq);
 372
 373         return 0;
 374 }
 375
 376 int lpc17xx_fill_chipspecops(struct canchip_t *chip){
 377
 378         chip->max_objects=1;
 379         chip->chip_irq = CAN_IRQn;
 380
 381         lpc17xx_register(chip->chipspecops);
 382
 383         return 0;
 384 }
 385
 386 int lpc17xx_register(struct chipspecops_t *chipspecops){
 387
 388         CANMSG("initializing lpc17xx can chip operations\n");
 389
 390         chipspecops->attach_to_chip = lpc17xx_attach_to_chip;
 391         chipspecops->pre_read_config = lpc17xx_pre_read_config;
 392         chipspecops->chip_config = lpc17xx_chip_config;
 393         chipspecops->pre_write_config = lpc17xx_pre_write_config;
 394         chipspecops->send_msg = lpc17xx_send_msg;
 395         chipspecops->wakeup_tx = lpc17xx_wakeup_tx;
 396         chipspecops->irq_handler = lpc17xx_irq_handler;
 397
 398         chipspecops->set_bittiming = lpc17xx_set_bittiming;
 399
 400         return 0;
 401
 402 }
 403
 404
 405 int lpc17xx_attach_to_chip(struct canchip_t *chip){
 406
 407         return 0;
 408 }
 409
 410 int lpc17xx_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj){
 411
 412         return 1;
 413 }
 414
 415
 416
 417 //---------------------------------------------------------------------------------
 418 //---------------------------------------------------------------------------------
 419
 420
 421 static void CAN_configPin(){
 422
 423 //      CAN1 - select P0.0 as RD1. P0.1 as TD1
 424
 425         uint32_t pinsel0;
 426         uint32_t pinmode0;
 427         uint32_t pinmode_od0;
 428         uint8_t pinsel0_val = 1;
 429         uint8_t pinmode0_val = 0;
 430         uint8_t pinmode_od0_val = 0;
 431
 432
 433         pinsel0 = PINCON->PINSEL0;
 434         pinsel0 &= ~CAN1_RX_MASK;
 435         pinsel0 &= ~CAN1_TX_MASK;
 436         pinsel0 |= __val2mfld(CAN1_RX_MASK, pinsel0_val);
 437         pinsel0 |= __val2mfld(CAN1_TX_MASK, pinsel0_val);
 438         PINCON->PINSEL0 = pinsel0;
 439
 440         pinmode0 = PINCON->PINMODE0;
 441         pinmode0 &= ~CAN1_RX_MASK;
 442         pinmode0 &= ~CAN1_TX_MASK;
 443         pinmode0 |= __val2mfld(CAN1_RX_MASK, pinmode0_val);
 444         pinmode0 |= __val2mfld(CAN1_TX_MASK, pinmode0_val);
 445         PINCON->PINMODE0 = pinmode0;
 446
 447         pinmode_od0 = PINCON->PINMODE_OD0;
 448         if (pinmode_od0_val){
 449                 pinmode_od0 |= CAN1_RX_BIT;
 450                 pinmode_od0 |= CAN1_TX_BIT;
 451         }
 452         else{
 453                 pinmode_od0 &= ~CAN1_RX_BIT;
 454                 pinmode_od0 &= ~CAN1_TX_BIT;
 455         }
 456         PINCON->PINMODE_OD0 = pinmode_od0;
 457
 458
 459 }
 460
 461 void CAN_recv(struct canchip_t *chip, canmsg_t* msg){
 462
 463         volatile uint32_t data;
 464         uint32_t i;
 465
 466         // read data lenght
 467         msg->length = (can_read_reg(chip, CAN_RFS_o)>>16) & 0xF;
 468
 469         // read identifier
 470         msg->id = can_read_reg(chip, CAN_RID_o);
 471
 472         // EXT frame
 473         if(can_read_reg(chip, CAN_RFS_o) & CAN_RFS_EXT)
 474                 msg->flags |= MSG_EXT;
 475         else
 476                 msg->flags &= ~MSG_EXT;
 477
 478
 479         // RTR frame
 480         if(can_read_reg(chip, CAN_RFS_o) & CAN_RFS_RTR)
 481                 msg->flags |= MSG_RTR;
 482         else
 483                 msg->flags &= ~MSG_RTR;
 484
 485
 486         // read data
 487         data = can_read_reg(chip, CAN_RDA_o);
 488         for(i=0; i<4; i++)
 489                 msg->data[i] = (data>>(i*8)) & 0xFF;
 490
 491         data = can_read_reg(chip, CAN_RDB_o);
 492         for(i=4; i<8; i++)
 493                 msg->data[i] = (data>>((i-4)*8)) & 0xFF;
 494
 495 }
 496
 497
 498 void CAN_send(struct canchip_t *chip, canmsg_t* msg){
 499
 500         volatile uint32_t data;
 501         volatile uint32_t can_tfi1;
 502         uint32_t i=0;
 503
 504         // check status of TB1
 505         while (!(can_read_reg(chip, CAN_SR_o) & CAN_SR_TBS1)){
 506                 if(i++<MAX_TRANSMIT_WAIT_LOOPS)
 507                         continue;
 508
 509                 // request command to abort transmission request
 510                 can_write_reg(chip, CAN_CMR_AT, CAN_CMR_o);
 511                 return;
 512         }
 513
 514         can_tfi1 = can_read_reg(chip, CAN_TFI1_o);
 515
 516         can_tfi1 &= ~0x000F0000;
 517         can_tfi1 |= (msg->length)<<16;
 518
 519         // EXT frame
 520         if(msg->flags & MSG_EXT)
 521                 can_tfi1 |= CAN_TFI1_EXT;
 522         else
 523                 can_tfi1 &= ~CAN_TFI1_EXT;
 524
 525         // RTR frame
 526         if(msg->flags & MSG_RTR)
 527                 can_tfi1 |= CAN_TFI1_RTR;
 528         else
 529                 can_tfi1 &= ~CAN_TFI1_RTR;
 530
 531         can_write_reg(chip, can_tfi1, CAN_TFI1_o);
 532
 533
 534         // write CAN ID
 535         can_write_reg(chip, msg->id, CAN_TID1_o);
 536
 537
 538         // write first 4 data bytes
 539         data=0;
 540         for(i=0; i<4; i++)
 541                 data |= (msg->data[i])<<(i*8);
 542
 543         can_write_reg(chip, data, CAN_TDA1_o);
 544
 545         // write second 4 data bytes
 546         data=0;
 547         for(i=4; i<8; i++)
 548                 data |= (msg->data[i])<<((i-4)*8);
 549
 550         can_write_reg(chip, data, CAN_TDB1_o);
 551
 552 }
 553
 554 void CAN_init(struct canchip_t *chip){
 555
 556         uint32_t tmp;
 557         uint32_t pclksel0;
 558         uint32_t val;
 559         uint32_t i;
 560
 561         // configure CAN1 pins
 562         CAN_configPin();
 563
 564         // turn on power and clock for CAN1
 565         SC->PCONP |= PCCAN1;
 566
 567         // set clock divide for CAN1
 568
 569         val = 0x00; // 00       PCLK_peripheral = CCLK/4
 570         pclksel0 = SC->PCLKSEL0;
 571         pclksel0 &= ~PCLK_CAN1_MASK;
 572         pclksel0 &= ~PCLK_CAN2_MASK;
 573         pclksel0 &= ~PCLK_ACF_MASK;
 574         pclksel0 |= __val2mfld(PCLK_CAN1_MASK, val);
 575         pclksel0 |= __val2mfld(PCLK_CAN2_MASK, val);
 576         pclksel0 |= __val2mfld(PCLK_ACF_MASK, val);
 577         SC->PCLKSEL0 = pclksel0;
 578
 579         // enter reset mode
 580         can_write_reg(chip, 1, CAN_MOD_o);
 581
 582         // disable all CAN interrupts
 583         can_write_reg(chip, 0, CAN_IER_o);
 584
 585         // reset value of Global Status Register (global controller status and error counters)
 586         can_write_reg(chip, 0x3C, CAN_GSR_o);
 587
 588         // request command to release Rx, Tx buffer and clear data overrun
 589         can_write_reg(chip, (CAN_CMR_AT | CAN_CMR_RRB | CAN_CMR_CDO), CAN_CMR_o);
 590
 591         // read to clear interrupt pending in Interrupt Capture Register
 592         tmp = can_read_reg(chip, CAN_ICR_o);
 593
 594         // return to normal operating
 595         can_write_reg(chip, 0, CAN_MOD_o);
 596
 597
 598         //--------------------------
 599
 600         // Acceptance Filter Off Mode
 601         CANAF_AFMR = 0x01;
 602
 603         // clear RAM masks
 604         for (i = 0; i < 512; i++) {
 605                 CANAF_RAM->mask[i] = 0x00;
 606         }
 607
 608         CANAF_SFF_sa = 0x00;
 609         CANAF_SFF_GRP_sa = 0x00;
 610         CANAF_EFF_sa = 0x00;
 611         CANAF_EFF_GRP_sa = 0x00;
 612         CANAF_ENDofTable = 0x00;
 613
 614         // Acceptance Filter Bypass Mode - all messages accepted
 615         CANAF_AFMR = 0x02;
 616
 617         //--------------------------
 618
 619
 620         // enable interrupt after transmit
 621         // enable receive interrupt
 622         // enable data overrun interrupt
 623         can_write_reg(chip, (CAN_IER_TIE1 | CAN_IER_RIE | CAN_IER_DOIE), CAN_IER_o);
 624
 625
 626 }
 627