1 /* c_can.h - Hynix HMS30c7202 ARM generic C_CAN module handling
2 * Linux CAN-bus device driver.
3 * Written by Sebastian Stolzenberg email:stolzi@sebastian-stolzenberg.de
4 * Based on code from Arnaud Westenberg email:arnaud@wanadoo.nl
5 * and Ake Hedman, eurosource, akhe@eurosource.se
6 * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
7 * email:pisa@cmp.felk.cvut.cz
8 * This software is released under the GPL-License.
9 * Version lincan-0.3 17 Jun 2004
13 * optimized inline version, may it be, that it can be too fast for the chip
15 extern inline void c_can_write_reg_w(const struct canchip_t *pchip, u16 data, unsigned reg)
17 can_ioptr_t address = pchip->chip_base_addr + reg;
18 #ifndef CONFIG_OC_LINCAN_DYNAMICIO
20 #else /*CONFIG_OC_LINCAN_DYNAMICIO*/
21 pchip->write_register(data, address);
22 #endif /*CONFIG_OC_LINCAN_DYNAMICIO*/
25 extern inline u16 c_can_read_reg_w(const struct canchip_t *pchip, unsigned reg)
27 can_ioptr_t address = pchip->chip_base_addr + reg;
28 #ifndef CONFIG_OC_LINCAN_DYNAMICIO
29 return readw(address);
30 #else /*CONFIG_OC_LINCAN_DYNAMICIO*/
31 return pchip->read_register(address);
32 #endif /*CONFIG_OC_LINCAN_DYNAMICIO*/
35 extern can_spinlock_t c_can_spwlock; // Spin lock for write operations
36 extern can_spinlock_t c_can_sprlock; // Spin lock for read operations
37 extern can_spinlock_t c_can_if1lock; // spin lock for the if1 register
38 extern can_spinlock_t c_can_if2lock; // spin lcok for the if2 register
40 int c_can_if1_busycheck(struct canchip_t *pchip);
41 int c_can_if2_busycheck(struct canchip_t *pchip);
43 int c_can_enable_configuration(struct canchip_t *pchip);
44 int c_can_disable_configuration(struct canchip_t *pchip);
45 int c_can_chip_config(struct canchip_t *pchip);
46 int c_can_baud_rate(struct canchip_t *chip, int rate, int clock,
47 int sjw, int sampl_pt, int flags);
48 int c_can_mask(struct msgobj_t *pmsgobj,
51 int c_can_use_mask(struct msgobj_t *pmsgobj,
53 int c_can_clear_objects(struct canchip_t *pchip);
54 int c_can_config_irqs(struct canchip_t *pchip,
56 int c_can_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj);
57 int c_can_send_msg(struct canchip_t *pchip, struct msgobj_t *pmsgobj,
58 struct canmsg_t *pmsg);
59 int c_can_remote_request(struct canchip_t *pchip, struct msgobj_t *pmsgobj );
60 int c_can_set_btregs(struct canchip_t *chip,
63 int c_can_start_chip(struct canchip_t *pchip);
64 int c_can_stop_chip(struct canchip_t *pchip);
65 int c_can_check_tx_stat(struct canchip_t *pchip);
67 int c_can_register(struct chipspecops_t *chipspecops);
69 void c_can_registerdump(struct canchip_t *pchip);
71 void c_can_if1_registerdump(struct canchip_t *pchip);
73 void c_can_irq_sync_activities(struct canchip_t *chip, struct msgobj_t *obj);
75 int c_can_irq_handler(int irq, struct canchip_t *pchip);
77 int c_can_fill_chipspecops(struct canchip_t *pchip);
79 /* The CCCE register is not implemented in version 1.2 of C_CAN */
80 #undef C_CAN_WITH_CCCE
82 /* The mask of C_CAN registers offsets */
83 #define C_CAN_REGOFFS_MASK 0xFF
85 /* SSEE C_CAN Memory map */
86 /* BasicCAN offsets are multiplied by two */
87 #define CCCR 0x00 /* Control Register */
88 #define CCSR 0x02 /* Status Register */
89 #define CCEC 0x04 /* Error Counting Register */
90 #define CCBT 0x06 /* Bit Timing Register */
91 #define CCINTR 0x08 /* Interrupt Register */
92 #define CCTR 0x0A /* Test Register */
93 #define CCBRPE 0x0C /* Baud Rate Prescaler Extension Register */
95 #ifdef C_CAN_WITH_CCCE
96 #define CCCE 0x0E /* CAN Enable Register */
97 #endif /*C_CAN_WITH_CCCE*/
99 #define CCIF1CR 0x10 /* Interface 1 Command Request Register */
100 #define CCIF1CM 0x12 /* IF1 Command Mask Register */
101 #define CCIF1M1 0x14 /* IF1 Mask 1 Register */
102 #define CCIF1M2 0x16 /* IF1 Mask 2 Register */
103 #define CCIF1A1 0x18 /* IF1 Arbitration 1 Register */
104 #define CCIF1A2 0x1A /* IF1 Arbitration 2 Register */
105 #define CCIF1DMC 0x1C /* IF1 Message Control Register */
106 #define CCIF1DA1 0x1E /* IF1 Data A 1 Register */
107 #define CCIF1DA2 0x20 /* IF1 Data A 2 Register */
108 #define CCIF1DB1 0x22 /* IF1 Data B 1 Register */
109 #define CCIF1DB2 0x24 /* IF1 Data B 2 Register */
111 #define CCIF2CR 0x40 /* Interface 2 Command Request Register */
112 #define CCIF2CM 0x42 /* IF2 Command Mask Register */
113 #define CCIF2M1 0x44 /* IF2 Mask 1 Register */
114 #define CCIF2M2 0x46 /* IF2 Mask 2 Register */
115 #define CCIF2A1 0x48 /* IF2 Arbitration 1 Register */
116 #define CCIF2A2 0x4A /* IF2 Arbitration 2 Register */
117 #define CCIF2DMC 0x4C /* IF2 Message Control Register */
118 #define CCIF2DA1 0x4E /* IF2 Data A 1 Register */
119 #define CCIF2DA2 0x50 /* IF2 Data A 2 Register */
120 #define CCIF2DB1 0x52 /* IF2 Data B 1 Register */
121 #define CCIF2DB2 0x54 /* IF2 Data B 2 Register */
123 #define CCTREQ1 0x80 /* Transmission Request 1 Register */
124 #define CCTREQ2 0x82 /* Transmission Request 2 Register */
126 #define CCND1 0x90 /* New Data 1 Register */
127 #define CCND2 0x92 /* New Data 2 Register */
129 #define CCINTP1 0xA0 /* Interrupt Pending 1 Register */
130 #define CCINTP2 0xA2 /* Interrupt Pending 2 Register */
132 #define CCIMV1 0xB0 /* Message Valid 1 Register */
133 #define CCIMV2 0xB2 /* Message Valid 2 Register */
135 /* Control register */
138 CR_INIT = 1, // Internal Initialization Pending
139 CR_MIE = 1<<1, // Module Interrupt Enable
140 CR_SIE = 1<<2, // Status-change Interrupt Enable
141 CR_EIE = 1<<3, // Error Interrupt Enable
142 CR_DAR = 1<<5, // Disable Automatic Retransmission
143 CR_CCE = 1<<6, // Configuration Change Enable
144 CR_TEST = 1<<7 // Test Mode Enable
147 /* Status Register */
150 SR_TXOK = 1<<3, // Transmitted a Message Successfully
151 SR_RXOK = 1<<4, // Received a Message Successfully
152 SR_EPASS = 1<<5, // Error Passive
153 SR_EWARN = 1<<6, // Error Warning Status
154 SR_BOFF = 1<<7, // Bus Off Status
157 /* Status Register Last Error Codes */
158 enum c_can_BASIC_SRLEC
160 SRLEC_NE = 0, // Last Error Code: No Error
161 SRLEC_SE = 1, // LEC: Stuff Error
162 SRLEC_FE = 2, // LEC: Form Error
163 SRLEC_AE = 3, // LEC: Acknowledgement Error
164 SRLEC_B1 = 4, // LEC: Bit1 Error
165 SRLEC_B0 = 5, // LEC: Bit0 Error
166 SRLEC_CR = 6 // LEC: CRC Error
169 /* Error Counting Register */
172 EC_REP = 1<<15 // Receive Error Passive
175 /* Interrupt Register */
178 INT_NOINT = 0, // No Interrupt is pending
179 INT_STAT = 0x8000 // Status Interrupt
182 /* CAN Test Register */
185 TR_BASIC = 1<<2, // Basic Mode
186 TR_SLNT = 1<<3, // Silent Mode
187 TR_LOOPB = 1<<4, // Loop Back Mode
188 TR_RX = 1<<7 // Receive (CAN_RX Pin)
191 /* CAN Test Register TX Control*/
192 enum c_can_BASIC_TRTX
194 TRTX_RST = 0, // Reset value, CAN_TX is controlled by the CAN Core
195 TRTX_MON = 1, // Sample Point can be monitored at CAN_TX pin
196 TRTX_DOM = 2, // CAN_TX pin drives a dominant('0') value
197 TRTX_REC = 3 // CAN_TX pin drives a recessive('1') value
200 /* CAN Enable Register */
203 CE_EN = 1 // CAN Enable Bit
206 /* Interface X Command Request Register */
207 enum c_can_BASIC_IFXCR
209 IFXCR_BUSY = 1<<15 // Busy Flag (Write Access only when Busy='0')
212 /* Interface X Command Mask Register */
213 enum c_can_BASIC_IFXCM
215 IFXCM_DB = 1, // R/W Data Byte 4-7
216 IFXCM_DA = 1<<1, // R/W Data Byte 0-3
217 IFXCM_TRND = 1<<2, // Transmit Request (WRRD=1) or Reset New Date Bit (WRRD=0)
218 IFXCM_CLRINTPND = 1<<3, // Clear Interrupt Pending Bit when reading the Message Object
219 IFXCM_CNTRL = 1<<4, // Access Interface X Message Control Bits
220 IFXCM_ARB = 1<<5, // Access Interface X Arbitration
221 IFXCM_MASK = 1<<6, // Access Interface X Mask Bits
222 IFXCM_WRRD = 1<<7 // Read/Write (write data from Interface Registers to Message Object if ='1')
223 // (read data from Message Object to Interface Registers if ='0')
226 /* Interface X Mask 2 Register */
227 enum c_can_BASIC_IFXMSK2
229 IFXMSK2_MDIR = 1<<14, // Mask Message Direction (message direction bit(RTR) used for acceptance filt. or not)
230 IFXMSK2_MXTD = 1<<15 // Mask Extended Identifier (extended id bit(IDE) used for acceptance filt. or not)
233 /* Interface X Arbitration 2 Register */
234 enum c_can_BASIC_IFXARB2
236 IFXARB2_DIR = 1<<13, // Message Direction (transmit='1')
237 IFXARB2_XTD = 1<<14, // Use Extended Identifier
238 IFXARB2_MVAL = 1<<15 // Message Validation
241 /* Interface X Message Control Register */
242 enum c_can_BASIC_IFXMC
244 IFXMC_EOB = 1<<7, // End of Buffer (marks last Message Object of FIFO Buffer)
245 IFXMC_TXRQST = 1<<8, // Transmit Request
246 IFXMC_RMTEN = 1<<9, // Remote Enable
247 IFXMC_RXIE = 1<<10, // Receive Interrupt Enable
248 IFXMC_TXIE = 1<<11, // Transmit Interrupt Enable
249 IFXMC_UMASK = 1<<12, // Use Identifier Mask
250 IFXMC_INTPND = 1<<13, // Interrupt Pending
251 IFXMC_MSGLST = 1<<14, // Message Lost (Only valid for direction = receive)
252 IFXMC_NEWDAT = 1<<15 // New Data