2 * Linux CAN-bus device driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * Changed for PeliCan mode SJA1000 by Tomasz Motylewski (BFAD GmbH)
6 * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
7 * email:pisa@cmp.felk.cvut.cz
8 * This software is released under the GPL-License.
9 * Version lincan-0.3 17 Jun 2004
12 #include "../include/can.h"
13 #include "../include/can_sysdep.h"
14 #include "../include/main.h"
15 #include "../include/sja1000p.h"
17 #ifdef CONFIG_OC_LINCAN_DETAILED_ERRORS
19 static const char *sja1000_ecc_errc_str[]={
26 static const char *sja1000_ecc_seg_str[]={
46 "tolerate dominant bits",
54 "acknowledge delimiter",
61 #endif /*CONFIG_OC_LINCAN_DETAILED_ERRORS*/
63 static int sja1000_report_error_limit_counter;
65 static void sja1000_report_error(struct canchip_t *chip,
66 unsigned sr, unsigned ir, unsigned ecc)
68 if(sja1000_report_error_limit_counter>=100)
71 CANMSG("Error: status register: 0x%x irq_register: 0x%02x error: 0x%02x\n",
74 sja1000_report_error_limit_counter+=10;
76 if(sja1000_report_error_limit_counter>=100){
77 sja1000_report_error_limit_counter+=10;
78 CANMSG("Error: too many errors, reporting disabled\n");
82 #ifdef CONFIG_OC_LINCAN_DETAILED_ERRORS
83 CANMSG("SR: BS=%c ES=%c TS=%c RS=%c TCS=%c TBS=%c DOS=%c RBS=%c\n",
84 sr&sjaSR_BS?'1':'0',sr&sjaSR_ES?'1':'0',
85 sr&sjaSR_TS?'1':'0',sr&sjaSR_RS?'1':'0',
86 sr&sjaSR_TCS?'1':'0',sr&sjaSR_TBS?'1':'0',
87 sr&sjaSR_DOS?'1':'0',sr&sjaSR_RBS?'1':'0');
88 CANMSG("IR: BEI=%c ALI=%c EPI=%c WUI=%c DOI=%c EI=%c TI=%c RI=%c\n",
89 sr&sjaIR_BEI?'1':'0',sr&sjaIR_ALI?'1':'0',
90 sr&sjaIR_EPI?'1':'0',sr&sjaIR_WUI?'1':'0',
91 sr&sjaIR_DOI?'1':'0',sr&sjaIR_EI?'1':'0',
92 sr&sjaIR_TI?'1':'0',sr&sjaIR_RI?'1':'0');
93 if((sr&sjaIR_EI) || 1){
94 CANMSG("EI: %s %s %s\n",
95 sja1000_ecc_errc_str[(ecc&(sjaECC_ERCC1|sjaECC_ERCC0))/sjaECC_ERCC0],
96 ecc&sjaECC_DIR?"RX":"TX",
97 sja1000_ecc_seg_str[ecc&sjaECC_SEG_M]
100 #endif /*CONFIG_OC_LINCAN_DETAILED_ERRORS*/
105 * sja1000p_enable_configuration - enable chip configuration mode
106 * @chip: pointer to chip state structure
108 int sja1000p_enable_configuration(struct canchip_t *chip)
111 enum sja1000_PeliCAN_MOD flags;
113 can_disable_irq(chip->chip_irq);
115 flags=can_read_reg(chip,SJAMOD);
117 while ((!(flags & sjaMOD_RM)) && (i<=10)) {
118 can_write_reg(chip, sjaMOD_RM, SJAMOD);
119 // TODO: configurable sjaMOD_AFM (32/16 bit acceptance filter)
120 // config sjaMOD_LOM (listen only)
123 flags=can_read_reg(chip, SJAMOD);
126 CANMSG("Reset error\n");
127 can_enable_irq(chip->chip_irq);
135 * sja1000p_disable_configuration - disable chip configuration mode
136 * @chip: pointer to chip state structure
138 int sja1000p_disable_configuration(struct canchip_t *chip)
141 enum sja1000_PeliCAN_MOD flags;
143 flags=can_read_reg(chip,SJAMOD);
145 while ( (flags & sjaMOD_RM) && (i<=50) ) {
146 // could be as long as 11*128 bit times after buss-off
147 can_write_reg(chip, 0, SJAMOD);
148 // TODO: configurable sjaMOD_AFM (32/16 bit acceptance filter)
149 // config sjaMOD_LOM (listen only)
152 flags=can_read_reg(chip, SJAMOD);
155 CANMSG("Error leaving reset status\n");
159 can_enable_irq(chip->chip_irq);
165 * sja1000p_chip_config: - can chip configuration
166 * @chip: pointer to chip state structure
168 * This function configures chip and prepares it for message
169 * transmission and reception. The function resets chip,
170 * resets mask for acceptance of all messages by call to
171 * sja1000p_extended_mask() function and then
172 * computes and sets baudrate with use of function sja1000p_baud_rate().
173 * Return Value: negative value reports error.
174 * File: src/sja1000p.c
176 int sja1000p_chip_config(struct canchip_t *chip)
181 if (sja1000p_enable_configuration(chip))
184 /* Set mode, clock out, comparator */
185 can_write_reg(chip,sjaCDR_PELICAN|chip->sja_cdr_reg,SJACDR);
187 /* Ensure, that interrupts are disabled even on the chip level now */
188 can_write_reg(chip, sjaDISABLE_INTERRUPTS, SJAIER);
190 /* Set driver output configuration */
191 can_write_reg(chip,chip->sja_ocr_reg,SJAOCR);
193 /* Simple check for chip presence */
194 for (i=0, n=0x5a; i<8; i++, n+=0xf) {
195 can_write_reg(chip,n,SJAACR0+i);
197 for (i=0, n=0x5a; i<8; i++, n+=0xf) {
198 r = n^can_read_reg(chip,SJAACR0+i);
200 CANMSG("sja1000p_chip_config: chip connection broken,"
201 " readback differ 0x%02x\n", r);
207 if (sja1000p_extended_mask(chip,0x00000000, 0xffffffff))
211 chip->baudrate=1000000;
212 if (sja1000p_baud_rate(chip,chip->baudrate,chip->clock,0,75,0))
215 /* Enable hardware interrupts */
216 can_write_reg(chip, sjaENABLE_INTERRUPTS, SJAIER);
218 sja1000p_disable_configuration(chip);
224 * sja1000p_extended_mask: - setup of extended mask for message filtering
225 * @chip: pointer to chip state structure
226 * @code: can message acceptance code
227 * @mask: can message acceptance mask
229 * Return Value: negative value reports error.
230 * File: src/sja1000p.c
232 int sja1000p_extended_mask(struct canchip_t *chip, unsigned long code, unsigned long mask)
236 if (sja1000p_enable_configuration(chip))
239 // LSB to +3, MSB to +0
240 for(i=SJA_PeliCAN_AC_LEN; --i>=0;) {
241 can_write_reg(chip,code&0xff,SJAACR0+i);
242 can_write_reg(chip,mask&0xff,SJAAMR0+i);
247 DEBUGMSG("Setting acceptance code to 0x%lx\n",(unsigned long)code);
248 DEBUGMSG("Setting acceptance mask to 0x%lx\n",(unsigned long)mask);
250 sja1000p_disable_configuration(chip);
256 * sja1000p_baud_rate: - set communication parameters.
257 * @chip: pointer to chip state structure
258 * @rate: baud rate in Hz
259 * @clock: frequency of sja1000 clock in Hz (ISA osc is 14318000)
260 * @sjw: synchronization jump width (0-3) prescaled clock cycles
261 * @sampl_pt: sample point in % (0-100) sets (TSEG1+1)/(TSEG1+TSEG2+2) ratio
262 * @flags: fields %BTR1_SAM, %OCMODE, %OCPOL, %OCTP, %OCTN, %CLK_OFF, %CBP
264 * Return Value: negative value reports error.
265 * File: src/sja1000p.c
267 int sja1000p_baud_rate(struct canchip_t *chip, int rate, int clock, int sjw,
268 int sampl_pt, int flags)
270 int best_error = 1000000000, error;
271 int best_tseg=0, best_brp=0, best_rate=0, brp=0;
272 int tseg=0, tseg1=0, tseg2=0;
274 if (sja1000p_enable_configuration(chip))
279 /* tseg even = round down, odd = round up */
280 for (tseg=(0+0+2)*2; tseg<=(sjaMAX_TSEG2+sjaMAX_TSEG1+2)*2+1; tseg++) {
281 brp = clock/((1+tseg/2)*rate)+tseg%2;
282 if (brp == 0 || brp > 64)
284 error = rate - clock/(brp*(1+tseg/2));
287 if (error <= best_error) {
291 best_rate = clock/(brp*(1+tseg/2));
294 if (best_error && (rate/best_error < 10)) {
295 CANMSG("baud rate %d is not possible with %d Hz clock\n",
297 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
298 best_rate, best_brp, best_tseg, tseg1, tseg2);
301 tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
304 if (tseg2 > sjaMAX_TSEG2)
305 tseg2 = sjaMAX_TSEG2;
306 tseg1 = best_tseg-tseg2-2;
307 if (tseg1>sjaMAX_TSEG1) {
308 tseg1 = sjaMAX_TSEG1;
309 tseg2 = best_tseg-tseg1-2;
312 DEBUGMSG("Setting %d bps.\n", best_rate);
313 DEBUGMSG("brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
314 best_brp, best_tseg, tseg1, tseg2,
315 (100*(best_tseg-tseg2)/(best_tseg+1)));
318 can_write_reg(chip, sjw<<6 | best_brp, SJABTR0);
319 can_write_reg(chip, ((flags & BTR1_SAM) != 0)<<7 | (tseg2<<4)
322 sja1000p_disable_configuration(chip);
328 * sja1000p_read: - reads and distributes one or more received messages
329 * @chip: pointer to chip state structure
330 * @obj: pinter to CAN message queue information
332 * File: src/sja1000p.c
334 void sja1000p_read(struct canchip_t *chip, struct msgobj_t *obj) {
335 int i, flags, len, datastart;
337 flags = can_read_reg(chip,SJAFRM);
338 if(flags&sjaFRM_FF) {
340 (can_read_reg(chip,SJAID0)<<21) +
341 (can_read_reg(chip,SJAID1)<<13) +
342 (can_read_reg(chip,SJAID2)<<5) +
343 (can_read_reg(chip,SJAID3)>>3);
347 (can_read_reg(chip,SJAID0)<<3) +
348 (can_read_reg(chip,SJAID1)>>5);
352 ((flags & sjaFRM_RTR) ? MSG_RTR : 0) |
353 ((flags & sjaFRM_FF) ? MSG_EXT : 0);
354 len = flags & sjaFRM_DLC_M;
355 obj->rx_msg.length = len;
356 if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
357 for(i=0; i< len; i++) {
358 obj->rx_msg.data[i]=can_read_reg(chip,datastart+i);
361 /* fill CAN message timestamp */
362 can_filltimestamp(&obj->rx_msg.timestamp);
364 canque_filter_msg2edges(obj->qends, &obj->rx_msg);
366 can_write_reg(chip, sjaCMR_RRB, SJACMR);
368 } while (can_read_reg(chip, SJASR) & sjaSR_RBS);
372 * sja1000p_pre_read_config: - prepares message object for message reception
373 * @chip: pointer to chip state structure
374 * @obj: pointer to message object state structure
376 * Return Value: negative value reports error.
377 * Positive value indicates immediate reception of message.
378 * File: src/sja1000p.c
380 int sja1000p_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj)
383 status=can_read_reg(chip,SJASR);
385 if(status & sjaSR_BS) {
386 /* Try to recover from error condition */
387 DEBUGMSG("sja1000p_pre_read_config bus-off recover 0x%x\n",status);
388 sja1000p_enable_configuration(chip);
389 can_write_reg(chip, 0, SJARXERR);
390 can_write_reg(chip, 0, SJATXERR1);
391 can_read_reg(chip, SJAECC);
392 sja1000p_disable_configuration(chip);
395 if (!(status&sjaSR_RBS)) {
399 can_write_reg(chip, sjaDISABLE_INTERRUPTS, SJAIER); //disable interrupts for a moment
400 sja1000p_read(chip, obj);
401 can_write_reg(chip, sjaENABLE_INTERRUPTS, SJAIER); //enable interrupts
405 #define MAX_TRANSMIT_WAIT_LOOPS 10
407 * sja1000p_pre_write_config: - prepares message object for message transmission
408 * @chip: pointer to chip state structure
409 * @obj: pointer to message object state structure
410 * @msg: pointer to CAN message
412 * This function prepares selected message object for future initiation
413 * of message transmission by sja1000p_send_msg() function.
414 * The CAN message data and message ID are transfered from @msg slot
415 * into chip buffer in this function.
416 * Return Value: negative value reports error.
417 * File: src/sja1000p.c
419 int sja1000p_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
420 struct canmsg_t *msg)
427 /* Wait until Transmit Buffer Status is released */
428 while ( !((status=can_read_reg(chip, SJASR)) & sjaSR_TBS) &&
429 i++<MAX_TRANSMIT_WAIT_LOOPS) {
433 if(status & sjaSR_BS) {
434 /* Try to recover from error condition */
435 DEBUGMSG("sja1000p_pre_write_config bus-off recover 0x%x\n",status);
436 sja1000p_enable_configuration(chip);
437 can_write_reg(chip, 0, SJARXERR);
438 can_write_reg(chip, 0, SJATXERR1);
439 can_read_reg(chip, SJAECC);
440 sja1000p_disable_configuration(chip);
442 if (!(can_read_reg(chip, SJASR) & sjaSR_TBS)) {
443 CANMSG("Transmit timed out, cancelling\n");
444 // here we should check if there is no write/select waiting for this
445 // transmit. If so, set error ret and wake up.
446 // CHECKME: if we do not disable sjaIER_TIE (TX IRQ) here we get interrupt
448 can_write_reg(chip, sjaCMR_AT, SJACMR);
450 while ( !(can_read_reg(chip, SJASR) & sjaSR_TBS) &&
451 i++<MAX_TRANSMIT_WAIT_LOOPS) {
454 if (!(can_read_reg(chip, SJASR) & sjaSR_TBS)) {
455 CANMSG("Could not cancel, please reset\n");
460 if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
461 /* len &= sjaFRM_DLC_M; ensured by above condition already */
462 can_write_reg(chip, ((msg->flags&MSG_EXT)?sjaFRM_FF:0) |
463 ((msg->flags & MSG_RTR) ? sjaFRM_RTR : 0) | len, SJAFRM);
464 if(msg->flags&MSG_EXT) {
466 can_write_reg(chip, id & 0xff, SJAID3);
468 can_write_reg(chip, id & 0xff, SJAID2);
470 can_write_reg(chip, id & 0xff, SJAID1);
472 can_write_reg(chip, id, SJAID0);
473 for(i=0; i < len; i++) {
474 can_write_reg(chip, msg->data[i], SJADATE+i);
478 can_write_reg(chip, (id >> 8) & 0xff, SJAID0);
479 can_write_reg(chip, id & 0xff, SJAID1);
480 for(i=0; i < len; i++) {
481 can_write_reg(chip, msg->data[i], SJADATS+i);
488 * sja1000p_send_msg: - initiate message transmission
489 * @chip: pointer to chip state structure
490 * @obj: pointer to message object state structure
491 * @msg: pointer to CAN message
493 * This function is called after sja1000p_pre_write_config() function,
494 * which prepares data in chip buffer.
495 * Return Value: negative value reports error.
496 * File: src/sja1000p.c
498 int sja1000p_send_msg(struct canchip_t *chip, struct msgobj_t *obj,
499 struct canmsg_t *msg)
501 can_write_reg(chip, sjaCMR_TR, SJACMR);
507 * sja1000p_check_tx_stat: - checks state of transmission engine
508 * @chip: pointer to chip state structure
510 * Return Value: negative value reports error.
511 * Positive return value indicates transmission under way status.
512 * Zero value indicates finishing of all issued transmission requests.
513 * File: src/sja1000p.c
515 int sja1000p_check_tx_stat(struct canchip_t *chip)
517 if (can_read_reg(chip,SJASR) & sjaSR_TCS)
524 * sja1000p_set_btregs: - configures bitrate registers
525 * @chip: pointer to chip state structure
526 * @btr0: bitrate register 0
527 * @btr1: bitrate register 1
529 * Return Value: negative value reports error.
530 * File: src/sja1000p.c
532 int sja1000p_set_btregs(struct canchip_t *chip, unsigned short btr0,
535 if (sja1000p_enable_configuration(chip))
538 can_write_reg(chip, btr0, SJABTR0);
539 can_write_reg(chip, btr1, SJABTR1);
541 sja1000p_disable_configuration(chip);
547 * sja1000p_start_chip: - starts chip message processing
548 * @chip: pointer to chip state structure
550 * Return Value: negative value reports error.
551 * File: src/sja1000p.c
553 int sja1000p_start_chip(struct canchip_t *chip)
555 enum sja1000_PeliCAN_MOD flags;
557 flags = can_read_reg(chip, SJAMOD) & (sjaMOD_LOM|sjaMOD_STM|sjaMOD_AFM|sjaMOD_SM);
558 can_write_reg(chip, flags, SJAMOD);
560 sja1000_report_error_limit_counter=0;
566 * sja1000p_stop_chip: - stops chip message processing
567 * @chip: pointer to chip state structure
569 * Return Value: negative value reports error.
570 * File: src/sja1000p.c
572 int sja1000p_stop_chip(struct canchip_t *chip)
574 enum sja1000_PeliCAN_MOD flags;
576 flags = can_read_reg(chip, SJAMOD) & (sjaMOD_LOM|sjaMOD_STM|sjaMOD_AFM|sjaMOD_SM);
577 can_write_reg(chip, flags|sjaMOD_RM, SJAMOD);
583 * sja1000p_attach_to_chip: - attaches to the chip, setups registers and state
584 * @chip: pointer to chip state structure
586 * Return Value: negative value reports error.
587 * File: src/sja1000p.c
589 int sja1000p_attach_to_chip(struct canchip_t *chip)
595 * sja1000p_release_chip: - called before chip structure removal if %CHIP_ATTACHED is set
596 * @chip: pointer to chip state structure
598 * Return Value: negative value reports error.
599 * File: src/sja1000p.c
601 int sja1000p_release_chip(struct canchip_t *chip)
603 sja1000p_stop_chip(chip);
604 can_write_reg(chip, sjaDISABLE_INTERRUPTS, SJAIER);
610 * sja1000p_remote_request: - configures message object and asks for RTR message
611 * @chip: pointer to chip state structure
612 * @obj: pointer to message object structure
614 * Return Value: negative value reports error.
615 * File: src/sja1000p.c
617 int sja1000p_remote_request(struct canchip_t *chip, struct msgobj_t *obj)
619 CANMSG("sja1000p_remote_request not implemented\n");
624 * sja1000p_standard_mask: - setup of mask for message filtering
625 * @chip: pointer to chip state structure
626 * @code: can message acceptance code
627 * @mask: can message acceptance mask
629 * Return Value: negative value reports error.
630 * File: src/sja1000p.c
632 int sja1000p_standard_mask(struct canchip_t *chip, unsigned short code,
635 CANMSG("sja1000p_standard_mask not implemented\n");
640 * sja1000p_clear_objects: - clears state of all message object residing in chip
641 * @chip: pointer to chip state structure
643 * Return Value: negative value reports error.
644 * File: src/sja1000p.c
646 int sja1000p_clear_objects(struct canchip_t *chip)
648 CANMSG("sja1000p_clear_objects not implemented\n");
653 * sja1000p_config_irqs: - tunes chip hardware interrupt delivery
654 * @chip: pointer to chip state structure
655 * @irqs: requested chip IRQ configuration
657 * Return Value: negative value reports error.
658 * File: src/sja1000p.c
660 int sja1000p_config_irqs(struct canchip_t *chip, short irqs)
662 CANMSG("sja1000p_config_irqs not implemented\n");
667 * sja1000p_irq_write_handler: - part of ISR code responsible for transmit events
668 * @chip: pointer to chip state structure
669 * @obj: pointer to attached queue description
671 * The main purpose of this function is to read message from attached queues
672 * and transfer message contents into CAN controller chip.
673 * This subroutine is called by
674 * sja1000p_irq_write_handler() for transmit events.
675 * File: src/sja1000p.c
677 void sja1000p_irq_write_handler(struct canchip_t *chip, struct msgobj_t *obj)
682 /* Do local transmitted message distribution if enabled */
684 /* fill CAN message timestamp */
685 can_filltimestamp(&obj->tx_slot->msg.timestamp);
687 obj->tx_slot->msg.flags |= MSG_LOCAL;
688 canque_filter_msg2edges(obj->qends, &obj->tx_slot->msg);
690 /* Free transmitted slot */
691 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
695 can_msgobj_clear_fl(obj,TX_PENDING);
696 cmd=canque_test_outslot(obj->qends, &obj->tx_qedge, &obj->tx_slot);
699 can_msgobj_set_fl(obj,TX_PENDING);
701 if (chip->chipspecops->pre_write_config(chip, obj, &obj->tx_slot->msg)) {
703 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_PREP);
704 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
708 if (chip->chipspecops->send_msg(chip, obj, &obj->tx_slot->msg)) {
710 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_SEND);
711 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
721 * sja1000p_irq_handler: - interrupt service routine
722 * @irq: interrupt vector number, this value is system specific
723 * @chip: pointer to chip state structure
725 * Interrupt handler is activated when state of CAN controller chip changes,
726 * there is message to be read or there is more space for new messages or
727 * error occurs. The receive events results in reading of the message from
728 * CAN controller chip and distribution of message through attached
730 * File: src/sja1000p.c
732 int sja1000p_irq_handler(int irq, struct canchip_t *chip)
734 int irq_register, status, error_code;
735 struct msgobj_t *obj=chip->msgobj[0];
736 int loop_cnt=CHIP_MAX_IRQLOOP;
738 irq_register=can_read_reg(chip,SJAIR);
739 // DEBUGMSG("sja1000_irq_handler: SJAIR:%02x\n",irq_register);
740 // DEBUGMSG("sja1000_irq_handler: SJASR:%02x\n",
741 // can_read_reg(chip,SJASR));
743 if ((irq_register & (sjaIR_BEI|sjaIR_EPI|sjaIR_DOI|sjaIR_EI|sjaIR_TI|sjaIR_RI)) == 0)
744 return CANCHIP_IRQ_NONE;
746 if(!(chip->flags&CHIP_CONFIGURED)) {
747 CANMSG("sja1000p_irq_handler: called for non-configured device, irq_register 0x%02x\n", irq_register);
748 return CANCHIP_IRQ_NONE;
751 status=can_read_reg(chip,SJASR);
756 CANMSG("sja1000p_irq_handler IRQ %d stuck\n",irq);
757 return CANCHIP_IRQ_STUCK;
760 /* (irq_register & sjaIR_RI) */
761 /* old variant using SJAIR, collides with intended use with irq_accept */
762 if (status & sjaSR_RBS) {
763 DEBUGMSG("sja1000_irq_handler: RI or RBS\n");
764 sja1000p_read(chip,obj);
768 /* (irq_register & sjaIR_TI) */
769 /* old variant using SJAIR, collides with intended use with irq_accept */
770 if (((status & sjaSR_TBS) && can_msgobj_test_fl(obj,TX_PENDING))||
771 (can_msgobj_test_fl(obj,TX_REQUEST))) {
772 DEBUGMSG("sja1000_irq_handler: TI or TX_PENDING and TBS\n");
774 can_msgobj_set_fl(obj,TX_REQUEST);
775 while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
776 can_msgobj_clear_fl(obj,TX_REQUEST);
778 if (can_read_reg(chip, SJASR) & sjaSR_TBS)
779 sja1000p_irq_write_handler(chip, obj);
781 can_msgobj_clear_fl(obj,TX_LOCK);
782 if(!can_msgobj_test_fl(obj,TX_REQUEST)) break;
783 DEBUGMSG("TX looping in sja1000_irq_handler\n");
786 if ((irq_register & (sjaIR_EI|sjaIR_BEI|sjaIR_EPI|sjaIR_DOI)) != 0) {
787 // Some error happened
788 error_code=can_read_reg(chip,SJAECC);
789 sja1000_report_error(chip, status, irq_register, error_code);
790 // FIXME: chip should be brought to usable state. Transmission cancelled if in progress.
791 // Reset flag set to 0 if chip is already off the bus. Full state report
794 if(error_code == 0xd9) {
796 /* no such device or address - no ACK received */
798 if(obj->tx_retry_cnt++>MAX_RETR) {
799 can_write_reg(chip, sjaCMR_AT, SJACMR); // cancel any transmition
800 obj->tx_retry_cnt = 0;
802 if(status&sjaSR_BS) {
803 CANMSG("bus-off, resetting sja1000p\n");
804 can_write_reg(chip, 0, SJAMOD);
808 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_BUS);
809 /*canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
814 if(sja1000_report_error_limit_counter)
815 sja1000_report_error_limit_counter--;
819 irq_register=can_read_reg(chip,SJAIR);
821 status=can_read_reg(chip,SJASR);
823 if(((status & sjaSR_TBS) && can_msgobj_test_fl(obj,TX_PENDING)) ||
824 (irq_register & sjaIR_TI))
825 can_msgobj_set_fl(obj,TX_REQUEST);
827 } while((irq_register & (sjaIR_BEI|sjaIR_EPI|sjaIR_DOI|sjaIR_EI|sjaIR_RI)) ||
828 (can_msgobj_test_fl(obj,TX_REQUEST) && !can_msgobj_test_fl(obj,TX_LOCK)) ||
829 (status & sjaSR_RBS));
831 return CANCHIP_IRQ_HANDLED;
835 * sja1000p_wakeup_tx: - wakeups TX processing
836 * @chip: pointer to chip state structure
837 * @obj: pointer to message object structure
839 * Function is responsible for initiating message transmition.
840 * It is responsible for clearing of object TX_REQUEST flag
842 * Return Value: negative value reports error.
843 * File: src/sja1000p.c
845 int sja1000p_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj)
848 can_preempt_disable();
850 can_msgobj_set_fl(obj,TX_PENDING);
851 can_msgobj_set_fl(obj,TX_REQUEST);
852 while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
853 can_msgobj_clear_fl(obj,TX_REQUEST);
855 if (can_read_reg(chip, SJASR) & sjaSR_TBS){
857 sja1000p_irq_write_handler(chip, obj);
860 can_msgobj_clear_fl(obj,TX_LOCK);
861 if(!can_msgobj_test_fl(obj,TX_REQUEST)) break;
862 DEBUGMSG("TX looping in sja1000p_wakeup_tx\n");
865 can_preempt_enable();
869 int sja1000p_register(struct chipspecops_t *chipspecops)
871 CANMSG("initializing sja1000p chip operations\n");
872 chipspecops->chip_config=sja1000p_chip_config;
873 chipspecops->baud_rate=sja1000p_baud_rate;
874 chipspecops->standard_mask=sja1000p_standard_mask;
875 chipspecops->extended_mask=sja1000p_extended_mask;
876 chipspecops->message15_mask=sja1000p_extended_mask;
877 chipspecops->clear_objects=sja1000p_clear_objects;
878 chipspecops->config_irqs=sja1000p_config_irqs;
879 chipspecops->pre_read_config=sja1000p_pre_read_config;
880 chipspecops->pre_write_config=sja1000p_pre_write_config;
881 chipspecops->send_msg=sja1000p_send_msg;
882 chipspecops->check_tx_stat=sja1000p_check_tx_stat;
883 chipspecops->wakeup_tx=sja1000p_wakeup_tx;
884 chipspecops->remote_request=sja1000p_remote_request;
885 chipspecops->enable_configuration=sja1000p_enable_configuration;
886 chipspecops->disable_configuration=sja1000p_disable_configuration;
887 chipspecops->attach_to_chip=sja1000p_attach_to_chip;
888 chipspecops->release_chip=sja1000p_release_chip;
889 chipspecops->set_btregs=sja1000p_set_btregs;
890 chipspecops->start_chip=sja1000p_start_chip;
891 chipspecops->stop_chip=sja1000p_stop_chip;
892 chipspecops->irq_handler=sja1000p_irq_handler;
893 chipspecops->irq_accept=NULL;
898 * sja1000p_fill_chipspecops - fills chip specific operations
899 * @chip: pointer to chip representation structure
901 * The function fills chip specific operations for sja1000 (PeliCAN) chip.
903 * Return Value: returns negative number in the case of fail
905 int sja1000p_fill_chipspecops(struct canchip_t *chip)
907 chip->chip_type="sja1000p";
909 sja1000p_register(chip->chipspecops);