2 * Header file for the Linux CAN-bus driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
5 * email:pisa@cmp.felk.cvut.cz
6 * This software is released under the GPL-License.
7 * Version lincan-0.2 9 Jul 2003
10 int i82527_enable_configuration(struct chip_t *chip);
11 int i82527_disable_configuration(struct chip_t *chip);
12 int i82527_chip_config(struct chip_t *chip);
13 int i82527_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,
14 int sampl_pt, int flags);
15 int i82527_standard_mask(struct chip_t *chip, unsigned short code,
17 int i82527_extended_mask(struct chip_t *chip, unsigned long code,
19 int i82527_message15_mask(struct chip_t *chip, unsigned long code,
21 int i82527_clear_objects(struct chip_t *chip);
22 int i82527_config_irqs(struct chip_t *chip, short irqs);
23 int i82527_pre_read_config(struct chip_t *chip, struct msgobj_t *obj);
24 int i82527_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
25 struct canmsg_t *msg);
26 int i82527_send_msg(struct chip_t *chip, struct msgobj_t *obj,
27 struct canmsg_t *msg);
28 int i82527_remote_request(struct chip_t *chip, struct msgobj_t *obj);
29 int i82527_set_btregs(struct chip_t *chip, unsigned short btr0,
31 int i82527_start_chip(struct chip_t *chip);
32 int i82527_stop_chip(struct chip_t *chip);
33 int i82527_check_tx_stat(struct chip_t *chip);
34 can_irqreturn_t i82527_irq_handler(int irq, void *dev_id, struct pt_regs *regs);
36 #define MSG_OFFSET(object) ((object)*0x10)
38 #define iCTL 0x00 // Control Register
39 #define iSTAT 0x01 // Status Register
40 #define iCPU 0x02 // CPU Interface Register
41 #define iHSR 0x04 // High Speed Read
42 #define iSGM0 0x06 // Standard Global Mask byte 0
44 #define iEGM0 0x08 // Extended Global Mask byte 0
48 #define i15M0 0x0c // Message 15 Mask byte 0
52 #define iCLK 0x1f // Clock Out Register
53 #define iBUS 0x2f // Bus Configuration Register
54 #define iBT0 0x3f // Bit Timing Register byte 0
56 #define iIRQ 0x5f // Interrupt Register
57 #define iP1C 0x9f // Port 1 Register
58 #define iP2C 0xaf // Port 2 Register
59 #define iP1I 0xbf // Port 1 Data In Register
60 #define iP2I 0xcf // Port 2 Data In Register
61 #define iP1O 0xdf // Port 1 Data Out Register
62 #define iP2O 0xef // Port 2 Data Out Register
63 #define iSRA 0xff // Serial Reset Address
65 #define iMSGCTL0 0x00 /* First Control register */
66 #define iMSGCTL1 0x01 /* Second Control register */
67 #define iMSGID0 0x02 /* First Byte of Message ID */
71 #define iMSGCFG 0x06 /* Message Configuration */
72 #define iMSGDAT0 0x07 /* First Data Byte */
81 /* Control Register (0x00) */
83 iCTL_INI = 1, // Initialization
84 iCTL_IE = 1<<1, // Interrupt Enable
85 iCTL_SIE = 1<<2, // Status Interrupt Enable
86 iCTL_EIE = 1<<3, // Error Interrupt Enable
87 iCTL_CCE = 1<<6 // Change Configuration Enable
90 /* Status Register (0x01) */
92 iSTAT_TXOK = 1<<3, // Transmit Message Successfully
93 iSTAT_RXOK = 1<<4, // Receive Message Successfully
94 iSTAT_WAKE = 1<<5, // Wake Up Status
95 iSTAT_WARN = 1<<6, // Warning Status
96 iSTAT_BOFF = 1<<7 // Bus Off Status
99 /* CPU Interface Register (0x02) */
101 iCPU_CEN = 1, // Clock Out Enable
102 iCPU_MUX = 1<<2, // Multiplex
103 iCPU_SLP = 1<<3, // Sleep
104 iCPU_PWD = 1<<4, // Power Down Mode
105 iCPU_DMC = 1<<5, // Divide Memory Clock
106 iCPU_DSC = 1<<6, // Divide System Clock
107 iCPU_RST = 1<<7 // Hardware Reset Status
110 /* Clock Out Register (0x1f) */
112 iCLK_CD0 = 1, // Clock Divider bit 0
116 iCLK_SL0 = 1<<4, // Slew Rate bit 0
120 /* Bus Configuration Register (0x2f) */
122 iBUS_DR0 = 1, // Disconnect RX0 Input
123 iBUS_DR1 = 1<<1, // Disconnect RX1 Input
124 iBUS_DT1 = 1<<3, // Disconnect TX1 Output
125 iBUS_POL = 1<<5, // Polarity
126 iBUS_CBY = 1<<6 // Comparator Bypass
129 #define RESET 1 // Bit Pair Reset Status
130 #define SET 2 // Bit Pair Set Status
131 #define UNCHANGED 3 // Bit Pair Unchanged
133 /* Message Control Register 0 (Base Address + 0x0) */
134 enum i82527_iMSGCTL0 {
135 INTPD_SET = SET, // Interrupt pending
136 INTPD_RES = RESET, // No Interrupt pending
137 INTPD_UNC = UNCHANGED,
138 RXIE_SET = SET<<2, // Receive Interrupt Enable
139 RXIE_RES = RESET<<2, // Receive Interrupt Disable
140 RXIE_UNC = UNCHANGED<<2,
141 TXIE_SET = SET<<4, // Transmit Interrupt Enable
142 TXIE_RES = RESET<<4, // Transmit Interrupt Disable
143 TXIE_UNC = UNCHANGED<<4,
144 MVAL_SET = SET<<6, // Message Valid
145 MVAL_RES = RESET<<6, // Message Invalid
146 MVAL_UNC = UNCHANGED<<6
149 /* Message Control Register 1 (Base Address + 0x01) */
150 enum i82527_iMSGCTL1 {
151 NEWD_SET = SET, // New Data
152 NEWD_RES = RESET, // No New Data
153 NEWD_UNC = UNCHANGED,
154 MLST_SET = SET<<2, // Message Lost
155 MLST_RES = RESET<<2, // No Message Lost
156 MLST_UNC = UNCHANGED<<2,
157 CPUU_SET = SET<<2, // CPU Updating
158 CPUU_RES = RESET<<2, // No CPU Updating
159 CPUU_UNC = UNCHANGED<<2,
160 TXRQ_SET = SET<<4, // Transmission Request
161 TXRQ_RES = RESET<<4, // No Transmission Request
162 TXRQ_UNC = UNCHANGED<<4,
163 RMPD_SET = SET<<6, // Remote Request Pending
164 RMPD_RES = RESET<<6, // No Remote Request Pending
165 RMPD_UNC = UNCHANGED<<6
168 /* Message Configuration Register (Base Address + 0x06) */
169 enum i82527_iMSGCFG {
170 MCFG_XTD = 1<<2, // Extended Identifier
171 MCFG_DIR = 1<<3 // Direction is Transmit
174 void i82527_seg_write_reg(const struct chip_t *chip, unsigned char data, unsigned address);
175 unsigned i82527_seg_read_reg(const struct chip_t *chip, unsigned address);