2 * Linux CAN-bus device driver.
3 * nsi_canpci.c - support for NSI CAN PCI card
4 * The card support added by Eric Pennamen <pennamen@gmail.com>
5 * Based on code from Arnaud Westenberg email:arnaud@wanadoo.nl
6 * Ake Hedman, eurosource, akhe@eurosource.se ,
7 * and Pavel Pisa - OCERA team member email:pisa@cmp.felk.cvut.cz
8 * This software is released under the GPL-License.
9 * Version lincan-0.3 17 Jun 2004
12 #include "../include/can.h"
13 #include "../include/can_sysdep.h"
14 #include "../include/main.h"
15 #include "../include/nsi_canpci.h"
16 #include "../include/i82527.h"
22 #define __NO_VERSION__
23 #include <linux/module.h>
25 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10))
26 #define ioread32 readl
27 #define iowrite32 writel
29 #define iowrite8 writeb
37 #define INT_CONF 0x00000040 /* valeur de config du registre INTCSR du PLX */
38 #define NSI_VENDOR_ID 0x1637
39 #define NSI_CANPCI_DEVICE_ID 0x0001
41 enum PORT2 { P2_0=1, P2_1=1<<1, P2_2=1<<2, P2_3=1<<3, P2_4=1<<4, P2_5=1<<5, P2_6=1<<6, P2_7=1<<7 };
43 /* Definition de tous les registres du PLX */
44 #define PLX_CNTRL 0x50 /* Regitre de control */
45 #define PLX_INTCSR 0x4C /* Registe pour les interruptions */
47 /* Horloge en Hz du chip i82527 respecter le tableau suivant: */
48 /* =========================================
49 * | XTAL | SCLK (DSC bit) | MCLK (DMC bit) |
50 * |======|================|================|
51 * | 4MHz | 4MHz (0) | 4MHz (0) | NE PAS OUBLIER DE POSITIONNER LES BITS DSC et DMC EN FONTION
52 * | 8MHz | 8MHz (0) | 8MHz (0) |
53 * |10MHz | 10MHz (0) | 5MHz (1) |
54 * |12MHz | 6MHZ (1) | 6MHZ (0) |
55 * |16MHz | 8MHz (1) | 8MHz (0) |
56 * ========================================== */
57 #define iCLOCK 16000000
59 static CAN_DEFINE_SPINLOCK(nsicanpci_port_lock);
61 /* Il faut reserver 4 zones:
62 * BAR0: 128 octets memoire (32bits) pour les registres du PLX9052
63 * BAR1: 128 octets I/O pour les registres du PLX9052
64 * BAR2: 256 octets memoire(8bits) pour les registres du PLX9052
65 * BAR3: 256 octets memoire(8bits) pour les registres du PLX9052
67 /* Variables globales contenant les @ des IO-Memory apres remap */
68 #define NB_VALID_BAR 4
69 void* addr_BAR_remap[NB_VALID_BAR]={0,0,0,0};
71 void nsi_canpci_connect_irq(struct candevice_t *candev)
73 /* Preparation du registre pour configurer les INT locales 1 et 2 du PLX, INT actif à l'etat Haut */
74 // iowrite32(INT_CONF,(void*)(candev->dev_base_addr+PLX_INTCSR));
76 // DEBUGMSG("Interruptions du PLX configurees !!\n");
79 void nsi_canpci_disconnect_irq(struct candevice_t *candev)
81 // Il faut aussi desactiver les interruption du PLX, sous peine de freeze au prochain init_module
82 // tout en laissant le bit isa mis a 1
83 iowrite32(0x0,(void*)(candev->dev_base_addr+PLX_INTCSR));
85 DEBUGMSG("disable interruption du PLX\n");
88 int nsi_canpci_config_irqs(struct canchip_t *chip, short irqs)
91 unsigned long it_mask,it_reg;
92 struct candevice_t *candev;
94 DEBUGMSG("NSI Interrupt configuration\n");
95 can_write_reg(chip,irqs,iCTL);
97 {//At least one interrupt source requested
100 DEBUGMSG("starting interrupt on chip 0\n");
105 DEBUGMSG("starting interrupt on chip 1\n");
108 candev=(struct candevice_t *)chip->chip_data;
109 it_reg = ioread32( (void*)(candev->dev_base_addr+PLX_INTCSR));
111 it_reg|=it_mask|0x40;
112 iowrite32(it_reg,(void*)(candev->dev_base_addr+PLX_INTCSR));
116 {//No more interrupt source
117 if(chip->chip_idx==0)
119 DEBUGMSG("stoping interrupt on chip 0\n");
124 DEBUGMSG("stoping interrupt on chip 1\n");
127 candev=(struct candevice_t *)chip->chip_data;
128 it_reg = ioread32( (void*)(candev->dev_base_addr+PLX_INTCSR));
131 iowrite32(it_reg,(void*)(candev->dev_base_addr+PLX_INTCSR));
137 int nsi_canpci_i82527_chip_config(struct canchip_t *chip)
140 can_write_reg(chip,chip->int_cpu_reg,iCPU); // Configure cpu interface
141 can_write_reg(chip,(iCTL_CCE|iCTL_INI),iCTL); // Enable configuration
142 i82527_seg_write_reg(chip,chip->int_clk_reg,iCLK); // Set clock out slew rates
143 i82527_seg_write_reg(chip,chip->int_bus_reg,iBUS); /* Bus configuration */
145 can_write_reg(chip,P2_2|P2_1,iP2C); // Configure P2_2,P2_1 en sortie
146 can_write_reg(chip,P2_2|P2_1,iP2O); // Positionne P2_2 a 1
148 can_write_reg(chip,0x00,iSTAT); /* Clear error status register */
150 /* Check if we can at least read back some arbitrary data from the
151 * card. If we can not, the card is not properly configured!
153 canobj_write_reg(chip,chip->msgobj[1],0x25,iMSGDAT1);
154 canobj_write_reg(chip,chip->msgobj[2],0x52,iMSGDAT3);
155 canobj_write_reg(chip,chip->msgobj[10],0xc3,iMSGDAT6);
156 if ( (canobj_read_reg(chip,chip->msgobj[1],iMSGDAT1) != 0x25) ||
157 (canobj_read_reg(chip,chip->msgobj[2],iMSGDAT3) != 0x52) ||
158 (canobj_read_reg(chip,chip->msgobj[10],iMSGDAT6) != 0xc3) ) {
159 CANMSG("Could not read back from the hardware.\n");
160 CANMSG("This probably means that your hardware is not correctly configured!\n");
164 DEBUGMSG("Could read back, hardware is probably configured correctly\n");
166 if (chip->baudrate == 0)
167 chip->baudrate=1600000;
169 if (i82527_baud_rate(chip,chip->baudrate,chip->clock,0,75,0)) {
170 CANMSG("Error configuring baud rate\n");
173 if (i82527_standard_mask(chip,0x0000,stdmask)) {
174 CANMSG("Error configuring standard mask\n");
177 if (i82527_extended_mask(chip,0x00000000,extmask)) {
178 CANMSG("Error configuring extended mask\n");
181 if (i82527_message15_mask(chip,0x00000000,mo15mask)) {
182 CANMSG("Error configuring message 15 mask\n");
185 if (i82527_clear_objects(chip)) {
186 CANMSG("Error clearing message objects\n");
190 if (nsi_canpci_config_irqs(chip,iCTL_IE|iCTL_EIE)) { /* has been 0x0a */
191 CANMSG("Error configuring interrupts\n");
198 int nsi_canpci_start_chip(struct canchip_t *chip)
200 unsigned long it_mask,it_reg;
201 struct candevice_t *candev;
203 if(chip->chip_idx==0)
205 DEBUGMSG("starting chip 0\n");
210 DEBUGMSG("starting chip 1\n");
213 candev=(struct candevice_t *)chip->chip_data;
214 it_reg = ioread32( (void*)(candev->dev_base_addr+PLX_INTCSR));
216 it_reg|=it_mask|0x40;
217 iowrite32(it_reg,(void*)(candev->dev_base_addr+PLX_INTCSR));
219 i82527_start_chip(chip);
223 int nsi_canpci_stop_chip(struct canchip_t *chip)
225 unsigned long it_mask,it_reg;
226 struct candevice_t *candev;
228 if(chip->chip_idx==0)
230 DEBUGMSG("stoping chip 0\n");
235 DEBUGMSG("stoping chip 1\n");
238 candev=(struct candevice_t *)chip->chip_data;
239 it_reg = ioread32( (void*)(candev->dev_base_addr+PLX_INTCSR));
242 iowrite32(it_reg,(void*)(candev->dev_base_addr+PLX_INTCSR));
244 i82527_stop_chip(chip);
248 int nsi_canpci_irq_handler(int irq, struct canchip_t *chip)
251 unsigned long it_reg;
252 struct candevice_t *candev;
253 candev=(struct candevice_t *)chip->chip_data;
254 retcode = CANCHIP_IRQ_NONE;
255 it_reg = ioread32( (void*)(candev->dev_base_addr+PLX_INTCSR));
257 if(chip->chip_idx==0)
259 if((it_reg &0x4)!=0) //interrupt active
261 if(i82527_irq_handler(irq,chip)==CANCHIP_IRQ_NONE)
262 {//soucis avec les IT
264 CANMSG("IT du canal0 annulee pour cause de dysonctionnement\n");
268 retcode=CANCHIP_IRQ_HANDLED;
275 if((it_reg &0x20)!=0) //interrupt active
277 if(i82527_irq_handler(irq,chip)==CANCHIP_IRQ_NONE)
278 {//soucis avec les IT
280 CANMSG("IT du canal1 annulee pour cause de dysonctionnement\n");
283 retcode=CANCHIP_IRQ_HANDLED;
290 /* The function template_request_io is used to reserve the io-memory. If your
291 * hardware uses a dedicated memory range as hardware control registers you
292 * will have to add the code to reserve this memory as well.
293 * The reserved memory starts at candev->io_addr, wich is the module parameter io.
295 int nsi_canpci_request_io(struct candevice_t *candev)
298 if(addr_BAR_remap[0]==NULL)
303 /* The function template_release_io is used to free the previously reserved
304 * io-memory. In case you reserved more memory, don't forget to free it here.
306 int nsi_canpci_release_io(struct candevice_t *candev)
308 unsigned long reg_reset;
309 struct pci_dev *pcidev = candev->sysdevptr.pcidev;
310 DEBUGMSG("Liberation des io de la carte \n");
312 nsi_canpci_disconnect_irq(candev);
313 // Recherche du registre de controle du PLX parmi les IO-port du PLX */
314 reg_reset = ioread32( (void*)(candev->dev_base_addr+PLX_CNTRL));
315 reg_reset&=(~(0x40000000));
317 iowrite32( (reg_reset | 0x40000000 ),(void*)(candev->dev_base_addr+PLX_CNTRL)); /* Mise à '1' du bit reset */
319 udelay(2500); /* Reset supérieur a 1ms car necessaire aux i82527 */
320 iowrite32( (reg_reset ),(void*)(candev->dev_base_addr+PLX_CNTRL)); /* Mise à '0' du bit reset */
322 udelay(2500); /* Reset supérieur a 1ms car necessaire aux i82527 */
323 iounmap(addr_BAR_remap[0]);
324 iounmap(addr_BAR_remap[1]);
325 iounmap(addr_BAR_remap[2]);
326 iounmap(addr_BAR_remap[3]);
328 pci_release_region(pcidev,0);
329 pci_release_region(pcidev,1);
330 pci_release_region(pcidev,2);
331 pci_release_region(pcidev,3);
335 /* The function template_reset is used to give a hardware reset. This is rather
336 * hardware specific so I haven't included example code. Don't forget to check
337 * the reset status of the chip before returning.
339 int nsi_canpci_reset(struct candevice_t *candev)
341 unsigned long reg_reset;
343 DEBUGMSG("Reset de la carte !!!\n");
344 /* Il faut aussi desactiver les interruption du PLX, sous peine de freeze au prochain init_module */
345 nsi_canpci_disconnect_irq(candev);
346 // Recherche du registre de controle du PLX parmi les IO-port du PLX */
347 reg_reset = ioread32( (void*)(candev->dev_base_addr+PLX_CNTRL));
348 reg_reset&=(~(0x40000000));
349 iowrite32( (reg_reset | 0x40000000 ),(void*)(candev->dev_base_addr+PLX_CNTRL)); /* Mise à '1' du bit reset */
351 udelay(2500); /* Reset supérieur a 1ms car necessaire aux i82527 */
352 iowrite32(reg_reset,(void*)(candev->dev_base_addr+PLX_CNTRL)); /* Mise à '0' du bit reset */
354 udelay(2500); /* Attente, pour laisser les composants s'initialiser */
355 DEBUGMSG("Reset termine !!!\n");
357 nsi_canpci_connect_irq(candev);
361 /* The function template_init_hw_data is used to initialize the hardware
362 * structure containing information about the installed CAN-board.
363 * RESET_ADDR represents the io-address of the hardware reset register.
364 * NR_82527 represents the number of intel 82527 chips on the board.
365 * NR_SJA1000 represents the number of philips sja1000 chips on the board.
366 * The flags entry can currently only be CANDEV_PROGRAMMABLE_IRQ to indicate that
367 * the hardware uses programmable interrupts.
370 int nsi_canpci_init_hw_data(struct candevice_t *candev)
372 struct pci_dev *pcidev = NULL;
374 /* recherche de la carte NSI CANPCI sur le bus */
377 pcidev = pci_find_device(NSI_VENDOR_ID, NSI_CANPCI_DEVICE_ID, pcidev);
379 while(can_check_dev_taken(pcidev));
385 pcidev = pci_find_device(NSI_VENDOR_ID, NSI_CANPCI_DEVICE_ID+1, pcidev);
387 while(can_check_dev_taken(pcidev));
390 CANMSG ("Error : NSI CAN PCI device not found\n");
395 CANMSG ("NSI CANPCI OPTO device found\n");
400 CANMSG ("NSI CANPCI device found\n");
404 if (pci_enable_device (pcidev))
406 CANMSG ("Cannot enable PCI device\n");
409 CANMSG ("NSI CANPCI device started\n");
410 candev->sysdevptr.pcidev = pcidev;
412 candev->nr_82527_chips=2;
413 candev->nr_sja1000_chips=0;
414 candev->nr_all_chips=2;
415 /* initialize device spinlock */
416 can_spin_lock_init(&candev->device_lock);
418 if(pci_request_region(pcidev,0,"nsi_canpci bar0")==0)
420 if(pci_request_region(pcidev,1,"nsi_canpci bar1")==0)
422 if(pci_request_region(pcidev,2,"nsi_canpci bar2")==0)
424 if(pci_request_region(pcidev,3,"nsi_canpci bar3")==0)
429 pci_release_region(pcidev,0);
430 pci_release_region(pcidev,1);
431 pci_release_region(pcidev,2);
437 pci_release_region(pcidev,0);
438 pci_release_region(pcidev,1);
444 pci_release_region(pcidev,0);
453 addr_BAR_remap[0]=ioremap(pci_resource_start(pcidev,0),pci_resource_len(pcidev,0) );
454 addr_BAR_remap[1]=ioremap(pci_resource_start(pcidev,1),pci_resource_len(pcidev,1) );
455 addr_BAR_remap[2]=ioremap(pci_resource_start(pcidev,2),pci_resource_len(pcidev,2) );
456 addr_BAR_remap[3]=ioremap(pci_resource_start(pcidev,3),pci_resource_len(pcidev,3) );
458 candev->dev_base_addr=(unsigned long)(addr_BAR_remap[0]);
462 /* The function template_init_chip_data is used to initialize the hardware
463 * structure containing information about the CAN chips.
464 * CHIP_TYPE represents the type of CAN chip. CHIP_TYPE can be "i82527" or
466 * The chip_base_addr entry represents the start of the 'official' memory map
467 * of the installed chip. It's likely that this is the same as the candev->io_addr
468 * argument supplied at module loading time.
469 * The clock argument holds the chip clock value in Hz.
472 int nsi_canpci_init_chip_data(struct candevice_t *candev, int chipnr)
475 CANMSG ("NSI chip data init %d\n",chipnr);
476 i82527_fill_chipspecops(candev->chip[chipnr]);
478 candev->chip[chipnr]->chipspecops->chip_config =nsi_canpci_i82527_chip_config;
479 candev->chip[chipnr]->chipspecops->start_chip=nsi_canpci_start_chip;
480 candev->chip[chipnr]->chipspecops->stop_chip=nsi_canpci_stop_chip;
481 candev->chip[chipnr]->chipspecops->config_irqs=nsi_canpci_config_irqs;
482 candev->chip[chipnr]->chipspecops->irq_handler=nsi_canpci_irq_handler;
483 candev->chip[chipnr]->chip_data =candev;
485 candev->chip[chipnr]->chip_base_addr= (unsigned long)addr_BAR_remap[chipnr+2];
486 candev->chip[chipnr]->clock = 16000000;
487 candev->chip[chipnr]->chip_irq=candev->sysdevptr.pcidev->irq;
488 candev->chip[chipnr]->flags=CHIP_IRQ_PCI;
489 candev->chip[chipnr]->int_cpu_reg = iCPU_DSC+iCPU_CEN;
490 candev->chip[chipnr]->int_clk_reg = iCLK_SL1+iCLK_CD0;
491 candev->chip[chipnr]->int_bus_reg = iBUS_CBY;
495 /* The function template_init_obj_data is used to initialize the hardware
496 * structure containing information about the different message objects on the
497 * CAN chip. In case of the sja1000 there's only one message object but on the
498 * i82527 chip there are 15.
499 * The code below is for a i82527 chip and initializes the object base addresses
500 * The entry obj_base_addr represents the first memory address of the message
501 * object. In case of the sja1000 obj_base_addr is taken the same as the chips
503 * Unless the hardware uses a segmented memory map, flags can be set zero.
505 int nsi_canpci_init_obj_data(struct canchip_t *chip, int objnr)
509 chip->msgobj[objnr]->obj_base_addr=
510 chip->chip_base_addr+(objnr+1)*0x10;
515 /* The function template_program_irq is used for hardware that uses programmable
516 * interrupts. If your hardware doesn't use programmable interrupts you should
517 * not set the candevices_t->flags entry to CANDEV_PROGRAMMABLE_IRQ and leave this
518 * function unedited. Again this function is hardware specific so there's no
521 int nsi_canpci_program_irq(struct candevice_t *candev)
526 /* The function template_write_register is used to write to hardware registers
527 * on the CAN chip. You should only have to edit this function if your hardware
528 * uses some specific write process.
530 void nsi_canpci_write_register(unsigned data, unsigned long address)
532 iowrite8((u8)data,(void*)address);
533 wmb(); /* Assure que la donnee a ete ecrite */
536 /* The function template_read_register is used to read from hardware registers
537 * on the CAN chip. You should only have to edit this function if your hardware
538 * uses some specific read process.
540 unsigned nsi_canpci_read_register(unsigned long address)
542 /* this is the same thing that the function write_register.
543 We use the two register, we write the address where we
544 want to read in a first time. In a second time we read the
547 can_spin_irqflags_t flags;
548 can_spin_lock_irqsave(&nsicanpci_port_lock,flags);
550 ret=ioread8((void*)address);
551 can_spin_unlock_irqrestore(&nsicanpci_port_lock,flags);
556 /* !!! Don't change this function !!! */
557 int nsi_canpci_register(struct hwspecops_t *hwspecops)
559 hwspecops->request_io = nsi_canpci_request_io;
560 hwspecops->release_io = nsi_canpci_release_io;
561 hwspecops->reset = nsi_canpci_reset;
562 hwspecops->init_hw_data = nsi_canpci_init_hw_data;
563 hwspecops->init_chip_data = nsi_canpci_init_chip_data;
564 hwspecops->init_obj_data = nsi_canpci_init_obj_data;
565 hwspecops->write_register = nsi_canpci_write_register;
566 hwspecops->read_register = nsi_canpci_read_register;
567 hwspecops->program_irq = nsi_canpci_program_irq;