2 * Linux CAN-bus device driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
5 * email:pisa@cmp.felk.cvut.cz
6 * This software is released under the GPL-License.
7 * Version lincan-0.2 9 Jul 2003
10 /* This file contains the low level functions for the pcccan-1 card from Gespac.
11 * You can probably find more information at http://www.gespac.com
14 #include "../include/can.h"
15 #include "../include/can_sysdep.h"
16 #include "../include/main.h"
17 #include "../include/pcccan.h"
18 #include "../include/i82527.h"
21 unsigned long pcccan_base=0x0;
23 static can_spinlock_t pcccan_port_lock=SPIN_LOCK_UNLOCKED;
26 * IO_RANGE is the io-memory range that gets reserved, please adjust according
27 * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
28 * #define IO_RANGE 0x20 for sja1000 chips in basic CAN mode.
31 /* The pcccan card uses indexed addressing hence the need to only reserve
32 * eight bytes of memory.
34 * base + 1 = Address loading
35 * base + 2 = Read register
36 * base + 3 = Read register + increment loaded address (saves a write operation
37 * when accessing consecutive registers)
39 * base + 5 = Address read
40 * base + 6 = Write register
41 * base + 7 = Write register + increment loaded address
46 * pcccan_request_io: - reserve io or memory range for can board
47 * @candev: pointer to candevice/board which asks for io. Field @io_addr
48 * of @candev is used in most cases to define start of the range
50 * The function pcccan_request_io() is used to reserve the io-memory. If your
51 * hardware uses a dedicated memory range as hardware control registers you
52 * will have to add the code to reserve this memory as well.
53 * %IO_RANGE is the io-memory range that gets reserved, please adjust according
54 * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
55 * #define IO_RANGE 0x20 for sja1000 chips in basic CAN mode.
56 * Return Value: The function returns zero on success or %-ENODEV on failure
59 int pcccan_request_io(struct candevice_t *candev)
61 if (!can_request_io_region(candev->io_addr,IO_RANGE,DEVICE_NAME)) {
62 CANMSG("Unable to open port: 0x%lx\n",candev->io_addr);
65 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", candev->io_addr, candev->io_addr + IO_RANGE - 1);
71 * pcccan_elease_io - free reserved io memory range
72 * @candev: pointer to candevice/board which releases io
74 * The function pcccan_release_io() is used to free reserved io-memory.
75 * In case you have reserved more io memory, don't forget to free it here.
76 * IO_RANGE is the io-memory range that gets released, please adjust according
77 * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
78 * #define IO_RANGE 0x20 for sja1000 chips in basic CAN mode.
79 * Return Value: The function always returns zero
82 int pcccan_release_io(struct candevice_t *candev)
84 can_release_io_region(candev->io_addr,IO_RANGE);
90 * pcccan_reset - hardware reset routine
91 * @candev: Pointer to candevice/board structure
93 * The function pcccan_reset() is used to give a hardware reset. This is
94 * rather hardware specific so I haven't included example code. Don't forget to
95 * check the reset status of the chip before returning.
96 * Return Value: The function returns zero on success or %-ENODEV on failure
99 int pcccan_reset(struct candevice_t *candev)
103 DEBUGMSG("Resetting pcccan-1 hardware ...\n");
104 while (i < 1000000) {
106 outb(0x0,candev->res_addr);
109 /* Check hardware reset status */
111 outb(iCPU,candev->io_addr+0x1);
112 while ( (inb(candev->io_addr+0x2)&0x80) && (i<=15) ) {
117 CANMSG("Reset status timeout!\n");
118 CANMSG("Please check your hardware.\n");
122 DEBUGMSG("Chip reset status ok.\n");
131 * pcccan_init_hw_data - Initialize hardware cards
132 * @candev: Pointer to candevice/board structure
134 * The function pcccan_init_hw_data() is used to initialize the hardware
135 * structure containing information about the installed CAN-board.
136 * %RESET_ADDR represents the io-address of the hardware reset register.
137 * %NR_82527 represents the number of intel 82527 chips on the board.
138 * %NR_SJA1000 represents the number of philips sja1000 chips on the board.
139 * The flags entry can currently only be %CANDEV_PROGRAMMABLE_IRQ to indicate that
140 * the hardware uses programmable interrupts.
141 * Return Value: The function always returns zero
144 int pcccan_init_hw_data(struct candevice_t *candev)
146 candev->res_addr=candev->io_addr;
147 candev->nr_82527_chips=NR_82527;
148 candev->nr_sja1000_chips=NR_SJA1000;
149 candev->nr_all_chips=NR_82527+NR_SJA1000;
150 candev->flags &= ~CANDEV_PROGRAMMABLE_IRQ;
155 #define CHIP_TYPE "i82527"
157 * pcccan_init_chip_data - Initialize chips
158 * @candev: Pointer to candevice/board structure
159 * @chipnr: Number of the CAN chip on the hardware card
161 * The function pcccan_init_chip_data() is used to initialize the hardware
162 * structure containing information about the CAN chips.
163 * %CHIP_TYPE represents the type of CAN chip. %CHIP_TYPE can be "i82527" or
165 * The @chip_base_addr entry represents the start of the 'official' memory map
166 * of the installed chip. It's likely that this is the same as the @io_addr
167 * argument supplied at module loading time.
168 * The @clock entry holds the chip clock value in Hz.
169 * The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
170 * register. Options defined in the %sja1000.h file:
171 * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
172 * The entry @sja_ocr_reg holds hardware specific options for the Output Control
173 * register. Options defined in the %sja1000.h file:
174 * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
175 * %OCR_TX0_LH, %OCR_TX1_ZZ.
176 * The entry @int_clk_reg holds hardware specific options for the Clock Out
177 * register. Options defined in the %i82527.h file:
178 * %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
179 * The entry @int_bus_reg holds hardware specific options for the Bus
180 * Configuration register. Options defined in the %i82527.h file:
181 * %iBUS_DR0, %iBUS_DR1, %iBUS_DT1, %iBUS_POL, %iBUS_CBY.
182 * The entry @int_cpu_reg holds hardware specific options for the cpu interface
183 * register. Options defined in the %i82527.h file:
184 * %iCPU_CEN, %iCPU_MUX, %iCPU_SLP, %iCPU_PWD, %iCPU_DMC, %iCPU_DSC, %iCPU_RST.
185 * Return Value: The function always returns zero
188 int pcccan_init_chip_data(struct candevice_t *candev, int chipnr)
190 candev->chip[chipnr]->chip_type=CHIP_TYPE;
191 candev->chip[chipnr]->chip_base_addr=candev->io_addr;
192 candev->chip[chipnr]->clock = 16000000;
193 candev->chip[chipnr]->int_cpu_reg = iCPU_DSC | iCPU_DMC;
194 candev->chip[chipnr]->int_clk_reg = iCLK_SL1 | iCLK_CD0;
195 candev->chip[chipnr]->int_bus_reg = iBUS_CBY | iBUS_DR1;
196 candev->chip[chipnr]->sja_cdr_reg = 0;
197 candev->chip[chipnr]->sja_ocr_reg = 0;
198 pcccan_irq=candev->chip[chipnr]->chip_irq;
199 pcccan_base=candev->chip[chipnr]->chip_base_addr;
205 * pcccan_init_obj_data - Initialize message buffers
206 * @chip: Pointer to chip specific structure
207 * @objnr: Number of the message buffer
209 * The function pcccan_init_obj_data() is used to initialize the hardware
210 * structure containing information about the different message objects on the
211 * CAN chip. In case of the sja1000 there's only one message object but on the
212 * i82527 chip there are 15.
213 * The code below is for a i82527 chip and initializes the object base addresses
214 * The entry @obj_base_addr represents the first memory address of the message
215 * object. In case of the sja1000 @obj_base_addr is taken the same as the chips
217 * Unless the hardware uses a segmented memory map, flags can be set zero.
218 * Return Value: The function always returns zero
221 int pcccan_init_obj_data(struct chip_t *chip, int objnr)
223 chip->msgobj[objnr]->obj_base_addr=(objnr+1)*0x10;
229 * pcccan_program_irq - program interrupts
230 * @candev: Pointer to candevice/board structure
232 * The function pcccan_program_irq() is used for hardware that uses
233 * programmable interrupts. If your hardware doesn't use programmable interrupts
234 * you should not set the @candevices_t->flags entry to %CANDEV_PROGRAMMABLE_IRQ and
235 * leave this function unedited. Again this function is hardware specific so
236 * there's no example code.
237 * Return value: The function returns zero on success or %-ENODEV on failure
240 int pcccan_program_irq(struct candevice_t *candev)
246 * pcccan_write_register - Low level write register routine
247 * @data: data to be written
248 * @address: memory address to write to
250 * The function pcccan_write_register() is used to write to hardware registers
251 * on the CAN chip. You should only have to edit this function if your hardware
252 * uses some specific write process.
253 * Return Value: The function does not return a value
256 void pcccan_write_register(unsigned char data, unsigned long address)
258 can_spin_irqflags_t flags;
259 can_spin_lock_irqsave(&pcccan_port_lock,flags);
260 outb(address - pcccan_base, pcccan_base+1);
261 outb(data, pcccan_base+6);
262 can_spin_unlock_irqrestore(&pcccan_port_lock,flags);
266 * pcccan_read_register - Low level read register routine
267 * @address: memory address to read from
269 * The function pcccan_read_register() is used to read from hardware registers
270 * on the CAN chip. You should only have to edit this function if your hardware
271 * uses some specific read process.
272 * Return Value: The function returns the value stored in @address
275 unsigned pcccan_read_register(unsigned long address)
278 can_spin_irqflags_t flags;
279 can_spin_lock_irqsave(&pcccan_port_lock,flags);
280 outb(address - pcccan_base, pcccan_base+1);
281 ret=inb(pcccan_base+2);
282 can_spin_unlock_irqrestore(&pcccan_port_lock,flags);
287 /* !!! Don't change this function !!! */
288 int pcccan_register(struct hwspecops_t *hwspecops)
290 hwspecops->request_io = pcccan_request_io;
291 hwspecops->release_io = pcccan_release_io;
292 hwspecops->reset = pcccan_reset;
293 hwspecops->init_hw_data = pcccan_init_hw_data;
294 hwspecops->init_chip_data = pcccan_init_chip_data;
295 hwspecops->init_obj_data = pcccan_init_obj_data;
296 hwspecops->write_register = pcccan_write_register;
297 hwspecops->read_register = pcccan_read_register;
298 hwspecops->program_irq = pcccan_program_irq;