4 Routines for sending and receiving messages for configuration and/or
5 communication over CAN network using a SJA1000 transceiver.
6 For use in UL_USB1 module, it runs in Intel mode.
7 See documentation for details.
15 #if SJA1000_CLK==(24000000)
16 /* Bus speed, Precaler, SJW, TSEG1, TSEG2
17 * For SJW setting we assume 1% xtal accuracy
19 const long sja1000_freqs[3][5]=
20 {{1000, 0x00, 0xC0, 0x08, 0x10}
21 ,{250, 0x02, 0xC0, 0x0A, 0x30}
22 ,{100, 0x07, 0xC0, 0x09, 0x30}};
23 const int sja1000_freq_cnt=3;
26 struct can_baudparams_t canbaud;
30 // Due to change in design there is CS_PIN connected with ALE_PIN and ALE_PIN connection to LPC is interrupted
31 // We don't use ALE_PIN
32 //IO0DIR|=P0_SJA1000_ALE_PIN|P0_SJA1000_CS_PIN|P0_SJA1000_RD_PIN|P0_SJA1000_WR_PIN;
33 IO0DIR|=P0_SJA1000_CS_PIN|P0_SJA1000_RD_PIN|P0_SJA1000_WR_PIN;
34 IO0DIR&=~(P0_SJA1000_INT_PIN);
36 SET_OUT_PIN(IO0,P0_SJA1000_CS_PIN);
37 CLR_OUT_PIN(IO1,P1_SJA1000_RST_PIN);
39 SET_OUT_PIN(IO0,P0_SJA1000_CS_PIN);
40 // Due to change in design there is CS_PIN connected with ALE_PIN and ALE_PIN connection to LPC is interrupted
41 // CLR_OUT_PIN(IO0,P0_SJA1000_ALE_PIN);
42 SET_OUT_PIN(IO1,P1_SJA1000_RST_PIN);
46 int can_write(uint8_t address,uint8_t* data)
48 IO1DIR|=0x00FF0000; // Port as output to send data
49 IO1CLR=0x00FF0000; // Clear all data on port
51 SET_OUT_PIN(IO0,P0_SJA1000_RD_PIN); // Stays high on write
52 SET_OUT_PIN(IO0,P0_SJA1000_WR_PIN); // Stays high on address write
53 SET_OUT_PIN(IO0,P0_SJA1000_CS_PIN); // Sets output buffers to third state
55 //SET_OUT_PIN(IO0,P0_SJA1000_ALE_PIN); // Start command
58 IO1SET=__val2mfld(0x00FF0000,address); // Shift data to SJA pins and output them
60 //CLR_OUT_PIN(IO0,P0_SJA1000_ALE_PIN); // Makes address active
61 CLR_OUT_PIN(IO0,P0_SJA1000_CS_PIN);
65 CLR_OUT_PIN(IO0,P0_SJA1000_WR_PIN);
68 IO1SET=__val2mfld(0x00FF0000,*data);
70 SET_OUT_PIN(IO0,P0_SJA1000_WR_PIN); // Data should be accepted by now
71 SET_OUT_PIN(IO0,P0_SJA1000_CS_PIN);
76 int can_read(const uint8_t address,uint8_t* data)
78 IO1DIR|=0x00FF0000; // Port as output to set address
79 IO1CLR=0x00FF0000; // Clear all data
81 SET_OUT_PIN(IO0,P0_SJA1000_WR_PIN); // Stays high on read
82 SET_OUT_PIN(IO0,P0_SJA1000_RD_PIN); // Stays high while entering address
83 SET_OUT_PIN(IO0,P0_SJA1000_CS_PIN);
85 //SET_OUT_PIN(IO0,P0_SJA1000_ALE_PIN);
87 // Request memory address
88 IO1SET=__val2mfld(0x00FF0000,address);
90 //CLR_OUT_PIN(IO0,P0_SJA1000_ALE_PIN);
91 CLR_OUT_PIN(IO0,P0_SJA1000_CS_PIN);
95 IO1DIR&=~0x00FF0000; // Sets port as input
96 CLR_OUT_PIN(IO0,P0_SJA1000_RD_PIN);
98 *data=__mfld2val(0x00FF0000,IO1PIN);
99 SET_OUT_PIN(IO0,P0_SJA1000_RD_PIN);
100 SET_OUT_PIN(IO0,P0_SJA1000_CS_PIN);
106 uint8_t data=0,count=0;
109 can_read(SJAMOD,&data);
112 } while (!(data&sjaMOD_RM));
114 data=sjaCDR_CLKOUT_DIV1|sjaCDR_CLK_OFF|sjaCDR_CBP|sjaCDR_PELICAN;
115 can_write((uint8_t)SJACDR,(uint8_t*)&data);
117 // Single acceptance filter, reset mode
118 data=sjaMOD_AFM|sjaMOD_RM;
119 can_write((uint8_t)SJAMOD,(uint8_t*)&data);
121 // Enabling all interrupt sources
122 data=sjaENABLE_INTERRUPTS;
123 can_write((uint8_t)SJAIER,(uint8_t*)&data);
125 // Accept all messages
127 can_write((uint8_t)SJAAMR0,(uint8_t*)&data);
128 can_write((uint8_t)SJAAMR0+1,(uint8_t*)&data);
129 can_write((uint8_t)SJAAMR0+2,(uint8_t*)&data);
130 can_write((uint8_t)SJAAMR0+3,(uint8_t*)&data);
133 can_write((uint8_t)SJACMR,(uint8_t*)&data);