lincan/src/sja1000p.c

   1 /* sja1000.c
   2  * Linux CAN-bus device driver.
   3  * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
   4  * Changed for PeliCan mode SJA1000 by Tomasz Motylewski (BFAD GmbH)
   5  * T.Motylewski@bfad.de
   6  * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
   7  * email:pisa@cmp.felk.cvut.cz
   8  * This software is released under the GPL-License.
   9  * Version lincan-0.2  9 Jul 2003
  10  */
  11
  12 #include <linux/autoconf.h>
  13
  14 #include <linux/sched.h>
  15 #include <linux/delay.h>
  16 #include <asm/irq.h>
  17
  18 #include "../include/main.h"
  19 #include "../include/sja1000p.h"
  20
  21 /**
  22  * sja1000p_enable_configuration - enable chip configuration mode
  23  * @chip: pointer to chip state structure
  24  */
  25 int sja1000p_enable_configuration(struct chip_t *chip)
  26 {
  27         int i=0;
  28         enum sja1000_PeliCAN_MOD flags;
  29
  30         disable_irq(chip->chip_irq);
  31
  32         flags=can_read_reg(chip,SJAMOD);
  33
  34         while ((!(flags & MOD_RM)) && (i<=10)) {
  35                 can_write_reg(chip, MOD_RM, SJAMOD);
  36 // TODO: configurable MOD_AFM (32/16 bit acceptance filter)
  37 // config MOD_LOM (listen only)
  38                 udelay(100);
  39                 i++;
  40                 flags=can_read_reg(chip, SJAMOD);
  41         }
  42         if (i>=10) {
  43                 CANMSG("Reset error\n");
  44                 enable_irq(chip->chip_irq);
  45                 return -ENODEV;
  46         }
  47
  48         return 0;
  49 }
  50
  51 /**
  52  * sja1000p_disable_configuration - disable chip configuration mode
  53  * @chip: pointer to chip state structure
  54  */
  55 int sja1000p_disable_configuration(struct chip_t *chip)
  56 {
  57         int i=0;
  58         enum sja1000_PeliCAN_MOD flags;
  59
  60         flags=can_read_reg(chip,SJAMOD);
  61
  62         while ( (flags & MOD_RM) && (i<=50) ) {
  63 // could be as long as 11*128 bit times after buss-off
  64                 can_write_reg(chip, 0, SJAMOD);
  65 // TODO: configurable MOD_AFM (32/16 bit acceptance filter)
  66 // config MOD_LOM (listen only)
  67                 udelay(100);
  68                 i++;
  69                 flags=can_read_reg(chip, SJAMOD);
  70         }
  71         if (i>=10) {
  72                 CANMSG("Error leaving reset status\n");
  73                 return -ENODEV;
  74         }
  75
  76         enable_irq(chip->chip_irq);
  77
  78         return 0;
  79 }
  80
  81 /**
  82  * sja1000p_chip_config: - can chip configuration
  83  * @chip: pointer to chip state structure
  84  *
  85  * This function configures chip and prepares it for message
  86  * transmission and reception. The function resets chip,
  87  * resets mask for acceptance of all messages by call to
  88  * sja1000p_extended_mask() function and then
  89  * computes and sets baudrate with use of function sja1000p_baud_rate().
  90  * Return Value: negative value reports error.
  91  * File: src/sja1000p.c
  92  */
  93 int sja1000p_chip_config(struct chip_t *chip)
  94 {
  95         if (sja1000p_enable_configuration(chip))
  96                 return -ENODEV;
  97
  98         /* Set mode, clock out, comparator */
  99         can_write_reg(chip,CDR_PELICAN|chip->sja_cdr_reg,SJACDR);
 100         /* Set driver output configuration */
 101         can_write_reg(chip,chip->sja_ocr_reg,SJAOCR);
 102
 103         if (sja1000p_extended_mask(chip,0x00000000, 0xffffffff))
 104                 return -ENODEV;
 105
 106         if (!baudrate)
 107                 baudrate=1000;
 108         if (sja1000p_baud_rate(chip,1000*baudrate,chip->clock,0,75,0))
 109                 return -ENODEV;
 110
 111         /* Enable hardware interrupts */
 112         can_write_reg(chip, ENABLE_INTERRUPTS, SJAIER);
 113
 114         sja1000p_disable_configuration(chip);
 115
 116         return 0;
 117 }
 118
 119 /**
 120  * sja1000p_extended_mask: - setup of extended mask for message filtering
 121  * @chip: pointer to chip state structure
 122  * @code: can message acceptance code
 123  * @mask: can message acceptance mask
 124  *
 125  * Return Value: negative value reports error.
 126  * File: src/sja1000p.c
 127  */
 128 int sja1000p_extended_mask(struct chip_t *chip, unsigned long code, unsigned  long mask)
 129 {
 130         int i;
 131
 132         if (sja1000p_enable_configuration(chip))
 133                 return -ENODEV;
 134
 135 // LSB to +3, MSB to +0
 136         for(i=SJA_PeliCAN_AC_LEN; --i>=0;) {
 137                 can_write_reg(chip,code&0xff,SJAACR0+i);
 138                 can_write_reg(chip,mask&0xff,SJAAMR0+i);
 139                 code >>= 8;
 140                 mask >>= 8;
 141         }
 142
 143         DEBUGMSG("Setting acceptance code to 0x%lx\n",(unsigned long)code);
 144         DEBUGMSG("Setting acceptance mask to 0x%lx\n",(unsigned long)mask);
 145
 146         sja1000p_disable_configuration(chip);
 147
 148         return 0;
 149 }
 150
 151 /**
 152  * sja1000p_baud_rate: - set communication parameters.
 153  * @chip: pointer to chip state structure
 154  * @rate: baud rate in Hz
 155  * @clock: frequency of sja1000 clock in Hz (ISA osc is 14318000)
 156  * @sjw: synchronization jump width (0-3) prescaled clock cycles
 157  * @sampl_pt: sample point in % (0-100) sets (TSEG1+1)/(TSEG1+TSEG2+2) ratio
 158  * @flags: fields %BTR1_SAM, %OCMODE, %OCPOL, %OCTP, %OCTN, %CLK_OFF, %CBP
 159  *
 160  * Return Value: negative value reports error.
 161  * File: src/sja1000p.c
 162  */
 163 int sja1000p_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,
 164                                                         int sampl_pt, int flags)
 165 {
 166         int best_error = 1000000000, error;
 167         int best_tseg=0, best_brp=0, best_rate=0, brp=0;
 168         int tseg=0, tseg1=0, tseg2=0;
 169
 170         if (sja1000p_enable_configuration(chip))
 171                 return -ENODEV;
 172
 173         clock /=2;
 174
 175         /* tseg even = round down, odd = round up */
 176         for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++) {
 177                 brp = clock/((1+tseg/2)*rate)+tseg%2;
 178                 if (brp == 0 || brp > 64)
 179                         continue;
 180                 error = rate - clock/(brp*(1+tseg/2));
 181                 if (error < 0)
 182                         error = -error;
 183                 if (error <= best_error) {
 184                         best_error = error;
 185                         best_tseg = tseg/2;
 186                         best_brp = brp-1;
 187                         best_rate = clock/(brp*(1+tseg/2));
 188                 }
 189         }
 190         if (best_error && (rate/best_error < 10)) {
 191                 CANMSG("baud rate %d is not possible with %d Hz clock\n",
 192                                                                 rate, 2*clock);
 193                 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
 194                                 best_rate, best_brp, best_tseg, tseg1, tseg2);
 195                 return -EINVAL;
 196         }
 197         tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
 198         if (tseg2 < 0)
 199                 tseg2 = 0;
 200         if (tseg2 > MAX_TSEG2)
 201                 tseg2 = MAX_TSEG2;
 202         tseg1 = best_tseg-tseg2-2;
 203         if (tseg1>MAX_TSEG1) {
 204                 tseg1 = MAX_TSEG1;
 205                 tseg2 = best_tseg-tseg1-2;
 206         }
 207
 208         DEBUGMSG("Setting %d bps.\n", best_rate);
 209         DEBUGMSG("brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
 210                                         best_brp, best_tseg, tseg1, tseg2,
 211                                         (100*(best_tseg-tseg2)/(best_tseg+1)));
 212
 213
 214         can_write_reg(chip, sjw<<6 | best_brp, SJABTR0);
 215         can_write_reg(chip, ((flags & BTR1_SAM) != 0)<<7 | (tseg2<<4)
 216                                         | tseg1, SJABTR1);
 217
 218         sja1000p_disable_configuration(chip);
 219
 220         return 0;
 221 }
 222
 223 /**
 224  * sja1000p_read: - reads and distributes one or more received messages
 225  * @chip: pointer to chip state structure
 226  * @obj: pinter to CAN message queue information
 227  *
 228  * File: src/sja1000p.c
 229  */
 230 void sja1000p_read(struct chip_t *chip, struct msgobj_t *obj) {
 231         int i, flags, len, datastart;
 232         do {
 233                 flags = can_read_reg(chip,SJAFRM);
 234                 if(flags&FRM_FF) {
 235                         obj->rx_msg.id =
 236                                 (can_read_reg(chip,SJAID0)<<21) +
 237                                 (can_read_reg(chip,SJAID1)<<13) +
 238                                 (can_read_reg(chip,SJAID2)<<5) +
 239                                 (can_read_reg(chip,SJAID3)>>3);
 240                         datastart = SJADATE;
 241                 } else {
 242                         obj->rx_msg.id =
 243                                 (can_read_reg(chip,SJAID0)<<3) +
 244                                 (can_read_reg(chip,SJAID1)>>5);
 245                         datastart = SJADATS;
 246                 }
 247                 obj->rx_msg.flags =
 248                         ((flags & FRM_RTR) ? MSG_RTR : 0) |
 249                         ((flags & FRM_FF) ? MSG_EXT : 0);
 250                 len = flags & FRM_DLC_M;
 251                 for(i=0; i< len; i++) {
 252                         obj->rx_msg.data[i]=can_read_reg(chip,datastart+i);
 253                 }
 254                 obj->rx_msg.length = len;
 255
 256                 canque_filter_msg2edges(obj->qends, &obj->rx_msg);
 257
 258                 can_write_reg(chip, CMR_RRB, SJACMR);
 259
 260         } while (can_read_reg(chip, SJASR) & SR_RBS);
 261 }
 262
 263 /**
 264  * sja1000p_pre_read_config: - prepares message object for message reception
 265  * @chip: pointer to chip state structure
 266  * @obj: pointer to message object state structure
 267  *
 268  * Return Value: negative value reports error.
 269  *      Positive value indicates immediate reception of message.
 270  * File: src/sja1000p.c
 271  */
 272 int sja1000p_pre_read_config(struct chip_t *chip, struct msgobj_t *obj)
 273 {
 274         int status;
 275         status=can_read_reg(chip,SJASR);
 276
 277         if(status  & SR_BS) {
 278                 /* Try to recover from error condition */
 279                 DEBUGMSG("sja1000p_pre_read_config bus-off recover 0x%x\n",status);
 280                 sja1000p_enable_configuration(chip);
 281                 can_write_reg(chip, 0, SJARXERR);
 282                 can_write_reg(chip, 0, SJATXERR1);
 283                 can_read_reg(chip, SJAECC);
 284                 sja1000p_disable_configuration(chip);
 285         }
 286
 287         if (!(status&SR_RBS)) {
 288                 return 0;
 289         }
 290
 291         can_write_reg(chip, DISABLE_INTERRUPTS, SJAIER); //disable interrupts for a moment
 292         sja1000p_read(chip, obj);
 293         can_write_reg(chip, ENABLE_INTERRUPTS, SJAIER); //enable interrupts
 294         return 1;
 295 }
 296
 297 #define MAX_TRANSMIT_WAIT_LOOPS 10
 298 /**
 299  * sja1000p_pre_write_config: - prepares message object for message transmission
 300  * @chip: pointer to chip state structure
 301  * @obj: pointer to message object state structure
 302  * @msg: pointer to CAN message
 303  *
 304  * This function prepares selected message object for future initiation
 305  * of message transmission by sja1000p_send_msg() function.
 306  * The CAN message data and message ID are transfered from @msg slot
 307  * into chip buffer in this function.
 308  * Return Value: negative value reports error.
 309  * File: src/sja1000p.c
 310  */
 311 int sja1000p_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
 312                                                         struct canmsg_t *msg)
 313 {
 314         int i=0;
 315         unsigned int id;
 316         int status;
 317
 318         /* Wait until Transmit Buffer Status is released */
 319         while ( !((status=can_read_reg(chip, SJASR)) & SR_TBS) &&
 320                                                 i++<MAX_TRANSMIT_WAIT_LOOPS) {
 321                 udelay(i);
 322         }
 323
 324         if(status & SR_BS) {
 325                 /* Try to recover from error condition */
 326                 DEBUGMSG("sja1000p_pre_write_config bus-off recover 0x%x\n",status);
 327                 sja1000p_enable_configuration(chip);
 328                 can_write_reg(chip, 0, SJARXERR);
 329                 can_write_reg(chip, 0, SJATXERR1);
 330                 can_read_reg(chip, SJAECC);
 331                 sja1000p_disable_configuration(chip);
 332         }
 333         if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
 334                 CANMSG("Transmit timed out, cancelling\n");
 335 // here we should check if there is no write/select waiting for this
 336 // transmit. If so, set error ret and wake up.
 337 // CHECKME: if we do not disable IER_TIE (TX IRQ) here we get interrupt
 338 // immediately
 339                 can_write_reg(chip, CMR_AT, SJACMR);
 340                 i=0;
 341                 while ( !(can_read_reg(chip, SJASR) & SR_TBS) &&
 342                                                 i++<MAX_TRANSMIT_WAIT_LOOPS) {
 343                         udelay(i);
 344                 }
 345                 if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
 346                         CANMSG("Could not cancel, please reset\n");
 347                         return -EIO;
 348                 }
 349         }
 350         msg->length &= FRM_DLC_M;
 351         can_write_reg(chip, ((msg->flags&MSG_EXT)?FRM_FF:0) |
 352                 ((msg->flags & MSG_RTR) ? FRM_RTR : 0) |
 353                 msg->length, SJAFRM);
 354         if(msg->flags&MSG_EXT) {
 355                 id=msg->id<<3;
 356                 can_write_reg(chip, id & 0xff, SJAID3);
 357                 id >>= 8;
 358                 can_write_reg(chip, id & 0xff, SJAID2);
 359                 id >>= 8;
 360                 can_write_reg(chip, id & 0xff, SJAID1);
 361                 id >>= 8;
 362                 can_write_reg(chip, id, SJAID0);
 363                 for(i=0; i < msg->length; i++) {
 364                         can_write_reg(chip, msg->data[i], SJADATE+i);
 365                 }
 366         } else {
 367                 id=msg->id<<5;
 368                 can_write_reg(chip, (id >> 8) & 0xff, SJAID0);
 369                 can_write_reg(chip, id & 0xff, SJAID1);
 370                 for(i=0; i < msg->length; i++) {
 371                         can_write_reg(chip, msg->data[i], SJADATS+i);
 372                 }
 373         }
 374         return 0;
 375 }
 376
 377 /**
 378  * sja1000p_send_msg: - initiate message transmission
 379  * @chip: pointer to chip state structure
 380  * @obj: pointer to message object state structure
 381  * @msg: pointer to CAN message
 382  *
 383  * This function is called after sja1000p_pre_write_config() function,
 384  * which prepares data in chip buffer.
 385  * Return Value: negative value reports error.
 386  * File: src/sja1000p.c
 387  */
 388 int sja1000p_send_msg(struct chip_t *chip, struct msgobj_t *obj,
 389                                                         struct canmsg_t *msg)
 390 {
 391         can_write_reg(chip, CMR_TR, SJACMR);
 392
 393         return 0;
 394 }
 395
 396 /**
 397  * sja1000p_check_tx_stat: - checks state of transmission engine
 398  * @chip: pointer to chip state structure
 399  *
 400  * Return Value: negative value reports error.
 401  *      Positive return value indicates transmission under way status.
 402  *      Zero value indicates finishing of all issued transmission requests.
 403  * File: src/sja1000p.c
 404  */
 405 int sja1000p_check_tx_stat(struct chip_t *chip)
 406 {
 407         if (can_read_reg(chip,SJASR) & SR_TCS)
 408                 return 0;
 409         else
 410                 return 1;
 411 }
 412
 413 /**
 414  * sja1000p_set_btregs: -  configures bitrate registers
 415  * @chip: pointer to chip state structure
 416  * @btr0: bitrate register 0
 417  * @btr1: bitrate register 1
 418  *
 419  * Return Value: negative value reports error.
 420  * File: src/sja1000p.c
 421  */
 422 int sja1000p_set_btregs(struct chip_t *chip, unsigned short btr0,
 423                                                         unsigned short btr1)
 424 {
 425         if (sja1000p_enable_configuration(chip))
 426                 return -ENODEV;
 427
 428         can_write_reg(chip, btr0, SJABTR0);
 429         can_write_reg(chip, btr1, SJABTR1);
 430
 431         sja1000p_disable_configuration(chip);
 432
 433         return 0;
 434 }
 435
 436 /**
 437  * sja1000p_start_chip: -  starts chip message processing
 438  * @chip: pointer to chip state structure
 439  *
 440  * Return Value: negative value reports error.
 441  * File: src/sja1000p.c
 442  */
 443 int sja1000p_start_chip(struct chip_t *chip)
 444 {
 445         enum sja1000_PeliCAN_MOD flags;
 446
 447         flags = can_read_reg(chip, SJAMOD) & (MOD_LOM|MOD_STM|MOD_AFM|MOD_SM);
 448         can_write_reg(chip, flags, SJAMOD);
 449
 450         return 0;
 451 }
 452
 453 /**
 454  * sja1000p_stop_chip: -  stops chip message processing
 455  * @chip: pointer to chip state structure
 456  *
 457  * Return Value: negative value reports error.
 458  * File: src/sja1000p.c
 459  */
 460 int sja1000p_stop_chip(struct chip_t *chip)
 461 {
 462         enum sja1000_PeliCAN_MOD flags;
 463
 464         flags = can_read_reg(chip, SJAMOD) & (MOD_LOM|MOD_STM|MOD_AFM|MOD_SM);
 465         can_write_reg(chip, flags|MOD_RM, SJAMOD);
 466
 467         return 0;
 468 }
 469
 470
 471 /**
 472  * sja1000p_remote_request: - configures message object and asks for RTR message
 473  * @chip: pointer to chip state structure
 474  * @obj: pointer to message object structure
 475  *
 476  * Return Value: negative value reports error.
 477  * File: src/sja1000p.c
 478  */
 479 int sja1000p_remote_request(struct chip_t *chip, struct msgobj_t *obj)
 480 {
 481         CANMSG("sja1000p_remote_request not implemented\n");
 482         return -ENOSYS;
 483 }
 484
 485 /**
 486  * sja1000p_standard_mask: - setup of mask for message filtering
 487  * @chip: pointer to chip state structure
 488  * @code: can message acceptance code
 489  * @mask: can message acceptance mask
 490  *
 491  * Return Value: negative value reports error.
 492  * File: src/sja1000p.c
 493  */
 494 int sja1000p_standard_mask(struct chip_t *chip, unsigned short code,
 495                 unsigned short mask)
 496 {
 497         CANMSG("sja1000p_standard_mask not implemented\n");
 498         return -ENOSYS;
 499 }
 500
 501 /**
 502  * sja1000p_clear_objects: - clears state of all message object residing in chip
 503  * @chip: pointer to chip state structure
 504  *
 505  * Return Value: negative value reports error.
 506  * File: src/sja1000p.c
 507  */
 508 int sja1000p_clear_objects(struct chip_t *chip)
 509 {
 510         CANMSG("sja1000p_clear_objects not implemented\n");
 511         return -ENOSYS;
 512 }
 513
 514 /**
 515  * sja1000p_config_irqs: - tunes chip hardware interrupt delivery
 516  * @chip: pointer to chip state structure
 517  * @irqs: requested chip IRQ configuration
 518  *
 519  * Return Value: negative value reports error.
 520  * File: src/sja1000p.c
 521  */
 522 int sja1000p_config_irqs(struct chip_t *chip, short irqs)
 523 {
 524         CANMSG("sja1000p_config_irqs not implemented\n");
 525         return -ENOSYS;
 526 }
 527
 528 /**
 529  * sja1000p_irq_write_handler: - part of ISR code responsible for transmit events
 530  * @chip: pointer to chip state structure
 531  * @obj: pointer to attached queue description
 532  *
 533  * The main purpose of this function is to read message from attached queues
 534  * and transfer message contents into CAN controller chip.
 535  * This subroutine is called by
 536  * sja1000p_irq_write_handler() for transmit events.
 537  * File: src/sja1000p.c
 538  */
 539 void sja1000p_irq_write_handler(struct chip_t *chip, struct msgobj_t *obj)
 540 {
 541         int cmd;
 542
 543         if(obj->tx_slot){
 544                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 545                 obj->tx_slot=NULL;
 546         }
 547
 548         cmd=canque_test_outslot(obj->qends, &obj->tx_qedge, &obj->tx_slot);
 549         if(cmd<0)
 550                 return;
 551
 552         if (chip->chipspecops->pre_write_config(chip, obj, &obj->tx_slot->msg)) {
 553                 obj->ret = -1;
 554                 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_PREP);
 555                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 556                 obj->tx_slot=NULL;
 557                 return;
 558         }
 559         if (chip->chipspecops->send_msg(chip, obj, &obj->tx_slot->msg)) {
 560                 obj->ret = -1;
 561                 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_SEND);
 562                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 563                 obj->tx_slot=NULL;
 564                 return;
 565         }
 566
 567 }
 568
 569 #define MAX_RETR 10
 570
 571 /**
 572  * sja1000p_irq_handler: - interrupt service routine
 573  * @irq: interrupt vector number, this value is system specific
 574  * @dev_id: driver private pointer registered at time of request_irq() call.
 575  *      The CAN driver uses this pointer to store relationship of interrupt
 576  *      to chip state structure - @struct chip_t
 577  * @regs: system dependent value pointing to registers stored in exception frame
 578  *
 579  * Interrupt handler is activated when state of CAN controller chip changes,
 580  * there is message to be read or there is more space for new messages or
 581  * error occurs. The receive events results in reading of the message from
 582  * CAN controller chip and distribution of message through attached
 583  * message queues.
 584  * File: src/sja1000p.c
 585  */
 586 irqreturn_t sja1000p_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
 587 {
 588         int irq_register, status, error_code;
 589         int static retransmitted=0; /* FIXME - should go into chip struct */
 590         struct chip_t *chip=(struct chip_t *)dev_id;
 591         struct msgobj_t *obj=chip->msgobj[0];
 592
 593         irq_register=can_read_reg(chip,SJAIR);
 594 //      DEBUGMSG("sja1000_irq_handler: SJAIR:%02x\n",irq_register);
 595 //      DEBUGMSG("sja1000_irq_handler: SJASR:%02x\n",
 596 //                                      can_read_reg(chip,SJASR));
 597
 598         if ((irq_register & (IR_BEI|IR_EPI|IR_DOI|IR_EI|IR_TI|IR_RI)) == 0)
 599                 return IRQ_NONE;
 600
 601         if(!obj->flags & OBJ_BUFFERS_ALLOCATED) {
 602                 CANMSG("sja1000p_irq_handler: called with device closed, irq_register 0x%02x\n", irq_register);
 603                 return IRQ_NONE;
 604         }
 605
 606         if ((irq_register & IR_RI) != 0) {
 607                 DEBUGMSG("sja1000_irq_handler: RI\n");
 608                 sja1000p_read(chip,obj);
 609                 obj->ret = 0;
 610         }
 611         if ((irq_register & IR_TI) != 0) {
 612                 DEBUGMSG("sja1000_irq_handler: TI\n");
 613                 obj->ret = 0;
 614                 set_bit(OBJ_TX_REQUEST,&obj->flags);
 615                 while(!test_and_set_bit(OBJ_TX_LOCK,&obj->flags)){
 616                         clear_bit(OBJ_TX_REQUEST,&obj->flags);
 617
 618                         if (can_read_reg(chip, SJASR) & SR_TBS)
 619                                 sja1000p_irq_write_handler(chip, obj);
 620
 621                         clear_bit(OBJ_TX_LOCK,&obj->flags);
 622                         if(!test_bit(OBJ_TX_REQUEST,&obj->flags)) break;
 623                         DEBUGMSG("TX looping in sja1000_irq_handler\n");
 624                 }
 625         }
 626         if ((irq_register & (IR_EI|IR_BEI|IR_EPI|IR_DOI)) != 0) {
 627                 // Some error happened
 628                 status=can_read_reg(chip,SJASR);
 629                 error_code=can_read_reg(chip,SJAECC);
 630                 CANMSG("Error: status register: 0x%x irq_register: 0x%02x error: 0x%02x\n",
 631                         status, irq_register, error_code);
 632 // FIXME: chip should be brought to usable state. Transmission cancelled if in progress.
 633 // Reset flag set to 0 if chip is already off the bus. Full state report
 634                 obj->ret=-1;
 635
 636                 if(error_code == 0xd9) {
 637                         obj->ret= -ENXIO;
 638                         /* no such device or address - no ACK received */
 639                 }
 640                 if(retransmitted++>MAX_RETR) {
 641                         can_write_reg(chip, CMR_AT, SJACMR); // cancel any transmition
 642                         retransmitted = 0;
 643                 }
 644                 if(status&SR_BS) {
 645                         CANMSG("bus-off, resetting sja1000p\n");
 646                         can_write_reg(chip, 0, SJAMOD);
 647                 }
 648
 649                 if(obj->tx_slot){
 650                         canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_BUS);
 651                         /*canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 652                         obj->tx_slot=NULL;*/
 653                 }
 654
 655         } else {
 656                 retransmitted=0;
 657         }
 658
 659         return IRQ_HANDLED;
 660 }
 661
 662 /**
 663  * sja1000p_wakeup_tx: - wakeups TX processing
 664  * @chip: pointer to chip state structure
 665  * @obj: pointer to message object structure
 666  *
 667  * Return Value: negative value reports error.
 668  * File: src/sja1000p.c
 669  */
 670 int sja1000p_wakeup_tx(struct chip_t *chip, struct msgobj_t *obj)
 671 {
 672          /* dummy lock to prevent preemption fully portable way */
 673         spinlock_t dummy_lock;
 674
 675         /*  preempt_disable() */
 676         spin_lock_init(&dummy_lock);
 677         spin_lock(&dummy_lock);
 678
 679         set_bit(OBJ_TX_REQUEST,&obj->flags);
 680         while(!test_and_set_bit(OBJ_TX_LOCK,&obj->flags)){
 681                 clear_bit(OBJ_TX_REQUEST,&obj->flags);
 682
 683                 if (can_read_reg(chip, SJASR) & SR_TBS)
 684                         sja1000p_irq_write_handler(chip, obj);
 685
 686                 clear_bit(OBJ_TX_LOCK,&obj->flags);
 687                 if(!test_bit(OBJ_TX_REQUEST,&obj->flags)) break;
 688                 DEBUGMSG("TX looping in sja1000p_wakeup_tx\n");
 689         }
 690
 691         /* preempt_enable(); */
 692         spin_unlock(&dummy_lock);
 693         return 0;
 694 }
 695
 696 int sja1000p_register(struct chipspecops_t *chipspecops)
 697 {
 698         CANMSG("initializing sja1000p chip operations\n");
 699         chipspecops->chip_config=sja1000p_chip_config;
 700         chipspecops->baud_rate=sja1000p_baud_rate;
 701         chipspecops->standard_mask=sja1000p_standard_mask;
 702         chipspecops->extended_mask=sja1000p_extended_mask;
 703         chipspecops->message15_mask=sja1000p_extended_mask;
 704         chipspecops->clear_objects=sja1000p_clear_objects;
 705         chipspecops->config_irqs=sja1000p_config_irqs;
 706         chipspecops->pre_read_config=sja1000p_pre_read_config;
 707         chipspecops->pre_write_config=sja1000p_pre_write_config;
 708         chipspecops->send_msg=sja1000p_send_msg;
 709         chipspecops->check_tx_stat=sja1000p_check_tx_stat;
 710         chipspecops->wakeup_tx=sja1000p_wakeup_tx;
 711         chipspecops->remote_request=sja1000p_remote_request;
 712         chipspecops->enable_configuration=sja1000p_enable_configuration;
 713         chipspecops->disable_configuration=sja1000p_disable_configuration;
 714         chipspecops->set_btregs=sja1000p_set_btregs;
 715         chipspecops->start_chip=sja1000p_start_chip;
 716         chipspecops->stop_chip=sja1000p_stop_chip;
 717         chipspecops->irq_handler=sja1000p_irq_handler;
 718         return 0;
 719 }