1 /**************************************************************************/
2 /* File: sja1000.h - Philips/NXP SJA1000 chip legacy mode (deprecated) */
4 /* LinCAN - (Not only) Linux CAN bus driver */
5 /* Copyright (C) 2002-2009 DCE FEE CTU Prague <http://dce.felk.cvut.cz> */
6 /* Copyright (C) 2002-2009 Pavel Pisa <pisa@cmp.felk.cvut.cz> */
7 /* Funded by OCERA and FRESCOR IST projects */
8 /* Based on CAN driver code by Arnaud Westenberg <arnaud@wanadoo.nl> */
10 /* LinCAN is free software; you can redistribute it and/or modify it */
11 /* under terms of the GNU General Public License as published by the */
12 /* Free Software Foundation; either version 2, or (at your option) any */
13 /* later version. LinCAN is distributed in the hope that it will be */
14 /* useful, but WITHOUT ANY WARRANTY; without even the implied warranty */
15 /* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */
16 /* General Public License for more details. You should have received a */
17 /* copy of the GNU General Public License along with LinCAN; see file */
18 /* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, */
19 /* Cambridge, MA 02139, USA. */
21 /* To allow use of LinCAN in the compact embedded systems firmware */
22 /* and RT-executives (RTEMS for example), main authors agree with next */
23 /* special exception: */
25 /* Including LinCAN header files in a file, instantiating LinCAN generics */
26 /* or templates, or linking other files with LinCAN objects to produce */
27 /* an application image/executable, does not by itself cause the */
28 /* resulting application image/executable to be covered by */
29 /* the GNU General Public License. */
30 /* This exception does not however invalidate any other reasons */
31 /* why the executable file might be covered by the GNU Public License. */
32 /* Publication of enhanced or derived LinCAN files is required although. */
33 /**************************************************************************/
35 int sja1000_enable_configuration(struct canchip_t *chip);
36 int sja1000_disable_configuration(struct canchip_t *chip);
37 int sja1000_chip_config(struct canchip_t *chip);
38 int sja1000_standard_mask(struct canchip_t *chip, unsigned short code, unsigned short mask);
39 int sja1000_baud_rate(struct canchip_t *chip, int rate, int clock, int sjw,
40 int sampl_pt, int flags);
41 int sja1000_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj);
42 int sja1000_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
43 struct canmsg_t *msg);
44 int sja1000_send_msg(struct canchip_t *chip, struct msgobj_t *obj,
45 struct canmsg_t *msg);
46 int sja1000_check_tx_stat(struct canchip_t *chip);
47 int sja1000_set_btregs(struct canchip_t *chip, unsigned short btr0,
49 int sja1000_start_chip(struct canchip_t *chip);
50 int sja1000_stop_chip(struct canchip_t *chip);
51 int sja1000_irq_handler(int irq, struct canchip_t *chip);
52 int sja1000_fill_chipspecops(struct canchip_t *chip);
54 /* BasicCAN mode address map */
55 #define SJACR 0x00 /* Control register */
56 #define SJACMR 0x01 /* Command register */
57 #define SJASR 0x02 /* Status register */
58 #define SJAIR 0x03 /* Interrupt register */
59 #define SJAACR 0x04 /* Acceptance Code register */
60 #define SJAAMR 0x05 /* Acceptance Mask Register */
61 #define SJABTR0 0x06 /* Bus Timing register 0 */
62 #define SJABTR1 0x07 /* Bus Timing register 1 */
63 #define SJAOCR 0x08 /* Output Control register */
64 #define SJACDR 0x1f /* Clock Divider register */
66 #define SJATXID1 0x0a /* Identifier byte 1 */
67 #define SJATXID0 0x0b /* Identifier byte 0 */
68 #define SJATXDAT0 0x0c /* First data byte */
69 #define SJATXDAT1 0x0d
70 #define SJATXDAT2 0x0e
71 #define SJATDDAT3 0x0f
72 #define SJATXDAT4 0x10
73 #define SJATXDAT5 0x11
74 #define SJATXDAT6 0x12
75 #define SJATXDAT7 0x13
77 #define SJARXID1 0x14 /* Identifier byte 1 */
78 #define SJARXID0 0x15 /* Identifier byte 0 */
79 #define SJARXDAT0 0x16 /* First data byte */
80 #define SJARXDAT1 0x17
81 #define SJARXDAT2 0x18
82 #define SJARXDAT3 0x19
83 #define SJARXDAT4 0x1a
84 #define SJARXDAT5 0x1b
85 #define SJARXDAT6 0x1c
86 #define SJARXDAT7 0x1d
88 /* Command register */
89 enum sja1000_BASIC_CMR {
90 sjaCMR_TR = 1, // Transmission request
91 sjaCMR_AT = 1<<1, // Abort Transmission
92 sjaCMR_RRB = 1<<2, // Release Receive Buffer
93 sjaCMR_CDO = 1<<3, // Clear Data Overrun
94 sjaCMR_GTS = 1<<4 // Go To Sleep
98 enum sja1000_BASIC_SR {
99 sjaSR_RBS = 1, // Receive Buffer Status
100 sjaSR_DOS = 1<<1, // Data Overrun Status
101 sjaSR_TBS = 1<<2, // Transmit Buffer Status
102 sjaSR_TCS = 1<<3, // Transmission Complete Status
103 sjaSR_RS = 1<<4, // Receive Status
104 sjaSR_TS = 1<<5, // Transmit Status
105 sjaSR_ES = 1<<6, // Error Status
106 sjaSR_BS = 1<<7 // Bus Status
109 /* Control Register */
110 enum sja1000_BASIC_CR {
111 sjaCR_RR = 1, // Reset Request
112 sjaCR_RIE = 1<<1, // Receive Interrupt Enable
113 sjaCR_TIE = 1<<2, // Transmit Interrupt Enable
114 sjaCR_EIE = 1<<3, // Error Interrupt Enable
115 sjaCR_OIE = 1<<4 // Overrun Interrupt Enable
118 /* Interrupt (status) Register */
119 enum sja1000_BASIC_IR {
120 sjaIR_RI = 1, // Receive Interrupt
121 sjaIR_TI = 1<<1, // Transmit Interrupt
122 sjaIR_EI = 1<<2, // Error Interrupt
123 sjaIR_DOI = 1<<3, // Data Overrun Interrupt
124 sjaIR_WUI = 1<<4 // Wake-Up Interrupt
127 /* Clock Divider Register */
129 /* f_out = f_osc/(2*(CDR[2:0]+1)) or f_osc if CDR[2:0]==7 */
130 sjaCDR_CLKOUT_DIV1 = 7,
131 sjaCDR_CLKOUT_DIV2 = 0,
132 sjaCDR_CLKOUT_DIV4 = 1,
133 sjaCDR_CLKOUT_DIV6 = 2,
134 sjaCDR_CLKOUT_DIV8 = 3,
135 sjaCDR_CLKOUT_DIV10 = 4,
136 sjaCDR_CLKOUT_DIV12 = 5,
137 sjaCDR_CLKOUT_DIV14 = 6,
138 sjaCDR_CLKOUT_MASK = 7,
139 sjaCDR_CLK_OFF = 1<<3, // Clock Off
140 sjaCDR_RXINPEN = 1<<5, // TX1 output is RX irq output
141 sjaCDR_CBP = 1<<6, // Input Comparator By-Pass
142 sjaCDR_PELICAN = 1<<7 // PeliCAN Mode
145 /* Output Control Register */
147 sjaOCR_MODE_BIPHASE = 0,
148 sjaOCR_MODE_TEST = 1,
149 sjaOCR_MODE_NORMAL = 2,
150 sjaOCR_MODE_CLOCK = 3,
151 // TX0 push-pull not inverted
152 sjaOCR_TX0_LH = 0x18,
153 // TX0 push-pull inverted
154 sjaOCR_TX0_HL = 0x1c,
155 // TX1 floating (off)
157 // TX1 pull-down not inverted
161 /** Frame format information 0x11 */
162 enum sja1000_BASIC_ID0 {
163 sjaID0_RTR = 1<<4, // Remote request
164 sjaID0_DLC_M = (1<<4)-1 // Length Mask