2 * Header file for the Linux CAN-bus driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
5 * email:pisa@cmp.felk.cvut.cz
6 * This software is released under the GPL-License.
7 * Version lincan-0.2 9 Jul 2003
12 #include <linux/version.h>
13 #include <linux/wait.h>
14 #include <linux/interrupt.h>
16 #include "./constants.h"
17 #include "./can_queue.h"
20 #define DEBUGMSG(fmt,args...) printk(KERN_ERR "can.o (debug): " fmt,\
23 #define DEBUGMSG(fmt,args...)
26 #define CANMSG(fmt,args...) printk(KERN_ERR "can.o: " fmt,##args)
28 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,7))
31 (MINOR(file->f_dentry->d_inode->i_rdev))
33 #else /* Linux kernel > 2.5.7 */
36 (minor(file->f_dentry->d_inode->i_rdev))
37 #endif /* Linux kernel > 2.5.7 */
39 #if ((LINUX_VERSION_CODE < KERNEL_VERSION(2,5,68)) && !defined(IRQ_RETVAL))
40 typedef void irqreturn_t;
47 * struct canhardware_t - structure representing pointers to all CAN boards
48 * @nr_boards: number of present boards
49 * @rtr_queue: RTR - remote transmission request queue (expect some changes there)
50 * @rtr_lock: locking for RTR queue
51 * @candevice: array of pointers to CAN devices/boards
53 struct canhardware_t {
55 struct rtr_id *rtr_queue;
57 struct candevice_t *candevice[MAX_HW_CARDS];
61 * struct candevice_t - CAN device/board structure
62 * @hwname: text string with board type
63 * @candev_idx: board index in canhardware_t.candevice[]
64 * @io_addr: IO/physical MEM address
65 * @res_addr: optional reset register port
66 * @dev_base_addr: CPU translated IO/virtual MEM address
67 * @flags: board flags: %PROGRAMMABLE_IRQ .. interrupt number
68 * can be programmed into board
69 * @nr_all_chips: number of chips present on the board
70 * @nr_82527_chips: number of Intel 8257 chips
71 * @nr_sja1000_chips: number of Philips SJA100 chips
72 * @chip: array of pointers to the chip structures
73 * @hwspecops: pointer to board specific operations
74 * @hosthardware_p: pointer to the root hardware structure
76 * The structure represent configuration and state of associated board.
77 * The driver infrastructure prepares this structure and calls
78 * board type specific board_register() function. The board support provided
79 * register function fills right function pointers in @hwspecops structure.
80 * Then driver setup calls functions init_hw_data(), init_chip_data(),
81 * init_chip_data(), init_obj_data() and program_irq(). Function init_hw_data()
82 * and init_chip_data() have to specify number and types of connected chips
83 * or objects respectively.
84 * The use of @nr_all_chips is preferred over use of fields @nr_82527_chips
85 * and @nr_sja1000_chips in the board non-specific functions.
86 * The @io_addr and @dev_base_addr is filled from module parameters
87 * to the same value. The request_io function can fix-up @dev_base_addr
88 * field if virtual address is different than bus address.
91 char *hwname; /* text board type */
92 int candev_idx; /* board index in canhardware_t.candevice[] */
93 unsigned long io_addr; /* IO/physical MEM address */
94 unsigned long res_addr; /* optional seset register port */
95 unsigned long dev_base_addr; /* CPU translated IO/virtual MEM address */
100 struct chip_t *chip[MAX_HW_CHIPS];
102 struct hwspecops_t *hwspecops;
104 struct canhardware_t *hosthardware_p;
108 * struct chip_t - CAN chip state and type information
109 * @chip_type: text string describing chip type
110 * @chip_idx: index of the chip in candevice_t.chip[] array
111 * @chip_irq: chip interrupt number if any
112 * @chip_base_addr: chip base address in the CPU IO or virtual memory space
113 * @flags: chip flags: %CHIP_CONFIGURED .. chip is configured,
114 * %CHIP_SEGMENTED .. access to the chip is segmented (mainly for i82527 chips)
115 * @clock: chip base clock frequency in Hz
116 * @write_register: write chip register function copy -
117 * @read_register: read chip register function copy
118 * @sja_cdr_reg: SJA specific register -
119 * holds hardware specific options for the Clock Divider
120 * register. Options defined in the sja1000.h file:
121 * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
122 * @sja_ocr_reg: SJA specific register -
123 * hold hardware specific options for the Output Control
124 * register. Options defined in the sja1000.h file:
125 * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
126 * %OCR_TX0_LH, %OCR_TX1_ZZ.
127 * @int_cpu_reg: Intel specific register -
128 * holds hardware specific options for the CPU Interface
129 * register. Options defined in the i82527.h file:
130 * %iCPU_CEN, %iCPU_MUX, %iCPU_SLP, %iCPU_PWD, %iCPU_DMC, %iCPU_DSC, %iCPU_RST.
131 * @int_clk_reg: Intel specific register -
132 * holds hardware specific options for the Clock Out
133 * register. Options defined in the i82527.h file:
134 * %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
135 * @int_bus_reg: Intel specific register -
136 * holds hardware specific options for the Bus Configuration
137 * register. Options defined in the i82527.h file:
138 * %iBUS_DR0, %iBUS_DR1, %iBUS_DT1, %iBUS_POL, %iBUS_CBY.
139 * @msgobj: array of pointers to individual communication objects
140 * @chipspecops: pointer to the set of chip specific object filled by init_chip_data() function
141 * @hostdevice: pointer to chip hosting board
142 * @max_objects: maximal number of communication objects connected to this chip
144 * The fields @write_register and @read_register are copied from
145 * corresponding fields from @hwspecops structure
146 * (chip->hostdevice->hwspecops->write_register and
147 * chip->hostdevice->hwspecops->read_register)
148 * to speedup can_write_reg() and can_read_reg() functions.
152 int chip_idx; /* chip index in candevice_t.chip[] */
154 unsigned long chip_base_addr;
156 int clock; /* Chip clock in Hz */
158 void (*write_register)(unsigned char data,unsigned long address);
159 unsigned (*read_register)(unsigned long address);
161 unsigned short sja_cdr_reg; /* sja1000 only! */
162 unsigned short sja_ocr_reg; /* sja1000 only! */
163 unsigned short int_cpu_reg; /* intel 82527 only! */
164 unsigned short int_clk_reg; /* intel 82527 only! */
165 unsigned short int_bus_reg; /* intel 82527 only! */
167 struct msgobj_t *msgobj[MAX_MSGOBJS];
169 struct chipspecops_t *chipspecops;
171 struct candevice_t *hostdevice;
173 int max_objects; /* 1 for sja1000, 15 for */
177 * struct msgobj_t - structure holding communication object state
179 * @minor: associated device minor number
180 * @object: object number in chip_t structure +1
181 * @flags: message object flags
182 * @ret: field holding status of the last Tx operation
183 * @qends: pointer to message object corresponding ends structure
184 * @tx_qedge: edge corresponding to transmitted message
185 * @tx_slot: slot holding transmitted message, slot is taken from
186 * canque_test_outslot() call and is freed by canque_free_outslot()
187 * or rescheduled canque_again_outslot()
188 * @rx_msg: temporary storage to hold received messages before
189 * calling to canque_filter_msg2edges()
190 * @hostchip: pointer to the &chip_t structure this object belongs to
191 * @obj_used: counter of users (associated file structures for Linux
192 * userspace clients) of this object
193 * @obj_users: list of user structures of type &canuser_t.
196 unsigned long obj_base_addr;
197 unsigned int minor; /* associated device minor number */
198 unsigned int object; /* object number in chip_t +1 for debug printk */
202 struct canque_ends_t *qends;
203 struct canque_edge_t *tx_qedge;
204 struct canque_slot_t *tx_slot;
205 struct canmsg_t rx_msg;
207 struct chip_t *hostchip;
210 struct list_head obj_users;
213 #define CAN_USER_MAGIC 0x05402033
216 * struct canuser_t - structure holding CAN user/client state
217 * @peers: for connection into list of object users
218 * @qends: pointer to the ends structure corresponding for this user
219 * @file: pointer to open device file state structure
220 * @msgobj: communication object the user is connected to
221 * @rx_edge0: default receive queue for filter IOCTL
222 * @magic: magic number to check consistency when pointer is retrieved
223 * from file private field
226 struct list_head peers;
227 struct canque_ends_t *qends;
228 struct file *file; /* back ptr to file */
229 struct msgobj_t *msgobj;
230 struct canque_edge_t *rx_edge0; /* simplifies IOCTL */
235 * struct hwspecops_t - hardware/board specific operations
236 * @request_io: reserve io or memory range for can board
237 * @release_io: free reserved io memory range
238 * @reset: hardware reset routine
239 * @init_hw_data: called to initialize &candevice_t structure, mainly
240 * @res_add, @nr_all_chips, @nr_82527_chips, @nr_sja1000_chips
242 * @init_chip_data: called initialize each &chip_t structure, mainly
243 * @chip_type, @chip_base_addr, @clock and chip specific registers.
244 * It is responsible to setup &chip_t->@chipspecops functions
245 * for non-standard chip types (type other than "i82527", "sja1000" or "sja1000p")
246 * @init_obj_data: called initialize each &msgobj_t structure,
247 * mainly @obj_base_addr field.
248 * @program_irq: program interrupt generation hardware of the board
249 * if flag %PROGRAMMABLE_IRQ is present for specified device/board
250 * @write_register: low level write register routine
251 * @read_register: low level read register routine
254 int (*request_io)(struct candevice_t *candev);
255 int (*release_io)(struct candevice_t *candev);
256 int (*reset)(struct candevice_t *candev);
257 int (*init_hw_data)(struct candevice_t *candev);
258 int (*init_chip_data)(struct candevice_t *candev, int chipnr);
259 int (*init_obj_data)(struct chip_t *chip, int objnr);
260 int (*program_irq)(struct candevice_t *candev);
261 void (*write_register)(unsigned char data,unsigned long address);
262 unsigned (*read_register)(unsigned long address);
266 * struct chipspecops_t - can controller chip specific operations
267 * @chip_config: CAN chip configuration
268 * @baud_rate: set communication parameters
269 * @standard_mask: setup of mask for message filtering
270 * @extended_mask: setup of extended mask for message filtering
271 * @message15_mask: set mask of i82527 message object 15
272 * @clear_objects: clears state of all message object residing in chip
273 * @config_irqs: tunes chip hardware interrupt delivery
274 * @pre_read_config: prepares message object for message reception
275 * @pre_write_config: prepares message object for message transmission
276 * @send_msg: initiate message transmission
277 * @remote_request: configures message object and asks for RTR message
278 * @check_tx_stat: checks state of transmission engine
279 * @wakeup_tx: wakeup TX processing
280 * @enable_configuration: enable chip configuration mode
281 * @disable_configuration: disable chip configuration mode
282 * @set_btregs: configures bitrate registers
283 * @start_chip: starts chip message processing
284 * @stop_chip: stops chip message processing
285 * @irq_handler: interrupt service routine
287 struct chipspecops_t {
288 int (*chip_config)(struct chip_t *chip);
289 int (*baud_rate)(struct chip_t *chip, int rate, int clock, int sjw,
290 int sampl_pt, int flags);
291 int (*standard_mask)(struct chip_t *chip, unsigned short code,
292 unsigned short mask);
293 int (*extended_mask)(struct chip_t *chip, unsigned long code,
295 int (*message15_mask)(struct chip_t *chip, unsigned long code,
297 int (*clear_objects)(struct chip_t *chip);
298 int (*config_irqs)(struct chip_t *chip, short irqs);
299 int (*pre_read_config)(struct chip_t *chip, struct msgobj_t *obj);
300 int (*pre_write_config)(struct chip_t *chip, struct msgobj_t *obj,
301 struct canmsg_t *msg);
302 int (*send_msg)(struct chip_t *chip, struct msgobj_t *obj,
303 struct canmsg_t *msg);
304 int (*remote_request)(struct chip_t *chip, struct msgobj_t *obj);
305 int (*check_tx_stat)(struct chip_t *chip);
306 int (*wakeup_tx)(struct chip_t *chip, struct msgobj_t *obj);
307 int (*enable_configuration)(struct chip_t *chip);
308 int (*disable_configuration)(struct chip_t *chip);
309 int (*set_btregs)(struct chip_t *chip, unsigned short btr0,
310 unsigned short btr1);
311 int (*start_chip)(struct chip_t *chip);
312 int (*stop_chip)(struct chip_t *chip);
313 irqreturn_t (*irq_handler)(int irq, void *dev_id, struct pt_regs *regs);
318 struct mem_addr *next;
321 /* Structure for the RTR queue */
324 struct canmsg_t *rtr_message;
325 wait_queue_head_t rtr_wq;
330 extern int minor[MAX_TOT_CHIPS];
333 extern char *hw[MAX_HW_CARDS];
334 extern int irq[MAX_IRQ];
335 extern unsigned long io[MAX_HW_CARDS];
337 extern struct canhardware_t *hardware_p;
338 extern struct chip_t *chips_p[MAX_TOT_CHIPS];
339 extern struct msgobj_t *objects_p[MAX_TOT_MSGOBJS];
341 extern struct mem_addr *mem_head;
343 /* Inline function to write to the hardware registers. The argument address is
344 * relative to the memory map of the chip and not the absolute memory address.
346 extern inline void can_write_reg(const struct chip_t *chip, unsigned char data, unsigned address)
348 unsigned long address_to_write;
349 address_to_write = chip->chip_base_addr+address;
350 chip->write_register(data, address_to_write);
353 extern inline unsigned can_read_reg(const struct chip_t *chip, unsigned address)
355 unsigned long address_to_read;
356 address_to_read = chip->chip_base_addr+address;
357 return chip->read_register(address_to_read);
360 extern inline void canobj_write_reg(const struct chip_t *chip, const struct msgobj_t *obj,
361 unsigned char data, unsigned address)
363 unsigned long address_to_write;
364 address_to_write = obj->obj_base_addr+address;
365 chip->write_register(data, address_to_write);
368 extern inline unsigned canobj_read_reg(const struct chip_t *chip, const struct msgobj_t *obj,
371 unsigned long address_to_read;
372 address_to_read = obj->obj_base_addr+address;
373 return chip->read_register(address_to_read);
376 int can_base_addr_fixup(struct candevice_t *candev, unsigned long new_base);
377 int can_request_io_region(unsigned long start, unsigned long n, const char *name);
378 void can_release_io_region(unsigned long start, unsigned long n);
379 int can_request_mem_region(unsigned long start, unsigned long n, const char *name);
380 void can_release_mem_region(unsigned long start, unsigned long n);
383 const char *boardtype;
384 int (*board_register)(struct hwspecops_t *hwspecops);
388 const struct boardtype_t* boardtype_find(const char *str);