4 * Header file for the Linux CAN-bus driver.
5 * Written by Sergei Sharonov sharonov@halliburton.com
6 * sja1000p was used as a prototype
7 * This software is released under the GPL-License.
8 * Version lincan-0.3 Feb 2006
11 // Fixup for old kernels - always defined for 2.6
13 #define container_of(ptr, type, member) ({ \
14 const typeof( ((type *)0)->member ) *__mptr = (ptr); \
15 (type *)( (char *)__mptr - offsetof(type,member) );})
19 int mcp2515_chip_config(struct canchip_t *chip);
20 int mcp2515_extended_mask(struct canchip_t *chip, unsigned long code, unsigned long mask);
21 int mcp2515_baud_rate(struct canchip_t *chip, int rate, int clock, int sjw,
22 int sampl_pt, int flags);
23 int mcp2515_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj);
24 int mcp2515_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
25 struct canmsg_t *msg);
26 int mcp2515_send_msg(struct canchip_t *chip, struct msgobj_t *obj,
27 struct canmsg_t *msg);
28 int mcp2515_fill_chipspecops(struct canchip_t *chip);
29 int mcp2515_irq_handler(int irq, struct canchip_t *chip);
31 int mcp2515_disp(char *buf, char **start, off_t offset,
32 int count, int *eof, void *data);
43 } __attribute__((packed)) MCP2515_FRAME;
45 #define SPI_BUF_LEN 16 /* 13+2 bytes max transfer len, 1 spare */
59 #define MCP2515_STATUS_SHUTDOWN (1)
60 #define MCP2515_TXBUF_NUM (3)
63 struct canchip_t *chip;
65 uint8_t spi_buf[SPI_BUF_LEN];
66 struct work_struct workqueue_handler;
67 struct tasklet_struct tasklet_handler;
69 struct work_struct txwq_handler;
70 DECLARE_BITMAP(txfree, MCP2515_TXBUF_NUM);
72 MCP2515_ERRCNT errcnt;
80 /// TXBnCTRL - TRANSMIT BUFFER n CONTROL REGISTERS
81 MCP2515_TXB0CTRL = 0x30,
82 MCP2515_TXB1CTRL = 0x40,
83 MCP2515_TXB2CTRL = 0x50,
85 /// TXRTSCTRL - TXnRTS PIN CONTROL AND STATUS REGISTER
86 MCP2515_TXRTSCTRL = 0x0d,
88 /// TXBnSIDH - TRANSMIT BUFFER n STANDARD IDENTIFIER HIGH
89 MCP2515_TXB0SIDH = 0x31,
90 MCP2515_TXB1SIDH = 0x41,
91 MCP2515_TXB2SIDH = 0x51,
93 /// TXBnSIDL - TRANSMIT BUFFER n STANDARD IDENTIFIER LOW
94 MCP2515_TXB0SIDL = 0x32,
95 MCP2515_TXB1SIDL = 0x42,
96 MCP2515_TXB2SIDL = 0x52,
98 /// TXBnEID8 - TRANSMIT BUFFER n EXTENDED IDENTIFIER HIGH
99 MCP2515_TXB0EID8 = 0x33,
100 MCP2515_TXB1EID8 = 0x43,
101 MCP2515_TXB2EID8 = 0x53,
103 /// TXBnEID0 - TRANSMIT BUFFER n EXTENDED IDENTIFIER LOW
104 MCP2515_TXB0EID0 = 0x34,
105 MCP2515_TXB1EID0 = 0x44,
106 MCP2515_TXB2EID0 = 0x54,
108 /// TXBnDLC - TRANSMIT BUFFER n DATA LENGTH CODE
109 MCP2515_TXB0DLC = 0x35,
110 MCP2515_TXB1DLC = 0x45,
111 MCP2515_TXB2DLC = 0x55,
113 /// TXBnDm - TRANSMIT BUFFER n DATA
114 MCP2515_TXB0DATA = 0x36, /* 0x36-0x3d */
115 MCP2515_TXB1DATA = 0x46, /* 0x46-0x4d */
116 MCP2515_TXB2DATA = 0x56, /* 0x56-0x5d */
118 /// RXB0CTRL - RECEIVE BUFFER CONTROL
119 MCP2515_RXB0CTRL = 0x60,
120 MCP2515_RXB1CTRL = 0x70,
122 /// BFPCTRL - RXnBF PIN CONTROL AND STATUS
123 MCP2515_BFPCTRL = 0x0c,
125 /// RXBnSIDH - RECEIVE BUFFER n STANDARD IDENTIFIER HIGH
126 MCP2515_RXB0SIDH = 0x61,
127 MCP2515_RXB1SIDH = 0x71,
129 /// RXBnSIDL - RECEIVE BUFFER n STANDARD IDENTIFIER LOW
130 MCP2515_RXB0SIDL = 0x62,
131 MCP2515_RXB1SIDL = 0x72,
133 /// RXBnEID8 - RECEIVE BUFFER n EXTENDED IDENTIFIER HIGH
134 MCP2515_RXB0EID8 = 63,
135 MCP2515_RXB1EID8 = 73,
137 /// RXBnEID0 - RECEIVE BUFFER n EXTENDED IDENTIFIER LOW
138 MCP2515_RXB0EID0 = 64,
139 MCP2515_RXB1EID0 = 74,
141 /// RXBnDLC - RECEIVE BUFFER n DATA LENGHT CODE
142 MCP2515_RXB0DLC = 65,
143 MCP2515_RXB1DLC = 75,
145 /// RXBnDM - RECEIVE BUFFER n DATA
146 MCP2515_RXB0DATA = 0x66, /* 0x66-0x6d */
147 MCP2515_RXB1DATA = 0x76, /* 0x76-0x7d */
149 /// RXFnSIDH - FILTER n STANDARD IDENTIFIER HIGH
150 MCP2515_RXF0SIDH = 0x00,
151 MCP2515_RXF1SIDH = 0x04,
152 MCP2515_RXF2SIDH = 0x08,
153 MCP2515_RXF3SIDH = 0x10,
154 MCP2515_RXF4SIDH = 0x14,
155 MCP2515_RXF5SIDH = 0x18,
157 /// RXFnSIDL - FILTER n STANDARD IDENTIFIER LOW
158 MCP2515_RXF0SIDL = 0x01,
159 MCP2515_RXF1SIDL = 0x05,
160 MCP2515_RXF2SIDL = 0x09,
161 MCP2515_RXF3SIDL = 0x11,
162 MCP2515_RXF4SIDL = 0x15,
163 MCP2515_RXF5SIDL = 0x19,
165 /// RXFnEID8 - FILTER n EXTENDED IDENTIFIER HIGH
166 MCP2515_RXF0EID8 = 0x02,
167 MCP2515_RXF1EID8 = 0x06,
168 MCP2515_RXF2EID8 = 0x0a,
169 MCP2515_RXF3EID8 = 0x12,
170 MCP2515_RXF4EID8 = 0x16,
171 MCP2515_RXF5EID8 = 0x1a,
173 /// RXFnEID0 - FILTER n EXTENDED IDENTIFIER LOW
174 MCP2515_RXF0EID0 = 0x03,
175 MCP2515_RXF1EID0 = 0x07,
176 MCP2515_RXF2EID0 = 0x0b,
177 MCP2515_RXF3EID0 = 0x13,
178 MCP2515_RXF4EID0 = 0x17,
179 MCP2515_RXF5EID0 = 0x1b,
181 /// RXMnSIDH - MASK n STANDARD IDENTIFIER HIGH
182 MCP2515_RXM0SIDH = 0x20,
183 MCP2515_RXM1SIDH = 0x24,
185 /// RXMnSIDL - MASK n STANDARD IDENTIFIER LOW
186 MCP2515_RXM0SIDL = 0x21,
187 MCP2515_RXM1SIDL = 0x25,
189 /// RXMnEID8 - MASK n EXTENDED IDENTIFIER HIGH
190 MCP2515_RXM0EID8 = 0x22,
191 MCP2515_RXM1EID8 = 0x26,
193 /// RXMnEID0 - MASK n EXTENDED IDENTIFIER LOW
194 MCP2515_RXM0EID0 = 0x23,
195 MCP2515_RXM1EID0 = 0x27,
197 /// CNFn - CONFIGURATION REGS
202 /// TEC - TRANSMIT ERROR COUNTER
205 /// REC - RECEIVER ERROR COUNTER
208 /// EFLG - ERROR FLAG
211 /// CANINTE - INTERRUPT ENABLE
212 MCP2515_CANINTE = 0x2b,
214 /// CANINTF - INTERRUPT FLAG
215 MCP2515_CANINTF = 0x2c,
217 /// CANCTRL - CAN CONTROL REGISTER
218 MCP2515_CANCTRL = 0x0f,
220 /// CANSTAT - CAN STATUS REGISTER
221 MCP2515_CANSTAT = 0x0e
225 /** Mode Register Bits */
227 mcpMOD_NORM = 0<<5, // Normal Operation Mode
228 mcpMOD_SLEEP = 1<<5, // Sleep Mode
229 mcpMOD_LOOPBACK = 2<<5, // Loopback Mode
230 mcpMOD_LISTEN = 3<<5, // Listen-only Mode
231 mcpMOD_CONFIG = 4<<5, // Configuration Mode
232 mcpMOD_MASK = 7<<5 // Mask for mod bits
235 /* BFPCTRL - RXnBF PIN CONTROL AND STATUS */
244 enum mcp2515_RXBSIDL {
250 enum mcp2515_RXBDLC {
256 enum mcp2515_RXB0CTRL {
273 enum mcp2515_TXBCTRL {
280 enum mcp2515_TXBSIDL {
296 /* Error flags EFLG */