1 /**************************************************************************/
2 /* File: nsi_canpci.c - NSI CAN PCI card (2xi82527) */
4 /* LinCAN - (Not only) Linux CAN bus driver */
5 /* Copyright (C) 2002-2009 DCE FEE CTU Prague <http://dce.felk.cvut.cz> */
6 /* Copyright (C) 2002-2009 Pavel Pisa <pisa@cmp.felk.cvut.cz> */
7 /* Copyright (C) 2004 Eric Pennamen <pennamen@gmail.com> */
8 /* Funded by OCERA and FRESCOR IST projects */
9 /* Based on CAN driver code by Arnaud Westenberg <arnaud@wanadoo.nl> */
10 /* and Ake Hedman, eurosource <akhe@eurosource.se> */
12 /* LinCAN is free software; you can redistribute it and/or modify it */
13 /* under terms of the GNU General Public License as published by the */
14 /* Free Software Foundation; either version 2, or (at your option) any */
15 /* later version. LinCAN is distributed in the hope that it will be */
16 /* useful, but WITHOUT ANY WARRANTY; without even the implied warranty */
17 /* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */
18 /* General Public License for more details. You should have received a */
19 /* copy of the GNU General Public License along with LinCAN; see file */
20 /* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, */
21 /* Cambridge, MA 02139, USA. */
23 /* To allow use of LinCAN in the compact embedded systems firmware */
24 /* and RT-executives (RTEMS for example), main authors agree with next */
25 /* special exception: */
27 /* Including LinCAN header files in a file, instantiating LinCAN generics */
28 /* or templates, or linking other files with LinCAN objects to produce */
29 /* an application image/executable, does not by itself cause the */
30 /* resulting application image/executable to be covered by */
31 /* the GNU General Public License. */
32 /* This exception does not however invalidate any other reasons */
33 /* why the executable file might be covered by the GNU Public License. */
34 /* Publication of enhanced or derived LinCAN files is required although. */
35 /**************************************************************************/
37 #include "../include/can.h"
38 #include "../include/can_sysdep.h"
39 #include "../include/main.h"
40 #include "../include/nsi_canpci.h"
41 #include "../include/i82527.h"
47 #define __NO_VERSION__
48 #include <linux/module.h>
50 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10))
51 #define ioread32 can_readl
52 #define iowrite32 can_writel
53 #define ioread8 can_readb
54 #define iowrite8 can_writeb
60 #define INT_CONF 0x00000040 /* value for register INTCSR of PLX */
61 #define NSI_VENDOR_ID 0x1637
62 #define NSI_CANPCI_DEVICE_ID 0x0001
64 enum PORT2 { P2_0=1, P2_1=1<<1, P2_2=1<<2, P2_3=1<<3, P2_4=1<<4, P2_5=1<<5, P2_6=1<<6, P2_7=1<<7 };
66 /*PLX register definition */
67 #define PLX_CNTRL 0x50 /* Controle register */
68 #define PLX_INTCSR 0x4C /* Interruption controle register */
70 /* This value define the i82527 clock frequency */
71 #define iCLOCK 16000000
74 /* Il faut reserver 4 zones:
75 * BAR0: 128 octets memoire (32bits) pour les registres du PLX9052
76 * BAR1: 128 octets I/O pour les registres du PLX9052
77 * BAR2: 256 octets memoire(8bits) pour les registres du PLX9052
78 * BAR3: 256 octets memoire(8bits) pour les registres du PLX9052
80 /* Variables globales contenant les @ des IO-Memory apres remap */
81 #define NB_VALID_BAR 4
84 void* addr_BAR_remap[NB_VALID_BAR];
87 void nsi_canpci_connect_irq(struct candevice_t *candev)
91 void nsi_canpci_disconnect_irq(struct candevice_t *candev)
93 //on disconnecting interrupt we need to disable interruption form PLX
94 iowrite32(0x0,(void*)(candev->io_addr+PLX_INTCSR));
95 DEBUGMSG("PLX interrupt disabled\n");
98 int nsi_canpci_config_irqs(struct canchip_t *chip, short irqs)
101 unsigned long it_mask,it_reg;
102 struct candevice_t *candev;
104 DEBUGMSG("Configuring NSI CANPCI interrupt\n");
105 can_write_reg(chip,irqs,iCTL);
107 {//At least one interrupt source requested
108 if(chip->chip_idx==0)
110 DEBUGMSG("starting interrupt on chip 0\n");
115 DEBUGMSG("starting interrupt on chip 1\n");
118 candev=chip->hostdevice;
119 it_reg = ioread32( (void*)(candev->io_addr+PLX_INTCSR));
120 it_reg|=it_mask|0x40;
121 iowrite32(it_reg,(void*)(candev->io_addr+PLX_INTCSR));
124 {//No more interrupt source
125 if(chip->chip_idx==0)
127 DEBUGMSG("stoping interrupt on chip 0\n");
132 DEBUGMSG("stoping interrupt on chip 1\n");
135 candev=chip->hostdevice;
136 it_reg = ioread32( (void*)(candev->io_addr+PLX_INTCSR));
138 iowrite32(it_reg,(void*)(candev->io_addr+PLX_INTCSR));
143 int nsi_canpci_i82527_chip_config(struct canchip_t *chip)
145 can_write_reg(chip,chip->int_cpu_reg,iCPU); // Configure cpu interface
146 can_write_reg(chip,(iCTL_CCE|iCTL_INI),iCTL); // Enable configuration
147 i82527_seg_write_reg(chip,chip->int_clk_reg,iCLK); // Set clock out slew rates
148 i82527_seg_write_reg(chip,chip->int_bus_reg,iBUS); /* Bus configuration */
150 can_write_reg(chip,P2_2|P2_1,iP2C); // The pin P2_2,P2_1 of the 527 must be set as output
151 can_write_reg(chip,P2_2|P2_1,iP2O); // and P2_2 must be set to 1
153 can_write_reg(chip,0x00,iSTAT); /* Clear error status register */
155 /* Check if we can at least read back some arbitrary data from the
156 * card. If we can not, the card is not properly configured!
158 canobj_write_reg(chip,chip->msgobj[1],0x25,iMSGDAT1);
159 canobj_write_reg(chip,chip->msgobj[2],0x52,iMSGDAT3);
160 canobj_write_reg(chip,chip->msgobj[10],0xc3,iMSGDAT6);
161 if ( (canobj_read_reg(chip,chip->msgobj[1],iMSGDAT1) != 0x25) ||
162 (canobj_read_reg(chip,chip->msgobj[2],iMSGDAT3) != 0x52) ||
163 (canobj_read_reg(chip,chip->msgobj[10],iMSGDAT6) != 0xc3) ) {
164 CANMSG("Could not read back from the hardware.\n");
165 CANMSG("This probably means that your hardware is not correctly configured!\n");
169 DEBUGMSG("Could read back, hardware is probably configured correctly\n");
171 if (chip->baudrate == 0)
172 chip->baudrate=1600000;
174 if (i82527_baud_rate(chip,chip->baudrate,chip->clock,0,75,0)) {
175 CANMSG("Error configuring baud rate\n");
178 if (i82527_standard_mask(chip,0x0000,stdmask)) {
179 CANMSG("Error configuring standard mask\n");
182 if (i82527_extended_mask(chip,0x00000000,extmask)) {
183 CANMSG("Error configuring extended mask\n");
186 if (i82527_message15_mask(chip,0x00000000,mo15mask)) {
187 CANMSG("Error configuring message 15 mask\n");
190 if (i82527_clear_objects(chip)) {
191 CANMSG("Error clearing message objects\n");
195 if (nsi_canpci_config_irqs(chip,iCTL_IE|iCTL_EIE)) { /* has been 0x0a */
196 CANMSG("Error configuring interrupts\n");
203 int nsi_canpci_start_chip(struct canchip_t *chip)
205 unsigned long it_mask,it_reg;
206 struct candevice_t *candev;
208 if(chip->chip_idx==0)
210 DEBUGMSG("starting chip 0\n");
215 DEBUGMSG("starting chip 1\n");
218 candev=chip->hostdevice;
219 it_reg = ioread32( (void*)(candev->io_addr+PLX_INTCSR));
221 it_reg|=it_mask|0x40;
222 iowrite32(it_reg,(void*)(candev->io_addr+PLX_INTCSR));
224 i82527_start_chip(chip);
228 int nsi_canpci_stop_chip(struct canchip_t *chip)
230 unsigned long it_mask,it_reg;
231 struct candevice_t *candev;
233 if(chip->chip_idx==0)
235 DEBUGMSG("stoping chip 0\n");
240 DEBUGMSG("stoping chip 1\n");
243 candev=chip->hostdevice;
244 it_reg = ioread32( (void*)(candev->io_addr+PLX_INTCSR));
247 iowrite32(it_reg,(void*)(candev->io_addr+PLX_INTCSR));
249 i82527_stop_chip(chip);
253 int nsi_canpci_irq_handler(int irq, struct canchip_t *chip)
256 unsigned long it_reg;
257 struct candevice_t *candev;
258 candev=chip->hostdevice;
259 retcode = CANCHIP_IRQ_NONE;
260 it_reg = ioread32( (void*)(candev->io_addr+PLX_INTCSR));
262 if(chip->chip_idx==0)
264 if((it_reg &0x4)!=0) //interrupt active
266 if(i82527_irq_handler(irq,chip)==CANCHIP_IRQ_NONE)
267 {//some trouble with IT
269 CANMSG("Unexcepted interruption from canal0, interruption is canceled\n");
273 retcode=CANCHIP_IRQ_HANDLED;
280 if((it_reg &0x20)!=0) //interrupt is set
282 if(i82527_irq_handler(irq,chip)==CANCHIP_IRQ_NONE)
283 {//soucis avec les IT
285 CANMSG("Unexcepted interruption from canal1, interruption is canceled\n");
288 retcode=CANCHIP_IRQ_HANDLED;
295 /* The function template_request_io is used to reserve the io-memory. If your
296 * hardware uses a dedicated memory range as hardware control registers you
297 * will have to add the code to reserve this memory as well.
298 * The reserved memory starts at candev->io_addr, wich is the module parameter io.
300 int nsi_canpci_request_io(struct candevice_t *candev)
303 if(candev->dev_base_addr==0)
308 /* The function template_release_io is used to free the previously reserved
309 * io-memory. In case you reserved more memory, don't forget to free it here.
311 int nsi_canpci_release_io(struct candevice_t *candev)
313 unsigned long reg_reset;
314 struct pci_dev *pcidev = candev->sysdevptr.pcidev;
315 DEBUGMSG("Releasing board io\n");
317 nsi_canpci_disconnect_irq(candev);
318 // First, set RESET signal to 0
319 reg_reset = ioread32( (void*)(candev->io_addr+PLX_CNTRL));
320 reg_reset&=(~(0x40000000));
322 //Then set it to '1' for reseting the board
323 iowrite32( (reg_reset | 0x40000000 ),(void*)(candev->io_addr+PLX_CNTRL));
325 udelay(2500); /* This delay must be greater than 1ms for i82527 */
326 iowrite32( (reg_reset ),(void*)(candev->io_addr+PLX_CNTRL)); //Releasing RESET signal
328 udelay(2500); // Waiting for some additionnal time before writing in the 82527
329 iounmap(((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[0]);
330 iounmap(((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[1]);
331 iounmap(((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[2]);
332 iounmap(((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[3]);
333 kfree((void*)(candev->dev_base_addr));
334 pci_release_region(pcidev,0);
335 pci_release_region(pcidev,1);
336 pci_release_region(pcidev,2);
337 pci_release_region(pcidev,3);
341 /* The function template_reset is used to give a hardware reset. This is rather
342 * hardware specific so I haven't included example code. Don't forget to check
343 * the reset status of the chip before returning.
345 int nsi_canpci_reset(struct candevice_t *candev)
347 unsigned long reg_reset;
349 DEBUGMSG("Board reset !!!\n");
350 // Before reset disconnet interrupt to avoir freeze
351 nsi_canpci_disconnect_irq(candev);
352 // First, set RESET signal to 0
353 reg_reset = ioread32( (void*)(candev->io_addr+PLX_CNTRL));
354 reg_reset&=(~(0x40000000));
355 //Then set it to '1' for reseting the board
356 iowrite32( (reg_reset | 0x40000000 ),(void*)(candev->io_addr+PLX_CNTRL));
358 udelay(2500); /* This delay must be greater than 1ms for i82527 */
359 iowrite32(reg_reset,(void*)(candev->io_addr+PLX_CNTRL)); //Releasing RESET signal
361 udelay(2500); // Waiting for some additionnal time before writing in the 82527
362 DEBUGMSG("Reset done !!!\n");
364 nsi_canpci_connect_irq(candev);
368 /* The function template_init_hw_data is used to initialize the hardware
369 * structure containing information about the installed CAN-board.
370 * RESET_ADDR represents the io-address of the hardware reset register.
371 * NR_82527 represents the number of intel 82527 chips on the board.
372 * NR_SJA1000 represents the number of philips sja1000 chips on the board.
373 * The flags entry can currently only be CANDEV_PROGRAMMABLE_IRQ to indicate that
374 * the hardware uses programmable interrupts.
377 int nsi_canpci_init_hw_data(struct candevice_t *candev)
379 struct pci_dev *pcidev;
381 /* looking for NSI CANPCI ident on the pci bus*/
382 pcidev = can_pci_get_next_untaken_device(NSI_VENDOR_ID, NSI_CANPCI_DEVICE_ID);
384 pcidev = can_pci_get_next_untaken_device(NSI_VENDOR_ID, NSI_CANPCI_DEVICE_ID+1);
386 CANMSG ("Error : NSI CAN PCI device not found\n");
390 CANMSG ("NSI CANPCI device found\n");
393 if (pci_enable_device (pcidev))
395 CANMSG ("Cannot enable PCI device\n");
398 CANMSG ("NSI CANPCI device started\n");
399 candev->sysdevptr.pcidev = pcidev;
401 candev->nr_82527_chips=2;
402 candev->nr_sja1000_chips=0;
403 candev->nr_all_chips=2;
404 /* initialize device spinlock */
405 can_spin_lock_init(&candev->device_lock);
407 if(pci_request_region(pcidev,0,"nsi_canpci bar0")==0)
409 if(pci_request_region(pcidev,1,"nsi_canpci bar1")==0)
411 if(pci_request_region(pcidev,2,"nsi_canpci bar2")==0)
413 if(pci_request_region(pcidev,3,"nsi_canpci bar3")==0)
418 pci_release_region(pcidev,0);
419 pci_release_region(pcidev,1);
420 pci_release_region(pcidev,2);
426 pci_release_region(pcidev,0);
427 pci_release_region(pcidev,1);
433 pci_release_region(pcidev,0);
441 candev->dev_base_addr=(unsigned long)(kmalloc(sizeof(t_CardArray),GFP_ATOMIC));
443 if((unsigned long)candev->dev_base_addr==0)
446 ((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[0]=ioremap(pci_resource_start(pcidev,0),pci_resource_len(pcidev,0) );
448 ((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[1]=ioremap(pci_resource_start(pcidev,1),pci_resource_len(pcidev,1) );
450 ((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[2]=ioremap(pci_resource_start(pcidev,2),pci_resource_len(pcidev,2) );
452 ((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[3]=ioremap(pci_resource_start(pcidev,3),pci_resource_len(pcidev,3) );
454 //Short acces to plx register
455 candev->io_addr=(unsigned long)(((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[0]);
459 can_pci_dev_put(pcidev);
464 void nsi_canpci_done_hw_data(struct candevice_t *candev)
466 struct pci_dev *pcidev = candev->sysdevptr.pcidev;
467 can_pci_dev_put(pcidev);
471 /* The function template_init_chip_data is used to initialize the hardware
472 * structure containing information about the CAN chips.
473 * CHIP_TYPE represents the type of CAN chip. CHIP_TYPE can be "i82527" or
475 * The chip_base_addr entry represents the start of the 'official' memory map
476 * of the installed chip. It's likely that this is the same as the candev->io_addr
477 * argument supplied at module loading time.
478 * The clock argument holds the chip clock value in Hz.
481 int nsi_canpci_init_chip_data(struct candevice_t *candev, int chipnr)
484 CANMSG ("NSI chip data init %d\n",chipnr);
485 i82527_fill_chipspecops(candev->chip[chipnr]);
487 candev->chip[chipnr]->chipspecops->chip_config =nsi_canpci_i82527_chip_config;
488 candev->chip[chipnr]->chipspecops->start_chip=nsi_canpci_start_chip;
489 candev->chip[chipnr]->chipspecops->stop_chip=nsi_canpci_stop_chip;
490 candev->chip[chipnr]->chipspecops->config_irqs=nsi_canpci_config_irqs;
491 candev->chip[chipnr]->chipspecops->irq_handler=nsi_canpci_irq_handler;
492 /*candev->chip[chipnr]->chip_data = NULL;*/
494 candev->chip[chipnr]->chip_base_addr= (unsigned long) (((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[chipnr+2]);
495 candev->chip[chipnr]->clock = iCLOCK;
496 candev->chip[chipnr]->chip_irq=candev->sysdevptr.pcidev->irq;
497 candev->chip[chipnr]->flags=CHIP_IRQ_PCI;
498 candev->chip[chipnr]->int_cpu_reg = iCPU_DSC+iCPU_CEN;
499 candev->chip[chipnr]->int_clk_reg = iCLK_SL1+iCLK_CD0;
500 candev->chip[chipnr]->int_bus_reg = iBUS_CBY;
504 /* The function template_init_obj_data is used to initialize the hardware
505 * structure containing information about the different message objects on the
506 * CAN chip. In case of the sja1000 there's only one message object but on the
507 * i82527 chip there are 15.
508 * The code below is for a i82527 chip and initializes the object base addresses
509 * The entry obj_base_addr represents the first memory address of the message
510 * object. In case of the sja1000 obj_base_addr is taken the same as the chips
512 * Unless the hardware uses a segmented memory map, flags can be set zero.
514 int nsi_canpci_init_obj_data(struct canchip_t *chip, int objnr)
518 chip->msgobj[objnr]->obj_base_addr=
519 chip->chip_base_addr+(objnr+1)*0x10;
524 /* The function template_program_irq is used for hardware that uses programmable
525 * interrupts. If your hardware doesn't use programmable interrupts you should
526 * not set the candevices_t->flags entry to CANDEV_PROGRAMMABLE_IRQ and leave this
527 * function unedited. Again this function is hardware specific so there's no
530 int nsi_canpci_program_irq(struct candevice_t *candev)
535 /* The function template_write_register is used to write to hardware registers
536 * on the CAN chip. You should only have to edit this function if your hardware
537 * uses some specific write process.
539 void nsi_canpci_write_register(unsigned data, can_ioptr_t address)
541 iowrite8((u8)data,(void*)address);
544 /* The function template_read_register is used to read from hardware registers
545 * on the CAN chip. You should only have to edit this function if your hardware
546 * uses some specific read process.
548 unsigned nsi_canpci_read_register(can_ioptr_t address)
550 return ioread8((void*)address);
554 /* !!! Don't change this function !!! */
555 int nsi_canpci_register(struct hwspecops_t *hwspecops)
557 hwspecops->request_io = nsi_canpci_request_io;
558 hwspecops->release_io = nsi_canpci_release_io;
559 hwspecops->reset = nsi_canpci_reset;
560 hwspecops->init_hw_data = nsi_canpci_init_hw_data;
561 hwspecops->done_hw_data = nsi_canpci_done_hw_data;
562 hwspecops->init_chip_data = nsi_canpci_init_chip_data;
563 hwspecops->init_obj_data = nsi_canpci_init_obj_data;
564 hwspecops->write_register = nsi_canpci_write_register;
565 hwspecops->read_register = nsi_canpci_read_register;
566 hwspecops->program_irq = nsi_canpci_program_irq;