embedded/app/usbcan/lpc17xx_can.c

   1 #include "can/lpc17xx_can.h"
   2
   3 static void CAN_configPin();
   4 static void CAN_setBusTiming(struct canchip_t *chip);
   5
   6 extern struct canhardware_t *hardware_p;
   7
   8 //---------------------------------------------------------------------------------
   9 //---------------------------------------------------------------------------------
  10
  11
  12 static inline void can_write_register(struct canchip_t *chip, uint32_t data, uint32_t reg_offs){
  13
  14         uint32_t address = chip->chip_base_addr + reg_offs;
  15         (*(volatile uint32_t*)(address)) = data;
  16
  17 }
  18
  19 static inline uint32_t can_read_register(struct canchip_t *chip, uint32_t reg_offs){
  20
  21         uint32_t address = chip->chip_base_addr + reg_offs;
  22         return (*(volatile uint32_t*)(address));
  23
  24 }
  25
  26 //---------------------------------------------------------------------------------
  27 //---------------------------------------------------------------------------------
  28
  29
  30 // interrupt handler
  31 // for transmitting - irq when one message was transmitted (for check if another message is pending in can msg queue)
  32 // for receiving - irq when message was received and is available in Receive buffer
  33
  34 void CAN_IRQHandler(){
  35
  36         uint32_t i;
  37
  38         struct canchip_t *chip;
  39         chip = hardware_p->candevice[0]->chip[0];
  40
  41         i = can_read_register(chip, CAN_ICR_o);
  42
  43         if(i & (CAN_ICR_TI1 | CAN_ICR_RI))
  44                 lpc17xx_irq_handler(0, chip);
  45
  46         if(i & CAN_ICR_DOI)
  47                 can_write_register(chip, CAN_CMR_CDO, CAN_CMR_o);
  48
  49
  50 }
  51
  52 //---------------------------------------------------------------------------------
  53 //---------------------------------------------------------------------------------
  54
  55
  56 // board can-lmc1 specific functions:
  57
  58 int can_lmc1_register(struct hwspecops_t *hwspecops){
  59
  60         hwspecops->request_io = can_lmc1_request_io;
  61         hwspecops->reset = can_lmc1_reset;
  62         hwspecops->init_hw_data = can_lmc1_init_hw_data;
  63         hwspecops->init_chip_data = can_lmc1_init_chip_data;
  64         hwspecops->init_obj_data = can_lmc1_init_obj_data;
  65         hwspecops->write_register = can_lmc1_write_register;
  66         hwspecops->read_register = can_lmc1_read_register;
  67
  68         return 0;
  69 }
  70
  71 int can_lmc1_init_hw_data(struct candevice_t *candev){
  72
  73         candev->res_addr=0;
  74         candev->nr_82527_chips=0;
  75         candev->nr_sja1000_chips=0;
  76         candev->nr_all_chips=1;
  77         candev->flags |= 0;
  78
  79         return 0;
  80 }
  81
  82 int can_lmc1_init_chip_data(struct candevice_t *candev, int chipnr){
  83
  84         lpc17xx_fill_chipspecops(candev->chip[chipnr]);
  85
  86         candev->chip[chipnr]->flags|= CHIP_IRQ_CUSTOM;
  87
  88         //debug
  89         candev->chip[chipnr]->chip_base_addr = CAN1_REGS_BASE;
  90
  91         candev->chip[chipnr]->chip_data=(void *)malloc(sizeof(struct can_lmc1_chip_data));
  92         if (candev->chip[chipnr]->chip_data==NULL)
  93                 return -ENOMEM;
  94
  95         return 0;
  96 }
  97
  98 int can_lmc1_init_obj_data(struct canchip_t *chip, int objnr){
  99
 100         return 0;
 101 }
 102
 103 void can_lmc1_write_register(unsigned data, unsigned long address){
 104         (*(volatile uint32_t*)(address)) = data;
 105 }
 106
 107 unsigned can_lmc1_read_register(unsigned long address){
 108         return (*(volatile uint32_t*)(address));
 109 }
 110
 111 int can_lmc1_request_io(struct candevice_t *candev)
 112 {
 113         return 0;
 114 }
 115
 116 int can_lmc1_reset(struct candevice_t *candev)
 117 {
 118         return 0;
 119 }
 120
 121
 122 //---------------------------------------------------------------------------------
 123 //---------------------------------------------------------------------------------
 124
 125
 126 // lpc17xx can chip specific functions:
 127
 128
 129 int lpc17xx_chip_config(struct canchip_t *chip){
 130
 131         CAN_init(chip);
 132
 133         return 0;
 134 }
 135
 136 int lpc17xx_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
 137                                                         struct canmsg_t *msg)
 138 {
 139
 140         CAN_send(chip, msg);
 141
 142         return 0;
 143 }
 144
 145 int lpc17xx_send_msg(struct canchip_t *chip, struct msgobj_t *obj,
 146                                                         struct canmsg_t *msg)
 147 {
 148
 149         // write transmission request
 150         can_write_register(chip, (CAN_CMR_TR | CAN_CMR_STB1), CAN_CMR_o);
 151
 152         return 0;
 153 }
 154
 155 int lpc17xx_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj)
 156 {
 157
 158         can_preempt_disable();
 159
 160         can_msgobj_set_fl(obj,TX_PENDING);
 161         can_msgobj_set_fl(obj,TX_REQUEST);
 162
 163         while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
 164                 can_msgobj_clear_fl(obj,TX_REQUEST);
 165
 166                 if (can_read_register(chip, CAN_SR_o) & CAN_SR_TBS1){
 167                         obj->tx_retry_cnt=0;
 168                         lpc17xx_irq_write_handler(chip, obj);
 169                 }
 170
 171                 can_msgobj_clear_fl(obj,TX_LOCK);
 172                 if(!can_msgobj_test_fl(obj,TX_REQUEST)) break;
 173
 174         }
 175
 176         can_preempt_enable();
 177
 178         return 0;
 179 }
 180
 181 int lpc17xx_irq_handler(int irq, struct canchip_t *chip)
 182 {
 183
 184         struct msgobj_t *obj;
 185         obj = chip->msgobj[0];
 186
 187         if(can_read_register(chip, CAN_SR_o) & CAN_SR_RBS) {
 188                         lpc17xx_read(chip,obj);
 189                         obj->ret = 0;
 190         }
 191
 192
 193         if ((can_msgobj_test_fl(obj,TX_PENDING)) || (can_msgobj_test_fl(obj,TX_REQUEST))) {
 194
 195                 can_msgobj_set_fl(obj,TX_REQUEST);
 196
 197                 while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
 198
 199                         obj->ret=0;
 200                         can_msgobj_clear_fl(obj,TX_REQUEST);
 201
 202                         if (can_read_register(chip, CAN_SR_o) & CAN_SR_TBS1){
 203                                 obj->tx_retry_cnt=0;
 204                                 lpc17xx_irq_write_handler(chip, obj);
 205                         }
 206
 207                         can_msgobj_clear_fl(obj,TX_LOCK);
 208                         if(!can_msgobj_test_fl(obj,TX_REQUEST)) break;
 209
 210                 }
 211         }
 212
 213
 214         return CANCHIP_IRQ_HANDLED;
 215
 216 }
 217
 218 void lpc17xx_irq_write_handler(struct canchip_t *chip, struct msgobj_t *obj)
 219 {
 220         int cmd;
 221
 222         if(obj->tx_slot){
 223                 /* Do local transmitted message distribution if enabled */
 224                 if (processlocal){
 225                         /* fill CAN message timestamp */
 226                         can_filltimestamp(&obj->tx_slot->msg.timestamp);
 227
 228                         obj->tx_slot->msg.flags |= MSG_LOCAL;
 229                         canque_filter_msg2edges(obj->qends, &obj->tx_slot->msg);
 230                 }
 231                 /* Free transmitted slot */
 232                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 233                 obj->tx_slot=NULL;
 234         }
 235
 236         can_msgobj_clear_fl(obj,TX_PENDING);
 237         cmd=canque_test_outslot(obj->qends, &obj->tx_qedge, &obj->tx_slot);
 238         if(cmd<0)
 239                 return;
 240         can_msgobj_set_fl(obj,TX_PENDING);
 241
 242         if (chip->chipspecops->pre_write_config(chip, obj, &obj->tx_slot->msg)) {
 243                 obj->ret = -1;
 244                 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_PREP);
 245                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 246                 obj->tx_slot=NULL;
 247                 return;
 248         }
 249         if (chip->chipspecops->send_msg(chip, obj, &obj->tx_slot->msg)) {
 250                 obj->ret = -1;
 251                 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_SEND);
 252                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 253                 obj->tx_slot=NULL;
 254                 return;
 255         }
 256
 257 }
 258
 259 void lpc17xx_read(struct canchip_t *chip, struct msgobj_t *obj) {
 260
 261
 262                 CAN_recv(chip, &obj->rx_msg);
 263
 264                 // fill CAN message timestamp
 265                 can_filltimestamp(&obj->rx_msg.timestamp);
 266
 267                 canque_filter_msg2edges(obj->qends, &obj->rx_msg);
 268
 269                 // release Receive buffer
 270                 can_write_register(chip, CAN_CMR_RRB, CAN_CMR_o);
 271
 272 }
 273
 274 int lpc17xx_fill_chipspecops(struct canchip_t *chip){
 275
 276         chip->max_objects=1;
 277
 278         lpc17xx_register(chip->chipspecops);
 279
 280         return 0;
 281 }
 282
 283 int lpc17xx_register(struct chipspecops_t *chipspecops){
 284
 285         CANMSG("initializing lpc17xx can chip operations\n");
 286
 287         chipspecops->attach_to_chip = lpc17xx_attach_to_chip;
 288         chipspecops->pre_read_config = lpc17xx_pre_read_config;
 289         chipspecops->chip_config = lpc17xx_chip_config;
 290         chipspecops->pre_write_config = lpc17xx_pre_write_config;
 291         chipspecops->send_msg = lpc17xx_send_msg;
 292         chipspecops->wakeup_tx = lpc17xx_wakeup_tx;
 293         chipspecops->irq_handler = lpc17xx_irq_handler;
 294
 295         return 0;
 296
 297 }
 298
 299
 300 int lpc17xx_attach_to_chip(struct canchip_t *chip){
 301
 302         return 0;
 303 }
 304
 305 int lpc17xx_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj){
 306
 307         return 1;
 308 }
 309
 310
 311
 312 //---------------------------------------------------------------------------------
 313 //---------------------------------------------------------------------------------
 314
 315
 316 static void CAN_configPin(){
 317
 318 //      CAN1 - select P0.0 as RD1. P0.1 as TD1
 319
 320         uint32_t pinsel0;
 321         uint32_t pinmode0;
 322         uint32_t pinmode_od0;
 323         uint8_t pinsel0_val = 1;
 324         uint8_t pinmode0_val = 0;
 325         uint8_t pinmode_od0_val = 0;
 326
 327
 328         pinsel0 = PINCON->PINSEL0;
 329         pinsel0 &= ~CAN1_RX_MASK;
 330         pinsel0 &= ~CAN1_TX_MASK;
 331         pinsel0 |= __val2mfld(CAN1_RX_MASK, pinsel0_val);
 332         pinsel0 |= __val2mfld(CAN1_TX_MASK, pinsel0_val);
 333         PINCON->PINSEL0 = pinsel0;
 334
 335         pinmode0 = PINCON->PINMODE0;
 336         pinmode0 &= ~CAN1_RX_MASK;
 337         pinmode0 &= ~CAN1_TX_MASK;
 338         pinmode0 |= __val2mfld(CAN1_RX_MASK, pinmode0_val);
 339         pinmode0 |= __val2mfld(CAN1_TX_MASK, pinmode0_val);
 340         PINCON->PINMODE0 = pinmode0;
 341
 342         pinmode_od0 = PINCON->PINMODE_OD0;
 343         if (pinmode_od0_val){
 344                 pinmode_od0 |= CAN1_RX_BIT;
 345                 pinmode_od0 |= CAN1_TX_BIT;
 346         }
 347         else{
 348                 pinmode_od0 &= ~CAN1_RX_BIT;
 349                 pinmode_od0 &= ~CAN1_TX_BIT;
 350         }
 351         PINCON->PINMODE_OD0 = pinmode_od0;
 352
 353
 354 }
 355
 356 void CAN_recv(struct canchip_t *chip, canmsg_t* msg){
 357
 358         volatile uint32_t data;
 359         uint32_t i;
 360
 361         // read data lenght
 362         msg->length = (can_read_register(chip, CAN_RFS_o)>>16) & 0xF;
 363
 364         // read identifier
 365         msg->id = can_read_register(chip, CAN_RID_o);
 366
 367         // EXT frame
 368         if(can_read_register(chip, CAN_RFS_o) & CAN_RFS_EXT)
 369                 msg->flags |= MSG_EXT;
 370         else
 371                 msg->flags &= ~MSG_EXT;
 372
 373
 374         // RTR frame
 375         if(can_read_register(chip, CAN_RFS_o) & CAN_RFS_RTR)
 376                 msg->flags |= MSG_RTR;
 377         else
 378                 msg->flags &= ~MSG_RTR;
 379
 380
 381         // read data
 382         data = can_read_register(chip, CAN_RDA_o);
 383         for(i=0; i<4; i++)
 384                 msg->data[i] = (data>>(i*8)) & 0xFF;
 385
 386         data = can_read_register(chip, CAN_RDB_o);
 387         for(i=4; i<8; i++)
 388                 msg->data[i] = (data>>((i-4)*8)) & 0xFF;
 389
 390 }
 391
 392 void CAN_send(struct canchip_t *chip, canmsg_t* msg){
 393
 394         volatile uint32_t data;
 395         volatile uint32_t can_tfi1;
 396         uint32_t i;
 397
 398         // check status of TB1
 399         while (!(can_read_register(chip, CAN_SR_o) & CAN_SR_TBS1)){}
 400
 401         can_tfi1 = can_read_register(chip, CAN_TFI1_o);
 402
 403         can_tfi1 &= ~0x000F0000;
 404         can_tfi1 |= (msg->length)<<16;
 405
 406         // EXT frame
 407         if(msg->flags & MSG_EXT)
 408                 can_tfi1 |= CAN_TFI1_EXT;
 409         else
 410                 can_tfi1 &= ~CAN_TFI1_EXT;
 411
 412         // RTR frame
 413         if(msg->flags & MSG_RTR)
 414                 can_tfi1 |= CAN_TFI1_RTR;
 415         else
 416                 can_tfi1 &= ~CAN_TFI1_RTR;
 417
 418         can_write_register(chip, can_tfi1, CAN_TFI1_o);
 419
 420
 421         // write CAN ID
 422         can_write_register(chip, msg->id, CAN_TID1_o);
 423
 424
 425         // write first 4 data bytes
 426         data=0;
 427         for(i=0; i<4; i++)
 428                 data |= (msg->data[i])<<(i*8);
 429
 430         can_write_register(chip, data, CAN_TDA1_o);
 431
 432         // write second 4 data bytes
 433         data=0;
 434         for(i=4; i<8; i++)
 435                 data |= (msg->data[i])<<((i-4)*8);
 436
 437         can_write_register(chip, data, CAN_TDB1_o);
 438
 439 }
 440
 441 void CAN_setBusTiming(struct canchip_t *chip){
 442
 443         uint32_t PCLK_CAN;
 444         uint32_t res;
 445
 446         uint8_t tq_numb; // number of time quantum
 447         uint8_t TSEG1, TSEG2;
 448         uint8_t BRP;
 449         uint8_t SJW;
 450         uint8_t SAM;
 451         uint8_t div;
 452
 453         // 0 = the bus is sampled once
 454         SAM = 0;
 455
 456         // the Synchronization Jump Width (this value plus one)
 457         SJW = 3;
 458
 459         // get clock divide for CAN1
 460         div = __mfld2val(PCLK_CAN1_MASK, SC->PCLKSEL0);
 461         switch(div){
 462                 case 0:
 463                         div = 4;
 464                         break;
 465                 case 1:
 466                         div = 1;
 467                         break;
 468                 case 2:
 469                         div = 2;
 470                         break;
 471                 case 3:
 472                         // only for CAN, for other peripherials '11' value means div=8
 473                         div = 6;
 474                         break;
 475         }
 476
 477
 478         PCLK_CAN = system_frequency / div;
 479
 480         res = PCLK_CAN / (chip->baudrate);
 481
 482
 483         // calculation of tq_numb - number of time quantum (must be in <8,25>)
 484         // tq_numb = TSEG1 + TSEG2 + 3
 485
 486         for(tq_numb=25; tq_numb>=8; tq_numb--){
 487
 488                 if ((res%tq_numb)==0){
 489
 490                         // Baud Rate Prescaler. The PCLK clock is divided by (this value plus one) to produce the CAN clock.
 491                         BRP = (res / tq_numb) - 1;
 492
 493                         // sync. segment allways 1 tq
 494                         tq_numb--;
 495
 496                         // number of tq from the sample point to the next nominal Sync. point (this value plus one)
 497                         TSEG2 = (tq_numb/3) - 1;
 498
 499                         // number of tq from Sync. point to the sample point (this value plus one)
 500                         TSEG1 = tq_numb - (tq_numb/3) - 1;
 501
 502                         break;
 503                 }
 504         }
 505
 506         can_write_register(chip, ((SAM<<23)|(TSEG2<<20)|(TSEG1<<16)|(SJW<<14)|(BRP<<0)), CAN_BTR_o);
 507
 508 }
 509
 510 void CAN_init(struct canchip_t *chip){
 511
 512         uint32_t tmp;
 513         uint32_t pclksel0;
 514         uint32_t val;
 515         uint32_t i;
 516
 517         printf("CAN INIT, baudrate: %d\n", chip->baudrate);
 518
 519         // configure CAN1 pins
 520         CAN_configPin();
 521
 522         // turn on power and clock for CAN1
 523         SC->PCONP |= PCCAN1;
 524
 525         // set clock divide for CAN1
 526
 527         val = 0x00; // 00       PCLK_peripheral = CCLK/4
 528         pclksel0 = SC->PCLKSEL0;
 529         pclksel0 &= ~PCLK_CAN1_MASK;
 530         pclksel0 &= ~PCLK_CAN2_MASK;
 531         pclksel0 &= ~PCLK_ACF_MASK;
 532         pclksel0 |= __val2mfld(PCLK_CAN1_MASK, val);
 533         pclksel0 |= __val2mfld(PCLK_CAN2_MASK, val);
 534         pclksel0 |= __val2mfld(PCLK_ACF_MASK, val);
 535         SC->PCLKSEL0 = pclksel0;
 536
 537         // enter reset mode
 538         can_write_register(chip, 1, CAN_MOD_o);
 539
 540         // disable all CAN interrupts
 541         can_write_register(chip, 0, CAN_IER_o);
 542
 543         // reset value of Global Status Register (global controller status and error counters)
 544         can_write_register(chip, 0x3C, CAN_GSR_o);
 545
 546         // request command to release Rx, Tx buffer and clear data overrun
 547         can_write_register(chip, (CAN_CMR_AT | CAN_CMR_RRB | CAN_CMR_CDO), CAN_CMR_o);
 548
 549         // read to clear interrupt pending in Interrupt Capture Register
 550         tmp = can_read_register(chip, CAN_ICR_o);
 551
 552         // set bus timing
 553         CAN_setBusTiming(chip);
 554
 555         // return to normal operating
 556         can_write_register(chip, 0, CAN_MOD_o);
 557
 558
 559         //--------------------------
 560
 561         // Acceptance Filter Off Mode
 562         CANAF_AFMR = 0x01;
 563
 564         // clear RAM masks
 565         for (i = 0; i < 512; i++) {
 566                 CANAF_RAM->mask[i] = 0x00;
 567         }
 568
 569         CANAF_SFF_sa = 0x00;
 570         CANAF_SFF_GRP_sa = 0x00;
 571         CANAF_EFF_sa = 0x00;
 572         CANAF_EFF_GRP_sa = 0x00;
 573         CANAF_ENDofTable = 0x00;
 574
 575         // Acceptance Filter Bypass Mode - all messages accepted
 576         CANAF_AFMR = 0x02;
 577
 578         //--------------------------
 579
 580
 581         // enable interrupt after transmit
 582         // enable receive interrupt
 583         // enable data overrun interrupt
 584         can_write_register(chip, (CAN_IER_TIE1 | CAN_IER_RIE | CAN_IER_DOIE), CAN_IER_o);
 585
 586         // enable CAN interrupt
 587         NVIC_EnableIRQ(CAN_IRQn);
 588
 589
 590
 591 }
 592