4 Routines for sending and receiving messages for configuration and/or
5 communication over CAN network using a SJA1000 transceiver.
6 For use in UL_USB1 module, it runs in Intel mode.
7 See documentation for details.
15 /***********************************************************************
16 * Microsecond delay routine
17 ***********************************************************************/
18 void udelay(long time)
20 volatile long ticks=(time * CCLK) / 2000000;
27 inline void can_data_pins_dir_output(void)
29 IO1DIR|=P1_SJA1000_DATA_PINS; // Port as output to send data
32 inline void can_data_pins_dir_input(void)
34 IO1DIR&=~P1_SJA1000_DATA_PINS; // Sets port as input
37 inline void can_data_pins_set_value(uint8_t data)
39 uint32_t val = __val2mfld(P1_SJA1000_DATA_PINS,data);
41 * Clear only that pins, which need that, lower transition
42 * frequency and eliminate spikes
44 IO1CLR= val ^ P1_SJA1000_DATA_PINS;
48 inline uint8_t can_data_pins_get_value(void)
50 return __mfld2val(P1_SJA1000_DATA_PINS,IO1PIN);
56 //CANMSG("Start can_comm_init\n");
57 IO1DIR |= P1_OUT_PORT_CS_PIN|P1_SJA1000_RST_PIN;
58 // Due to change in design there is CS_PIN connected with ALE_PIN and ALE_PIN connection to LPC is interrupted
59 // We don't use ALE_PIN
60 //IO0DIR|=P0_SJA1000_ALE_PIN|P0_SJA1000_CS_PIN|P0_SJA1000_RD_PIN|P0_SJA1000_WR_PIN;
61 IO0DIR|=P0_SJA1000_CS_PIN|P0_SJA1000_RD_PIN|P0_SJA1000_WR_PIN;
62 IO0DIR&=~(P0_SJA1000_INT_PIN);
64 SET_OUT_PIN(IO0,P0_SJA1000_CS_PIN);
65 CLR_OUT_PIN(IO1,P1_SJA1000_RST_PIN);
67 SET_OUT_PIN(IO0,P0_SJA1000_CS_PIN);
68 // Due to change in design there is CS_PIN connected with ALE_PIN and ALE_PIN connection to LPC is interrupted
69 // CLR_OUT_PIN(IO0,P0_SJA1000_ALE_PIN);
70 SET_OUT_PIN(IO1,P1_SJA1000_RST_PIN);
74 void can_write(uint8_t data, uint8_t address)
76 can_data_pins_dir_output();
78 can_data_pins_set_value(address);
80 SET_OUT_PIN(IO0,P0_SJA1000_RD_PIN); // Stays high on write
81 SET_OUT_PIN(IO0,P0_SJA1000_WR_PIN); // Stays high on address write
82 SET_OUT_PIN(IO0,P0_SJA1000_CS_PIN); // Sets output buffers to third state
84 //SET_OUT_PIN(IO0,P0_SJA1000_ALE_PIN); // Start command
87 //CLR_OUT_PIN(IO0,P0_SJA1000_ALE_PIN); // Makes address active
88 CLR_OUT_PIN(IO0,P0_SJA1000_CS_PIN);
92 can_data_pins_set_value(data);
94 CLR_OUT_PIN(IO0,P0_SJA1000_WR_PIN);
95 CLR_OUT_PIN(IO0,P0_SJA1000_WR_PIN);
97 SET_OUT_PIN(IO0,P0_SJA1000_WR_PIN); // Data should be accepted by now
98 SET_OUT_PIN(IO0,P0_SJA1000_CS_PIN);
102 uint8_t can_read(const uint8_t address)
106 can_data_pins_dir_output();
107 // Set memory address
108 can_data_pins_set_value(address);
110 SET_OUT_PIN(IO0,P0_SJA1000_WR_PIN); // Stays high on read
111 SET_OUT_PIN(IO0,P0_SJA1000_RD_PIN); // Stays high while entering address
112 SET_OUT_PIN(IO0,P0_SJA1000_CS_PIN);
114 //SET_OUT_PIN(IO0,P0_SJA1000_ALE_PIN);
117 //CLR_OUT_PIN(IO0,P0_SJA1000_ALE_PIN);
118 CLR_OUT_PIN(IO0,P0_SJA1000_CS_PIN);
122 can_data_pins_dir_input();
123 CLR_OUT_PIN(IO0,P0_SJA1000_RD_PIN);
124 CLR_OUT_PIN(IO0,P0_SJA1000_RD_PIN);
126 data = can_data_pins_get_value();
127 SET_OUT_PIN(IO0,P0_SJA1000_RD_PIN);
128 SET_OUT_PIN(IO0,P0_SJA1000_CS_PIN);
135 uint8_t data=0,count=0;
138 data = can_read(SJAMOD);
141 } while (!(data&sjaMOD_RM));
143 data=sjaCDR_CLKOUT_DIV1|sjaCDR_CLK_OFF|sjaCDR_CBP|sjaCDR_PELICAN;
144 can_write(data, SJACDR);
146 // Single acceptance filter, reset mode
147 data=sjaMOD_AFM|sjaMOD_RM;
148 can_write(data, SJAMOD);
150 // Enabling all interrupt sources
151 data=sjaENABLE_INTERRUPTS;
152 can_write(data, SJAIER);
154 // Accept all messages
156 can_write(data, SJAAMR0);
157 can_write(data, SJAAMR0+1);
158 can_write(data, SJAAMR0+2);
159 can_write(data, SJAAMR0+3);
162 can_write(data, SJACMR);