1 /*******************************************************************
2 Components for embedded applications builded for
3 laboratory and medical instruments firmware
5 system_def.h - common cover for definition of hardware adresses,
6 registers, timing and other hardware dependant
7 parts of embedded hardware
9 Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
10 (C) 2002 by PiKRON Ltd. http://www.pikron.com
12 *******************************************************************/
14 #ifndef _SYSTEM_DEF_H_
15 #define _SYSTEM_DEF_H_
18 #include <system_stub.h>
28 #define VER_CODE(major,minor,patch) (major*0x10000+minor*0x100+patch)
29 /* Software version */
30 #define SW_VER_ID "UL_HA_2X_RELAY_ACTUATOR"
31 #define SW_VER_MAJOR 0
32 #define SW_VER_MINOR 2
33 #define SW_VER_PATCH 0
34 #define SW_VER_CODE VER_CODE(SW_VER_MAJOR,SW_VER_MINOR,SW_VER_PATCH)
35 /* Hardware version */
36 #define HW_VER_ID "UL_HA_2X_RELAY_ACTUATOR"
37 #define HW_VER_MAJOR 1
38 #define HW_VER_MINOR 0
39 #define HW_VER_PATCH 0
40 #define HW_VER_CODE VER_CODE(HW_VER_MAJOR,HW_VER_MINOR,HW_VER_PATCH)
41 /* Version of mechanical */
42 #define MECH_VER_ID "UL_HA_2X_RELAY_ACTUATOR"
43 #define MECH_VER_MAJOR 0
44 #define MECH_VER_MINOR 0
45 #define MECH_VER_PATCH 0
46 #define MECH_VER_CODE VER_CODE(MECH_VER_MAJOR,MECH_VER_MINOR,MECH_VER_PATCH)
49 // PLL setup values are computed within the LPC include file
50 // It relies upon the following defines
51 #define FOSC (14745600) // Master Oscillator Freq.
52 #define PLL_MUL (4) // PLL Multiplier
53 #define CCLK (FOSC * PLL_MUL) // CPU Clock Freq.
55 // Pheripheral Bus Speed Divider
56 #define PBSD 1 // MUST BE 1, 2, or 4
57 #define PCLK (CCLK / PBSD) // Pheripheal Bus Clock Freq.
59 #define SYS_TIMER_HZ 1000
62 #define BIT(n) (1 << (n))
65 // Port Bit Definitions & Macros: Description - initial conditions
66 #define RE2_BIT BIT(0) // used by UART0
67 #define RE1_BIT BIT(1) // used by UART0
68 #define LED5_BIT BIT(2)
69 #define LED4_BIT BIT(3)
70 #define LED3_BIT BIT(4)
71 #define LED2_BIT BIT(5)
72 #define LED1_BIT BIT(6)
73 #define P0_07_UNUSED_BIT BIT(7)
74 #define TXD1_BIT BIT(8)
75 #define RXD1_BIT BIT(9) // used by UART1
76 #define RTS1_BIT BIT(10) // used by UART1
77 #define CTS1_BIT BIT(11) // used by UART1
78 #define DSR1_BIT BIT(12) // used by UART1
79 #define P0_13_UNUSED_BIT BIT(13)
80 #define BOOT_BIT BIT(14)
81 #define IN1_BIT BIT(15)
82 #define IN2_BIT BIT(16)
83 #define P0_17_UNUSED_BIT BIT(17)
84 #define P0_18_UNUSED_BIT BIT(18)
85 #define AC_IN_BIT BIT(19)
86 #define P0_20_UNUSED_BIT BIT(20)
87 #define P0_21_UNUSED_BIT BIT(21)
88 #define P0_22_UNUSED_BIT BIT(22)
89 #define P0_23_UNUSED_BIT BIT(23)
90 #define P0_24_UNUSED_BIT BIT(24)
91 #define TEMP_BIT BIT(25)
92 #define P0_26_UNUSED_BIT BIT(26)
93 #define P0_27_UNUSED_BIT BIT(27)
94 #define P0_28_UNUSED_BIT BIT(28)
95 #define P0_29_UNUSED_BIT BIT(29)
96 #define P0_30_UNUSED_BIT BIT(30)
97 #define BUTTON_BIT BIT(31)
100 #define P0IO_INPUT_BITS (uint32_t) ( \
109 #define P0IO_ZERO_BITS (uint32_t) ( \
135 #define P0IO_ONE_BITS (uint32_t) ( \
139 #define P0IO_OUTPUT_BITS (uint32_t) ( \
144 /***************************************************************************/
146 #define LED_GP LED1_BIT /* GENREAL PURPOSE LED */
147 #define LED_ERR LED2_BIT
149 /***************************************************************************/
155 #define CREATE_PORT_NAME_PIN(port) port##PIN
156 #define CREATE_PORT_NAME_CLR(port) port##CLR
157 #define CREATE_PORT_NAME_SET(port) port##SET
159 #define GET_IN_PIN(port,in) ((CREATE_PORT_NAME_PIN(port) & in)?1:0)
160 #define SET_OUT_PIN(port,out) (CREATE_PORT_NAME_SET(port)=out)
161 #define CLR_OUT_PIN(port,out) (CREATE_PORT_NAME_CLR(port)=out)
163 /***************************************************************************/
165 #define WATCHDOG_ENABLED
166 #define WATCHDOG_TIMEOUT_MS 1000
168 /***************************************************************************/
169 /* uLan configuration */
174 #ifdef ULD_DEFAULT_BUFFER_SIZE
175 #undef ULD_DEFAULT_BUFFER_SIZE
176 #define ULD_DEFAULT_BUFFER_SIZE 0x0400
179 #define UL_DRV_SYSLESS_PORT 0xE0010000
180 #define UL_DRV_SYSLESS_BAUD 19200
181 #define UL_DRV_SYSLESS_IRQ HAL_INTERRUPT_UART1
182 #define UL_DRV_SYSLESS_MY_ADR_DEFAULT 1
185 #define watchdog_feed lpc_watchdog_feed
186 #define kvpb_erase lpcisp_kvpb_erase
187 #define kvpb_copy lpcisp_kvpb_copy
188 #define kvpb_flush lpcisp_kvpb_flush
189 #define KVPB_DEFAULT_FLAGS KVPB_DESC_DOUBLE|KVPB_DESC_CHUNKWO
191 #define HAL_ARM_LPC2XXX_EXTINT_ERRATA
193 #endif /* _SYSTEM_DEF_H_ */