1 /******************************************************************************
6 * Header file for Philips LPC214x USB enabled ARM Processors
7 * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
9 * No guarantees, warrantees, or promises, implied or otherwise.
10 * May be used for hobby or commercial purposes provided copyright
11 * notice remains intact or GPL license is applied.
13 *****************************************************************************/
18 /* USBIntSt - USB Interrupt Status (R/W) */
19 #define USB_INT_REQ_LP (1<<0) /*Low priority interrupt line status (RO) */
20 #define USB_INT_REQ_HP (1<<1) /*High priority interrupt line status. (RO) */
21 #define USB_INT_REQ_DMA (1<<2) /*DMA interrupt line status. This bit is read only. (LPC2146/8 only) 0*/
22 #define USB_need_clock (1<<8) /*USB need clock indicator*/
23 #define USB_EN_USB_INTS (1<<31) /*Enable all USB interrupts*/
25 /* Device interrupt registers */
26 #define USBDevIntSt_o 0x0000 /* USB Device Interrupt Status (RO) */
27 #define USBDevIntEn_o 0x0004 /* USB Device Interrupt Enable (R/W) */
28 #define USBDevIntClr_o 0x0008 /* USB Device Interrupt Clear (WO) */
29 #define USBDevIntSet_o 0x000C /* USB Device Interrupt Set (WO) */
30 #define USBDevInt_FRAME (1<<0) /*Frame interrupt @1kHz for ISO transfers*/
31 #define USBDevInt_EP_FAST (1<<1) /*Fast interrupt transfer for the endpoint*/
32 #define USBDevInt_EP_SLOW (1<<2) /*Slow interrupt transfer for the endpoint*/
33 #define USBDevInt_DEV_STAT (1<<3) /*USB Bus reset, USB suspend change or Connect occured*/
34 #define USBDevInt_CCEMTY (1<<4) /*Command code register is empty/ready for CMD*/
35 #define USBDevInt_CDFULL (1<<5) /*Command data register is full/data available*/
36 #define USBDevInt_RxENDPKT (1<<6) /*Current packet in the FIFO is transferred to the CPU*/
37 #define USBDevInt_TxENDPKT (1<<7) /*TxPacket bytes written to FIFO*/
38 #define USBDevInt_EP_RLZED (1<<8) /*Endpoints realized after Maxpacket size update*/
39 #define USBDevInt_ERR_INT (1<<9) /*Error Interrupt - Use Read Error Status Command 0xFB*/
41 #define USBDevIntPri_o 0x002C /* USB Device Interrupt Priority (WO) */
42 #define USBDevIntPri_FRAME (1<<0) /*0/1 FRAME int routed to the low/high priority interrupt line*/
43 #define USBDevIntPri_EP_FAST (1<<1) /*0/1 EP_FAST int routed to the low/high priority line*/
45 /* Endpoint interrupt registers - bits corresponds to EP0 to EP31 */
46 #define USBEpIntSt_o 0x0030 /* USB Endpoint Interrupt Status (RO) */
47 #define USBEpIntEn_o 0x0034 /* USB Endpoint Interrupt Enable (R/W) */
48 #define USBEpIntClr_o 0x0038 /* USB Endpoint Interrupt Clear (WO) */
49 #define USBEpIntSet_o 0x003C /* USB Endpoint Interrupt Set (WO) */
50 #define USBEpIntPri_o 0x0040 /* USB Endpoint Priority (WO) */
51 /* Endpoint realization registers */
52 #define USBReEp_o 0x0044 /* USB Realize Endpoint (R/W) */
53 #define USBEpInd_o 0x0048 /* USB Endpoint Index (WO) */
54 #define USBEpInd_Ind 0x001F /* Index for subsequent USBMaxPSize (WO) */
55 #define USBMaxPSize_o 0x004C /* USB MaxPacketSize (R/W) */
56 #define USBMaxPSize_Size 0x03FF /* The maximum packet size value */
57 /* USB transfer registers */
58 #define USBRxData_o 0x0018 /* USB Receive Data (RO) */
59 #define USBRxPLen_o 0x0020 /* USB Receive Packet Length (RO) */
60 #define USBRxPLen_PKT_LNGTH (0x03FF) /*Remaining amount of bytes to be read from RAM*/
61 #define USBRxPLen_DV (1<<10) /*Data valid. 0 only for error ISO packet*/
62 #define USBRxPLen_PKT_RDY (1<<11) /*Packet length valid and packet is ready for reading*/
63 #define USBTxData_o 0x001C /* USB Transmit Data (WO) */
64 #define USBTxPLen_o 0x0024 /* USB Transmit Packet Length (WO) */
65 #define USBTxPLen_PKT_LNGTH (0x03FF) /*Remaining amount of bytes to be written to the EP_RAM*/
66 #define USBCtrl_o 0x0028 /* USB Control (R/W) */
67 #define USBCtrl_RD_EN (1<<0) /*Read mode control*/
68 #define USBCtrl_WR_EN (1<<1) /*Write mode control*/
69 #define USBCtrl_LOG_ENDPOINT 0x003C /*Logical Endpoint number*/
70 /* Command registers */
71 #define USBCmdCode_o 0x0010 /* USB Command Code (WO) */
72 #define USBCmdCode_CMD_PHASE 0x0000FF00 /*The command phase*/
73 #define USBCmdCode_CMD_CODE 0x00FF0000 /*The code for the command*/
74 #define USBCmdData_o 0x0014 /* USB Command Data (RO) */
75 /* DMA registers (LPC2146/8 only) */
76 #define USBDMARSt_o 0x0050 /* USB DMA Request Status (RO) */
77 #define USBDMARClr_o 0x0054 /* USB DMA Request Clear (WO) */
78 #define USBDMARSet_o 0x0058 /* USB DMA Request Set (WO) */
79 #define USBUDCAH_o 0x0080 /* USB UDCA Head (R/W) has to be aligned to 128 bytes */
80 #define USBEpDMASt_o 0x0084 /* USB Endpoint DMA Status (RO) */
81 #define USBEpDMAEn_o 0x0088 /* USB Endpoint DMA Enable (WO) */
82 #define USBEpDMADis_o 0x008C /* USB Endpoint DMA Disable (WO) */
83 #define USBDMAIntSt_o 0x0090 /* USB DMA Interrupt Status (RO) */
84 #define USBDMAIntEn_o 0x0094 /* USB DMA Interrupt Enable (R/W) */
85 #define USBDMAInt_EoT (1<<0) /*End of Transfer Interrupt bit, 1 if USBEoTIntSt != 0*/
86 #define USBDMAInt_New_DD_Rq (1<<1) /* New DD Request Interrupt bit, 1 if USBNDDRIntSt != 0*/
87 #define USBDMAInt_SysError (1<<2) /*System Error Interrupt bit, 1 if USBSysErrIntSt != 0*/
88 #define USBEoTIntSt_o 0x00A0 /* USB End of Transfer Interrupt Status (RO) */
89 #define USBEoTIntClr_o 0x00A4 /* USB End of Transfer Interrupt Clear (WO) */
90 #define USBEoTIntSet_o 0x00A8 /* USB End of Transfer Interrupt Set (WO) */
91 #define USBNDDRIntSt_o 0x00AC /* USB New DD Request Interrupt Status (RO) */
92 #define USBNDDRIntClr_o 0x00B0 /* USB New DD Request Interrupt Clear (WO) */
93 #define USBNDDRIntSet_o 0x00B4 /* USB New DD Request Interrupt Set (WO) */
94 #define USBSysErrIntSt_o 0x00B8 /* USB System Error Interrupt Status (RO) */
95 #define USBSysErrIntClr_o 0x00BC /* USB System Error Interrupt Clear (WO) */
96 #define USBSysErrIntSet_o 0x00C0 /* USB System Error Interrupt Set (WO) */
97 #define USB_MODULE_ID_o 0x00FC /* USB Module ID */
100 #define USB_CMD_SET_ADDR 0x00D00500
101 #define USB_CMD_CFG_DEV 0x00D80500
102 #define USB_CMD_SET_MODE 0x00F30500
103 #define USB_CMD_RD_FRAME 0x00F50500
104 #define USB_DAT_RD_FRAME 0x00F50200
105 #define USB_CMD_RD_TEST 0x00FD0500
106 #define USB_DAT_RD_TEST 0x00FD0200
107 #define USB_CMD_SET_DEV_STAT 0x00FE0500
108 #define USB_CMD_GET_DEV_STAT 0x00FE0500
109 #define USB_DAT_GET_DEV_STAT 0x00FE0200
110 #define USB_CMD_GET_ERR_CODE 0x00FF0500
111 #define USB_DAT_GET_ERR_CODE 0x00FF0200
112 #define USB_CMD_RD_ERR_STAT 0x00FB0500
113 #define USB_DAT_RD_ERR_STAT 0x00FB0200
114 #define USB_DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
115 #define USB_CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
116 #define USB_DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
117 #define USB_CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
118 #define USB_DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
119 #define USB_CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
120 #define USB_CMD_CLR_BUF 0x00F20500
121 #define USB_DAT_CLR_BUF 0x00F20200
122 #define USB_CMD_VALID_BUF 0x00FA0500
124 /* Device Address Register Definitions */
125 #define USBC_DEV_ADDR_MASK 0x7F
126 #define USBC_DEV_EN 0x80
128 /* Device Configure Register Definitions */
129 #define USBC_CONF_DEVICE 0x01
131 /* Device Mode Register Definitions */
132 #define USBC_AP_CLK 0x01
133 #define USBC_INAK_CI 0x02
134 #define USBC_INAK_CO 0x04
135 #define USBC_INAK_II 0x08
136 #define USBC_INAK_IO 0x10
137 #define USBC_INAK_BI 0x20
138 #define USBC_INAK_BO 0x40
140 /* Device Status Register Definitions */
141 #define USBC_DEV_CON 0x01
142 #define USBC_DEV_CON_CH 0x02
143 #define USBC_DEV_SUS 0x04
144 #define USBC_DEV_SUS_CH 0x08
145 #define USBC_DEV_RST 0x10
147 /* Error Code Register Definitions */
148 #define USBC_ERR_EC_MASK 0x0F
149 #define USBC_ERR_EA 0x10
151 /* Error Status Register Definitions */
152 #define USBC_ERR_PID 0x01
153 #define USBC_ERR_UEPKT 0x02
154 #define USBC_ERR_DCRC 0x04
155 #define USBC_ERR_TIMOUT 0x08
156 #define USBC_ERR_EOP 0x10
157 #define USBC_ERR_B_OVRN 0x20
158 #define USBC_ERR_BTSTF 0x40
159 #define USBC_ERR_TGL 0x80
161 /* Endpoint Select Register Definitions */
162 #define USBC_EP_SEL_F 0x01
163 #define USBC_EP_SEL_ST 0x02
164 #define USBC_EP_SEL_STP 0x04
165 #define USBC_EP_SEL_PO 0x08
166 #define USBC_EP_SEL_EPN 0x10
167 #define USBC_EP_SEL_B_1_FULL 0x20
168 #define USBC_EP_SEL_B_2_FULL 0x40
170 /* Endpoint Status Register Definitions */
171 #define USBC_EP_STAT_ST 0x01
172 #define USBC_EP_STAT_DA 0x20
173 #define USBC_EP_STAT_RF_MO 0x40
174 #define USBC_EP_STAT_CND_ST 0x80
176 /* Clear Buffer Register Definitions */
177 #define USBC_CLR_BUF_PO 0x01
181 /* Device interrupt registers */
182 REG32 DevIntSt; /* USB Device Interrupt Status (RO) 0000 */
183 REG32 DevIntEn; /* USB Device Interrupt Enable (R/W) 0004 */
184 REG32 DevIntClr; /* USB Device Interrupt Clear (WO) 0008 */
185 REG32 DevIntSet; /* USB Device Interrupt Set (WO) 000C */
186 /* Command registers */
187 REG32 CmdCode; /* USB Command Code (WO) 0010 */
188 REG32 CmdData; /* USB Command Data (RO) 0014 */
189 /* USB transfer registers */
190 REG32 RxData; /* USB Receive Data (RO) 0018 */
191 REG32 TxData; /* USB Transmit Data (WO) 001C */
192 REG32 RxPLen; /* USB Receive Packet Length (RO) 0020 */
193 REG32 TxPLen; /* USB Transmit Packet Length (WO) 0024 */
194 REG32 Ctrl; /* USB Control (R/W) 0028 */
195 /* Device interrupt priority register */
196 REG_8 USBDevIntPri; /* USB Device Interrupt Priority (WO) 002C */
198 /* Endpoint interrupt registers */
199 REG32 EpIntSt; /* USB Endpoint Interrupt Status (RO) 0030 */
200 REG32 EpIntEn; /* USB Endpoint Interrupt Enable (R/W) 0034 */
201 REG32 EpIntClr; /* USB Endpoint Interrupt Clear (WO) 0038 */
202 REG32 EpIntSet; /* USB Endpoint Interrupt Set (WO) 003C */
203 REG32 EpIntPri; /* USB Endpoint Priority (WO) 0040 */
204 /* Endpoint realization registers */
205 REG32 ReEp; /* USB Realize Endpoint (R/W) 0044 */
206 REG32 EpInd; /* USB Endpoint Index (WO) 0048 */
207 REG32 MaxPSize; /* USB MaxPacketSize (R/W) 004C */
208 /* DMA registers (LPC2146/8 only) */
209 REG32 DMARSt; /* USB DMA Request Status (RO) 0050 */
210 REG32 DMARClr; /* USB DMA Request Clear (WO) 0054 */
211 REG32 DMARSet; /* USB DMA Request Set (WO) 0058 */
213 REG32 UDCAH; /* USB UDCA Head (R/W) 0080 */
214 REG32 EpDMASt; /* USB Endpoint DMA Status (RO) 0084 */
215 REG32 EpDMAEn; /* USB Endpoint DMA Enable (WO) 0088 */
216 REG32 EpDMADis; /* USB Endpoint DMA Disable (WO) 008C */
217 REG32 DMAIntSt; /* USB DMA Interrupt Status (RO) 0090 */
218 REG32 DMAIntEn; /* USB DMA Interrupt Enable (R/W) 0094 */
220 REG32 EoTIntSt; /* USB End of Transfer Interrupt Status (RO) 00A0 */
221 REG32 EoTIntClr; /* USB End of Transfer Interrupt Clear (WO) 00A4 */
222 REG32 EoTIntSet; /* USB End of Transfer Interrupt Set (WO) 00A8 */
223 REG32 NDDRIntSt; /* USB New DD Request Interrupt Status (RO) 00AC */
224 REG32 NDDRIntClr; /* USB New DD Request Interrupt Clear (WO) 00B0 */
225 REG32 NDDRIntSet; /* USB New DD Request Interrupt Set (WO) 00B4 */
226 REG32 SysErrIntSt; /* USB System Error Interrupt Status (RO) 00B8 */
227 REG32 SysErrIntClr; /* USB System Error Interrupt Clear (WO) 00BC */
228 REG32 SysErrIntSet; /* USB System Error Interrupt Set (WO) 00C0 */
230 REG32 MODULE_ID; /* Module ID (RO) 00FC */