1 /******************************************************************************
3 * $RCSfile: LPC21xx.h,v $
6 * Header file for Philips LPC21xx ARM Processors
7 * Copyright 2004 R O SoftWare
9 * No guarantees, warrantees, or promises, implied or otherwise.
10 * May be used for hobby or commercial purposes provided copyright
11 * notice remains intact.
13 *****************************************************************************/
17 #define REG_8 volatile unsigned char
18 #define REG16 volatile unsigned short
19 #define REG32 volatile unsigned long
33 ///////////////////////////////////////////////////////////////////////////////
35 #define KVPB_CHUNK_SIZE 16
37 ///////////////////////////////////////////////////////////////////////////////
38 // ISP_RAM2FLASH_BLOCK_SIZE for CPU - minimal is 512, can be smaller for some CPU
39 #ifndef ISP_RAM2FLASH_BLOCK_SIZE
40 #define ISP_RAM2FLASH_BLOCK_SIZE 512
41 #endif /* ISP_RAM2FLASH_BLOCK_SIZE */
43 ///////////////////////////////////////////////////////////////////////////////
45 #define WD ((wdRegs_t *)0xE0000000)
48 #define WDMOD WD->mod /* Watchdog Mode Register */
49 #define WDTC WD->tc /* Watchdog Time Constant Register */
50 #define WDFEED WD->feed /* Watchdog Feed Register */
51 #define WDTV WD->tv /* Watchdog Time Value Register */
53 ///////////////////////////////////////////////////////////////////////////////
55 #define TMR0 ((pwmTmrRegs_t *)0xE0004000)
58 #define T0IR TMR0->ir /* Interrupt Register */
59 #define T0TCR TMR0->tcr /* Timer Control Register */
60 #define T0TC TMR0->tc /* Timer Counter */
61 #define T0PR TMR0->pr /* Prescale Register */
62 #define T0PC TMR0->pc /* Prescale Counter Register */
63 #define T0MCR TMR0->mcr /* Match Control Register */
64 #define T0MR0 TMR0->mr0 /* Match Register 0 */
65 #define T0MR1 TMR0->mr1 /* Match Register 1 */
66 #define T0MR2 TMR0->mr2 /* Match Register 2 */
67 #define T0MR3 TMR0->mr3 /* Match Register 3 */
68 #define T0CCR TMR0->ccr /* Capture Control Register */
69 #define T0CR0 TMR0->cr0 /* Capture Register 0 */
70 #define T0CR1 TMR0->cr1 /* Capture Register 1 */
71 #define T0CR2 TMR0->cr2 /* Capture Register 2 */
72 #define T0CR3 TMR0->cr3 /* Capture Register 3 */
73 #define T0EMR TMR0->emr /* External Match Register */
75 ///////////////////////////////////////////////////////////////////////////////
77 #define TMR1 ((pwmTmrRegs_t *)0xE0008000)
80 #define T1IR TMR1->ir /* Interrupt Register */
81 #define T1TCR TMR1->tcr /* Timer Control Register */
82 #define T1TC TMR1->tc /* Timer Counter */
83 #define T1PR TMR1->pr /* Prescale Register */
84 #define T1PC TMR1->pc /* Prescale Counter Register */
85 #define T1MCR TMR1->mcr /* Match Control Register */
86 #define T1MR0 TMR1->mr0 /* Match Register 0 */
87 #define T1MR1 TMR1->mr1 /* Match Register 1 */
88 #define T1MR2 TMR1->mr2 /* Match Register 2 */
89 #define T1MR3 TMR1->mr3 /* Match Register 3 */
90 #define T1CCR TMR1->ccr /* Capture Control Register */
91 #define T1CR0 TMR1->cr0 /* Capture Register 0 */
92 #define T1CR1 TMR1->cr1 /* Capture Register 1 */
93 #define T1CR2 TMR1->cr2 /* Capture Register 2 */
94 #define T1CR3 TMR1->cr3 /* Capture Register 3 */
95 #define T1EMR TMR1->emr /* External Match Register */
97 ///////////////////////////////////////////////////////////////////////////////
98 // Pulse Width Modulator (PWM)
99 #define PWM ((pwmTmrRegs_t *)0xE0014000)
102 #define PWMIR PWM->ir /* Interrupt Register */
103 #define PWMTCR PWM->tcr /* Timer Control Register */
104 #define PWMTC PWM->tc /* Timer Counter */
105 #define PWMPR PWM->pr /* Prescale Register */
106 #define PWMPC PWM->pc /* Prescale Counter Register */
107 #define PWMMCR PWM->mcr /* Match Control Register */
108 #define PWMMR0 PWM->mr0 /* Match Register 0 */
109 #define PWMMR1 PWM->mr1 /* Match Register 1 */
110 #define PWMMR2 PWM->mr2 /* Match Register 2 */
111 #define PWMMR3 PWM->mr3 /* Match Register 3 */
112 #define PWMMR4 PWM->mr4 /* Match Register 4 */
113 #define PWMMR5 PWM->mr5 /* Match Register 5 */
114 #define PWMMR6 PWM->mr6 /* Match Register 6 */
115 #define PWMPCR PWM->pcr /* Control Register */
116 #define PWMLER PWM->ler /* Latch Enable Register */
118 ///////////////////////////////////////////////////////////////////////////////
119 // Universal Asynchronous Receiver Transmitter 0 (UART0)
120 #define UART0 ((uartRegs_t *)0xE000C000)
121 #define U0_PINSEL (0x00000005) /* PINSEL0 Value for UART0 */
122 #define U0_PINMASK (0x0000000F) /* PINSEL0 Mask for UART0 */
125 #define U0RBR UART0->rbr /* Receive Buffer Register */
126 #define U0THR UART0->thr /* Transmit Holding Register */
127 #define U0IER UART0->ier /* Interrupt Enable Register */
128 #define U0IIR UART0->iir /* Interrupt ID Register */
129 #define U0FCR UART0->fcr /* FIFO Control Register */
130 #define U0LCR UART0->lcr /* Line Control Register */
131 #define U0LSR UART0->lsr /* Line Status Register */
132 #define U0SCR UART0->scr /* Scratch Pad Register */
133 #define U0DLL UART0->dll /* Divisor Latch Register (LSB) */
134 #define U0DLM UART0->dlm /* Divisor Latch Register (MSB) */
136 ///////////////////////////////////////////////////////////////////////////////
137 // Universal Asynchronous Receiver Transmitter 1 (UART1)
138 #define UART1 ((uartRegs_t *)0xE0010000)
139 #define U1_PINSEL (0x00050000) /* PINSEL0 Value for UART1 */
140 #define U1_PINMASK (0x000F0000) /* PINSEL0 Mask for UART1 */
143 #define U1RBR UART1->rbr /* Receive Buffer Register */
144 #define U1THR UART1->thr /* Transmit Holding Register */
145 #define U1IER UART1->ier /* Interrupt Enable Register */
146 #define U1IIR UART1->iir /* Interrupt ID Register */
147 #define U1FCR UART1->fcr /* FIFO Control Register */
148 #define U1LCR UART1->lcr /* Line Control Register */
149 #define U1MCR UART1->mcr /* MODEM Control Register */
150 #define U1LSR UART1->lsr /* Line Status Register */
151 #define U1MSR UART1->msr /* MODEM Status Register */
152 #define U1SCR UART1->scr /* Scratch Pad Register */
153 #define U1DLL UART1->dll /* Divisor Latch Register (LSB) */
154 #define U1DLM UART1->dlm /* Divisor Latch Register (MSB) */
156 ///////////////////////////////////////////////////////////////////////////////
158 #define I2C ((i2cRegs_t *)0xE001C000)
161 #define I2CONSET I2C->conset /* Control Set Register */
162 #define I2STAT I2C->stat /* Status Register */
163 #define I2DAT I2C->dat /* Data Register */
164 #define I2ADR I2C->adr /* Slave Address Register */
165 #define I2SCLH I2C->sclh /* SCL Duty Cycle Register (high half word) */
166 #define I2SCLL I2C->scll /* SCL Duty Cycle Register (low half word) */
167 #define I2CONCLR I2C->conclr /* Control Clear Register */
169 ///////////////////////////////////////////////////////////////////////////////
170 // Serial Peripheral Interface 0 (SPI0)
171 #define SPI0 ((spiRegs_t *)0xE0020000)
174 #define S0SPCR SPI0->cr /* Control Register */
175 #define S0SPSR SPI0->sr /* Status Register */
176 #define S0SPDR SPI0->dr /* Data Register */
177 #define S0SPCCR SPI0->ccr /* Clock Counter Register */
178 #define S0SPINT SPI0->flag /* Interrupt Flag Register */
180 ///////////////////////////////////////////////////////////////////////////////
181 // Serial Peripheral Interface 1 (SPI1)
182 #define SPI1 ((spiRegs_t *)0xE0030000)
185 #define S1SPCR SPI1->cr /* Control Register */
186 #define S1SPSR SPI1->sr /* Status Register */
187 #define S1SPDR SPI1->dr /* Data Register */
188 #define S1SPCCR SPI1->ccr /* Clock Counter Register */
189 #define S1SPINT SPI1->flag /* Interrupt Flag Register */
191 ///////////////////////////////////////////////////////////////////////////////
193 #define RTC ((rtcRegs_t *)0xE0024000)
196 #define RTCILR RTC->ilr /* Interrupt Location Register */
197 #define RTCCTC RTC->ctc /* Clock Tick Counter */
198 #define RTCCCR RTC->ccr /* Clock Control Register */
199 #define RTCCIIR RTC->ciir /* Counter Increment Interrupt Register */
200 #define RTCAMR RTC->amr /* Alarm Mask Register */
201 #define RTCCTIME0 RTC->ctime0 /* Consolidated Time Register 0 */
202 #define RTCCTIME1 RTC->ctime1 /* Consolidated Time Register 1 */
203 #define RTCCTIME2 RTC->ctime2 /* Consolidated Time Register 2 */
204 #define RTCSEC RTC->sec /* Seconds Register */
205 #define RTCMIN RTC->min /* Minutes Register */
206 #define RTCHOUR RTC->hour /* Hours Register */
207 #define RTCDOM RTC->dom /* Day Of Month Register */
208 #define RTCDOW RTC->dow /* Day Of Week Register */
209 #define RTCDOY RTC->doy /* Day Of Year Register */
210 #define RTCMONTH RTC->month /* Months Register */
211 #define RTCYEAR RTC->year /* Years Register */
212 #define RTCALSEC RTC->alsec /* Alarm Seconds Register */
213 #define RTCALMIN RTC->almin /* Alarm Minutes Register */
214 #define RTCALHOUR RTC->alhour /* Alarm Hours Register */
215 #define RTCALDOM RTC->aldom /* Alarm Day Of Month Register */
216 #define RTCALDOW RTC->aldow /* Alarm Day Of Week Register */
217 #define RTCALDOY RTC->aldoy /* Alarm Day Of Year Register */
218 #define RTCALMON RTC->almon /* Alarm Months Register */
219 #define RTCALYEAR RTC->alyear /* Alarm Years Register */
220 #define RTCPREINT RTC->preint /* Prescale Value Register (integer) */
221 #define RTCPREFRAC RTC->prefrac /* Prescale Value Register (fraction) */
223 ///////////////////////////////////////////////////////////////////////////////
224 // General Purpose Input/Output
225 #define GPIO ((gpioRegs_t *)0xE0028000)
228 #define IO0PIN GPIO->in0 /* P0 Pin Value Register */
229 #define IO0SET GPIO->set0 /* P0 Pin Output Set Register */
230 #define IO0DIR GPIO->dir0 /* P0 Pin Direction Register */
231 #define IO0CLR GPIO->clr0 /* P0 Pin Output Clear Register */
232 #define IO1PIN GPIO->in1 /* P1 Pin Value Register */
233 #define IO1SET GPIO->set1 /* P1 Pin Output Set Register */
234 #define IO1DIR GPIO->dir1 /* P1 Pin Direction Register */
235 #define IO1CLR GPIO->clr1 /* P1 Pin Output Clear Register */
237 ///////////////////////////////////////////////////////////////////////////////
239 #define PINSEL ((pinRegs_t *)0xE002C000)
241 // Pin Connect Block Registers
242 #define PINSEL0 PINSEL->sel0 /* Pin Function Select Register 0 */
243 #define PINSEL1 PINSEL->sel1 /* Pin Function Select Register 1 */
244 #define PINSEL2 PINSEL->sel2 /* Pin Function Select Register 2 */
246 ///////////////////////////////////////////////////////////////////////////////
248 #define ADC ((adcRegs_t *)0xE0034000)
250 // A/D Converter Registers
251 #define ADCR ADC->cr /* Control Register */
252 #define ADDR ADC->dr /* Data Register */
254 ///////////////////////////////////////////////////////////////////////////////
255 // System Contol Block
256 #define SCB ((scbRegs_t *)0xE01FC000)
258 // Memory Accelerator Module Registers (MAM)
259 #define MAMCR SCB->mam.cr /* Control Register */
260 #define MAMTIM SCB->mam.tim /* Timing Control Register */
262 // Memory Mapping Control Register
263 #define MEMMAP SCB->memmap
265 // Phase Locked Loop Registers (PLL)
266 #define PLLCON SCB->pll.con /* Control Register */
267 #define PLLCFG SCB->pll.cfg /* Configuration Register */
268 #define PLLSTAT SCB->pll.stat /* Status Register */
269 #define PLLFEED SCB->pll.feed /* Feed Register */
271 // Power Control Registers
272 #define PCON SCB->p.con /* Control Register */
273 #define PCONP SCB->p.conp /* Peripherals Register */
275 // VPB Divider Register
276 #define VPBDIV SCB->vpbdiv
278 // External Interrupt Registers
279 #define EXTINT SCB->ext.flag /* Flag Register */
280 #define EXTWAKE SCB->ext.wake /* Wakeup Register */
281 #define EXTMODE SCB->ext.mode /* Mode Register */
282 #define EXTPOLAR SCB->ext.polar /* Polarity Register */
284 ///////////////////////////////////////////////////////////////////////////////
285 // Vectored Interrupt Controller
286 #define VIC ((vicRegs_t *)0xFFFFF000)
288 // Vectored Interrupt Controller Registers
289 #define VICIRQStatus VIC->irqStatus /* IRQ Status Register */
290 #define VICFIQStatus VIC->fiqStatus /* FIQ Status Register */
291 #define VICRawIntr VIC->rawIntr /* Raw Interrupt Status Register */
292 #define VICIntSelect VIC->intSelect /* Interrupt Select Register */
293 #define VICIntEnable VIC->intEnable /* Interrupt Enable Register */
294 #define VICIntEnClear VIC->intEnClear /* Interrupt Enable Clear Register */
295 #define VICSoftInt VIC->softInt /* Software Interrupt Register */
296 #define VICSoftIntClear VIC->softIntClear /* Software Interrupt Clear Register */
297 #define VICProtection VIC->protection /* Protection Enable Register */
298 #define VICVectAddr VIC->vectAddr /* Vector Address Register */
299 #define VICDefVectAddr VIC->defVectAddr /* Default Vector Address Register */
300 #define VICVectAddr0 VIC->vectAddr0 /* Vector Address 0 Register */
301 #define VICVectAddr1 VIC->vectAddr1 /* Vector Address 1 Register */
302 #define VICVectAddr2 VIC->vectAddr2 /* Vector Address 2 Register */
303 #define VICVectAddr3 VIC->vectAddr3 /* Vector Address 3 Register */
304 #define VICVectAddr4 VIC->vectAddr4 /* Vector Address 4 Register */
305 #define VICVectAddr5 VIC->vectAddr5 /* Vector Address 5 Register */
306 #define VICVectAddr6 VIC->vectAddr6 /* Vector Address 6 Register */
307 #define VICVectAddr7 VIC->vectAddr7 /* Vector Address 7 Register */
308 #define VICVectAddr8 VIC->vectAddr8 /* Vector Address 8 Register */
309 #define VICVectAddr9 VIC->vectAddr9 /* Vector Address 9 Register */
310 #define VICVectAddr10 VIC->vectAddr10 /* Vector Address 10 Register */
311 #define VICVectAddr11 VIC->vectAddr11 /* Vector Address 11 Register */
312 #define VICVectAddr12 VIC->vectAddr12 /* Vector Address 12 Register */
313 #define VICVectAddr13 VIC->vectAddr13 /* Vector Address 13 Register */
314 #define VICVectAddr14 VIC->vectAddr14 /* Vector Address 14 Register */
315 #define VICVectAddr15 VIC->vectAddr15 /* Vector Address 15 Register */
316 #define VICVectCntl0 VIC->vectCntl0 /* Vector Control 0 Register */
317 #define VICVectCntl1 VIC->vectCntl1 /* Vector Control 1 Register */
318 #define VICVectCntl2 VIC->vectCntl2 /* Vector Control 2 Register */
319 #define VICVectCntl3 VIC->vectCntl3 /* Vector Control 3 Register */
320 #define VICVectCntl4 VIC->vectCntl4 /* Vector Control 4 Register */
321 #define VICVectCntl5 VIC->vectCntl5 /* Vector Control 5 Register */
322 #define VICVectCntl6 VIC->vectCntl6 /* Vector Control 6 Register */
323 #define VICVectCntl7 VIC->vectCntl7 /* Vector Control 7 Register */
324 #define VICVectCntl8 VIC->vectCntl8 /* Vector Control 8 Register */
325 #define VICVectCntl9 VIC->vectCntl9 /* Vector Control 9 Register */
326 #define VICVectCntl10 VIC->vectCntl10 /* Vector Control 10 Register */
327 #define VICVectCntl11 VIC->vectCntl11 /* Vector Control 11 Register */
328 #define VICVectCntl12 VIC->vectCntl12 /* Vector Control 12 Register */
329 #define VICVectCntl13 VIC->vectCntl13 /* Vector Control 13 Register */
330 #define VICVectCntl14 VIC->vectCntl14 /* Vector Control 14 Register */
331 #define VICVectCntl15 VIC->vectCntl15 /* Vector Control 15 Register */