20 #define ARM_cpsr uregs[16]
21 #define ARM_pc uregs[15]
22 #define ARM_lr uregs[14]
23 #define ARM_sp uregs[13]
24 #define ARM_ip uregs[12]
25 #define ARM_fp uregs[11]
26 #define ARM_r10 uregs[10]
27 #define ARM_r9 uregs[9]
28 #define ARM_r8 uregs[8]
29 #define ARM_r7 uregs[7]
30 #define ARM_r6 uregs[6]
31 #define ARM_r5 uregs[5]
32 #define ARM_r4 uregs[4]
33 #define ARM_r3 uregs[3]
34 #define ARM_r2 uregs[2]
35 #define ARM_r1 uregs[1]
36 #define ARM_r0 uregs[0]
37 #define ARM_ORIG_r0 uregs[17]
40 struct undef_hook *next;
41 unsigned long instr_mask;
42 unsigned long instr_val;
43 unsigned long cpsr_mask;
44 unsigned long cpsr_val;
45 int (*fn)(struct pt_regs *regs, unsigned int instr);
48 int register_undef_hook(struct undef_hook *hook);
52 typedef struct irq_handler {
53 void (*handler)(int, void *, struct pt_regs *);
57 struct irq_handler *next;
61 #define IRQH_ON_LIST 0x100 /* handler is used */
63 extern irq_handler_t *irq_array[NR_IRQS];
64 extern void *irq_vec[NR_IRQS];
66 int add_irq_handler(int vectno,irq_handler_t *handler);
68 int del_irq_handler(int vectno,irq_handler_t *handler);
70 int test_irq_handler(int vectno,const irq_handler_t *handler);
72 void irq_redirect2vector(int vectno,struct pt_regs *regs);
74 /* IRQ handling code */
79 __asm__ __volatile__( \
80 "mrs %0, cpsr @ sti\n" \
81 " bic %0, %0, #128\n" \
91 __asm__ __volatile__( \
92 "mrs %0, cpsr @ cli\n" \
93 " orr %0, %0, #128\n" \
100 #define save_and_cli(flags) \
102 unsigned long temp; \
103 (void) (&temp == &flags); \
104 __asm__ __volatile__( \
105 "mrs %0, cpsr @ save_and_cli\n" \
106 " orr %1, %0, #128\n" \
108 : "=r" (flags), "=r" (temp) \
113 #define save_flags(flags) \
115 __asm__ __volatile__( \
116 "mrs %0, cpsr @ save_flags\n" \
122 #define restore_flags(flags) \
123 __asm__ __volatile__( \
124 "msr cpsr_c, %0 @ restore_flags\n" \
130 /* FIQ handling code */
134 unsigned long temp; \
135 __asm__ __volatile__( \
136 "mrs %0, cpsr @ sti\n" \
137 " bic %0, %0, #64\n" \
146 unsigned long temp; \
147 __asm__ __volatile__( \
148 "mrs %0, cpsr @ cli\n" \
149 " orr %0, %0, #64\n" \
156 #define fiq_save_and_cli(flags) \
158 unsigned long temp; \
159 (void) (&temp == &flags); \
160 __asm__ __volatile__( \
161 "mrs %0, cpsr @ save_and_cli\n" \
162 " orr %1, %0, #192\n" \
164 : "=r" (flags), "=r" (temp) \
169 void __cpu_coherent_range(unsigned long start, unsigned long end);
171 static inline void flush_icache_range(unsigned long start, unsigned long end)
173 __cpu_coherent_range(start, end);
176 /* atomic access routines */
178 //typedef unsigned long atomic_t;
180 static inline void atomic_clear_mask(unsigned long mask, volatile unsigned long *addr)
186 restore_flags(flags);
189 static inline void atomic_set_mask(unsigned long mask, volatile unsigned long *addr)
195 restore_flags(flags);
198 static inline void set_bit(int nr, volatile unsigned long *addr)
204 restore_flags(flags);
207 static inline void clear_bit(int nr, volatile unsigned long *addr)
213 restore_flags(flags);
216 static inline int test_bit(int nr, volatile unsigned long *addr)
218 return ((*addr) & (1<<nr))?1:0;
221 static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
230 restore_flags(flags);
234 #define __memory_barrier() \
235 __asm__ __volatile__("": : : "memory")
237 /*masked fields macros*/
239 #define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask))
240 #define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1)))
242 static inline void outb(unsigned int port, int val) {
243 *(volatile unsigned char *)(port)=val;
246 static inline unsigned char inb(unsigned int port) {
247 return *(volatile unsigned char *)(port);
250 #endif /* _ARM_CPU_DEF_H */