core: Allow writing to more PCI config space registers

Enable write access to the Master Latency Timer (non-functional for
PCIe) and the Cacheline Size (no misuse potential identified).

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>

diff --git a/hypervisor/pci.c b/hypervisor/pci.c
index df8383c8419d76bdd89f55b24349cf61c4155eb8..b7f6a457a2675fd30c2c1938beef67783d38ff74 100644 (file)
--- a/hypervisor/pci.c
+++ b/hypervisor/pci.c
@@ -40,13 +40,13 @@ struct pci_cfg_access {
 /* Type 1: Endpoints */
 static const struct pci_cfg_access endpoint_write_access[] = {
        { 0x04, 0xffffffff }, /* Command, Status */
-       { 0x0c, 0xff000000 }, /* BIST */
+       { 0x0c, 0xff00ffff }, /* BIST, Latency Timer, Cacheline */
        { 0x3c, 0x000000ff }, /* Int Line */
 };
 /* Type 2: Bridges */
 static const struct pci_cfg_access bridge_write_access[] = {
        { 0x04, 0xffffffff }, /* Command, Status */
-       { 0x0c, 0xff000000 }, /* BIST */
+       { 0x0c, 0xff00ffff }, /* BIST, Latency Timer, Cacheline */
        { 0x3c, 0xffff00ff }, /* Int Line, Bridge Control */
 };